2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007 MIPS Technologies, Inc.
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Korey Sewell
46 #include "arch/utility.hh"
47 #include "base/bigint.hh"
48 #include "config/the_isa.hh"
49 #include "cpu/inorder/resources/cache_unit.hh"
50 #include "cpu/inorder/resources/resource_list.hh"
51 #include "cpu/inorder/cpu.hh"
52 #include "cpu/inorder/first_stage.hh"
53 #include "cpu/inorder/inorder_dyn_inst.hh"
54 #include "cpu/inorder/pipeline_traits.hh"
55 #include "cpu/inorder/resource_pool.hh"
56 #include "cpu/inorder/thread_context.hh"
57 #include "cpu/inorder/thread_state.hh"
58 #include "cpu/activity.hh"
59 #include "cpu/base.hh"
60 #include "cpu/exetrace.hh"
61 #include "cpu/quiesce_event.hh"
62 #include "cpu/simple_thread.hh"
63 #include "cpu/thread_context.hh"
64 #include "debug/Activity.hh"
65 #include "debug/InOrderCPU.hh"
66 #include "debug/InOrderCachePort.hh"
67 #include "debug/Interrupt.hh"
68 #include "debug/Quiesce.hh"
69 #include "debug/RefCount.hh"
70 #include "debug/SkedCache.hh"
71 #include "params/InOrderCPU.hh"
72 #include "sim/full_system.hh"
73 #include "sim/process.hh"
74 #include "sim/stat_control.hh"
75 #include "sim/system.hh"
77 #if THE_ISA == ALPHA_ISA
78 #include "arch/alpha/osfpal.hh"
82 using namespace TheISA
;
83 using namespace ThePipeline
;
85 InOrderCPU::CachePort::CachePort(CacheUnit
*_cacheUnit
) :
86 CpuPort(_cacheUnit
->name() + "-cache-port", _cacheUnit
->cpu
),
91 InOrderCPU::CachePort::recvTiming(Packet
*pkt
)
94 DPRINTF(InOrderCachePort
, "Got error packet back for address: %x\n",
96 else if (pkt
->isResponse())
97 cacheUnit
->processCacheCompletion(pkt
);
99 //@note: depending on consistency model, update here
100 DPRINTF(InOrderCachePort
, "Received snoop pkt %x,Ignoring\n",
108 InOrderCPU::CachePort::recvRetry()
110 cacheUnit
->recvRetry();
113 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
114 : Event(CPU_Tick_Pri
), cpu(c
)
119 InOrderCPU::TickEvent::process()
126 InOrderCPU::TickEvent::description() const
128 return "InOrderCPU tick event";
131 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
132 Fault fault
, ThreadID _tid
, DynInstPtr inst
,
133 CPUEventPri event_pri
)
134 : Event(event_pri
), cpu(_cpu
)
136 setEvent(e_type
, fault
, _tid
, inst
);
140 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
143 "ActivateNextReadyThread",
149 "SquashFromMemStall",
154 InOrderCPU::CPUEvent::process()
156 switch (cpuEventType
)
159 cpu
->activateThread(tid
);
160 cpu
->resPool
->activateThread(tid
);
163 case ActivateNextReadyThread
:
164 cpu
->activateNextReadyThread();
167 case DeactivateThread
:
168 cpu
->deactivateThread(tid
);
169 cpu
->resPool
->deactivateThread(tid
);
173 cpu
->haltThread(tid
);
174 cpu
->resPool
->deactivateThread(tid
);
178 cpu
->suspendThread(tid
);
179 cpu
->resPool
->suspendThread(tid
);
182 case SquashFromMemStall
:
183 cpu
->squashDueToMemStall(inst
->squashingStage
, inst
->seqNum
, tid
);
184 cpu
->resPool
->squashDueToMemStall(inst
, inst
->squashingStage
,
189 DPRINTF(InOrderCPU
, "Trapping CPU\n");
190 cpu
->trap(fault
, tid
, inst
);
191 cpu
->resPool
->trap(fault
, tid
, inst
);
192 cpu
->trapPending
[tid
] = false;
196 cpu
->syscall(inst
->syscallNum
, tid
);
197 cpu
->resPool
->trap(fault
, tid
, inst
);
201 fatal("Unrecognized Event Type %s", eventNames
[cpuEventType
]);
204 cpu
->cpuEventRemoveList
.push(this);
210 InOrderCPU::CPUEvent::description() const
212 return "InOrderCPU event";
216 InOrderCPU::CPUEvent::scheduleEvent(int delay
)
218 assert(!scheduled() || squashed());
219 cpu
->reschedule(this, cpu
->nextCycle(curTick() + cpu
->ticks(delay
)), true);
223 InOrderCPU::CPUEvent::unscheduleEvent()
229 InOrderCPU::InOrderCPU(Params
*params
)
231 cpu_id(params
->cpu_id
),
235 stageWidth(params
->stageWidth
),
236 resPool(new ResourcePool(this, params
)),
238 dataPort(resPool
->getDataUnit()),
239 instPort(resPool
->getInstUnit()),
240 removeInstsThisCycle(false),
241 activityRec(params
->name
, NumStages
, 10, params
->activity
),
242 system(params
->system
),
248 deferRegistration(false/*params->deferRegistration*/),
249 stageTracing(params
->stageTracing
),
255 // Resize for Multithreading CPUs
256 thread
.resize(numThreads
);
258 ThreadID active_threads
= params
->workload
.size();
262 active_threads
= params
->workload
.size();
264 if (active_threads
> MaxThreads
) {
265 panic("Workload Size too large. Increase the 'MaxThreads'"
266 "in your InOrder implementation or "
267 "edit your workload size.");
271 if (active_threads
> 1) {
272 threadModel
= (InOrderCPU::ThreadModel
) params
->threadModel
;
274 if (threadModel
== SMT
) {
275 DPRINTF(InOrderCPU
, "Setting Thread Model to SMT.\n");
276 } else if (threadModel
== SwitchOnCacheMiss
) {
277 DPRINTF(InOrderCPU
, "Setting Thread Model to "
278 "Switch On Cache Miss\n");
282 threadModel
= Single
;
286 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
288 lastCommittedPC
[tid
].set(0);
291 // SMT is not supported in FS mode yet.
292 assert(numThreads
== 1);
293 thread
[tid
] = new Thread(this, 0, NULL
);
295 if (tid
< (ThreadID
)params
->workload
.size()) {
296 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
297 tid
, params
->workload
[tid
]->prog_fname
);
299 new Thread(this, tid
, params
->workload
[tid
]);
301 //Allocate Empty thread so M5 can use later
302 //when scheduling threads to CPU
303 Process
* dummy_proc
= params
->workload
[0];
304 thread
[tid
] = new Thread(this, tid
, dummy_proc
);
307 // Eventually set this with parameters...
311 // Setup the TC that will serve as the interface to the threads/CPU.
312 InOrderThreadContext
*tc
= new InOrderThreadContext
;
314 tc
->thread
= thread
[tid
];
316 // Setup quiesce event.
317 this->thread
[tid
]->quiesceEvent
= new EndQuiesceEvent(tc
);
319 // Give the thread the TC.
320 thread
[tid
]->tc
= tc
;
321 thread
[tid
]->setFuncExeInst(0);
322 globalSeqNum
[tid
] = 1;
324 // Add the TC to the CPU's list of TC's.
325 this->threadContexts
.push_back(tc
);
328 // Initialize TimeBuffer Stage Queues
329 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
330 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
331 stageQueue
[stNum
]->id(stNum
);
335 // Set Up Pipeline Stages
336 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
338 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
340 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
342 pipelineStage
[stNum
]->setCPU(this);
343 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
344 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
346 // Take Care of 1st/Nth stages
348 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
349 if (stNum
< NumStages
- 1)
350 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
353 // Initialize thread specific variables
354 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
355 archRegDepMap
[tid
].setCPU(this);
357 nonSpecInstActive
[tid
] = false;
358 nonSpecSeqNum
[tid
] = 0;
360 squashSeqNum
[tid
] = MaxAddr
;
361 lastSquashCycle
[tid
] = 0;
363 memset(intRegs
[tid
], 0, sizeof(intRegs
[tid
]));
364 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
367 // Define dummy instructions and resource requests to be used.
368 dummyInst
[tid
] = new InOrderDynInst(this,
374 dummyReq
[tid
] = new ResourceRequest(resPool
->getResource(0));
378 // Use this dummy inst to force squashing behind every instruction
380 dummyTrapInst
[tid
] = new InOrderDynInst(this, NULL
, 0, 0, 0);
381 dummyTrapInst
[tid
]->seqNum
= 0;
382 dummyTrapInst
[tid
]->squashSeqNum
= 0;
383 dummyTrapInst
[tid
]->setTid(tid
);
386 trapPending
[tid
] = false;
390 dummyReqInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
391 dummyReqInst
->setSquashed();
392 dummyReqInst
->resetInstCount();
394 dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
395 dummyBufferInst
->setSquashed();
396 dummyBufferInst
->resetInstCount();
398 endOfSkedIt
= skedCache
.end();
399 frontEndSked
= createFrontEndSked();
400 faultSked
= createFaultSked();
402 lastRunningCycle
= curTick();
407 // Schedule First Tick Event, CPU will reschedule itself from here on out.
408 scheduleTickEvent(0);
411 InOrderCPU::~InOrderCPU()
415 SkedCacheIt sked_it
= skedCache
.begin();
416 SkedCacheIt sked_end
= skedCache
.end();
418 while (sked_it
!= sked_end
) {
419 delete (*sked_it
).second
;
425 m5::hash_map
<InOrderCPU::SkedID
, ThePipeline::RSkedPtr
> InOrderCPU::skedCache
;
428 InOrderCPU::createFrontEndSked()
430 RSkedPtr res_sked
= new ResourceSked();
432 StageScheduler
F(res_sked
, stage_num
++);
433 StageScheduler
D(res_sked
, stage_num
++);
436 F
.needs(FetchSeq
, FetchSeqUnit::AssignNextPC
);
437 F
.needs(ICache
, FetchUnit::InitiateFetch
);
440 D
.needs(ICache
, FetchUnit::CompleteFetch
);
441 D
.needs(Decode
, DecodeUnit::DecodeInst
);
442 D
.needs(BPred
, BranchPredictor::PredictBranch
);
443 D
.needs(FetchSeq
, FetchSeqUnit::UpdateTargetPC
);
446 DPRINTF(SkedCache
, "Resource Sked created for instruction Front End\n");
452 InOrderCPU::createFaultSked()
454 RSkedPtr res_sked
= new ResourceSked();
455 StageScheduler
W(res_sked
, NumStages
- 1);
456 W
.needs(Grad
, GraduationUnit::CheckFault
);
457 DPRINTF(SkedCache
, "Resource Sked created for instruction Faults\n");
462 InOrderCPU::createBackEndSked(DynInstPtr inst
)
464 RSkedPtr res_sked
= lookupSked(inst
);
465 if (res_sked
!= NULL
) {
466 DPRINTF(SkedCache
, "Found %s in sked cache.\n",
470 res_sked
= new ResourceSked();
473 int stage_num
= ThePipeline::BackEndStartStage
;
474 StageScheduler
X(res_sked
, stage_num
++);
475 StageScheduler
M(res_sked
, stage_num
++);
476 StageScheduler
W(res_sked
, stage_num
++);
478 if (!inst
->staticInst
) {
479 warn_once("Static Instruction Object Not Set. Can't Create"
480 " Back End Schedule");
485 X
.needs(RegManager
, UseDefUnit::MarkDestRegs
);
486 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
487 if (!idx
|| !inst
->isStore()) {
488 X
.needs(RegManager
, UseDefUnit::ReadSrcReg
, idx
);
492 //@todo: schedule non-spec insts to operate on this cycle
493 // as long as all previous insts are done
494 if ( inst
->isNonSpeculative() ) {
495 // skip execution of non speculative insts until later
496 } else if ( inst
->isMemRef() ) {
497 if ( inst
->isLoad() ) {
498 X
.needs(AGEN
, AGENUnit::GenerateAddr
);
500 } else if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
501 X
.needs(MDU
, MultDivUnit::StartMultDiv
);
503 X
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
507 if (!inst
->isNonSpeculative()) {
508 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
509 M
.needs(MDU
, MultDivUnit::EndMultDiv
);
512 if ( inst
->isLoad() ) {
513 M
.needs(DCache
, CacheUnit::InitiateReadData
);
515 M
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
516 } else if ( inst
->isStore() ) {
517 for (int i
= 1; i
< inst
->numSrcRegs(); i
++ ) {
518 M
.needs(RegManager
, UseDefUnit::ReadSrcReg
, i
);
520 M
.needs(AGEN
, AGENUnit::GenerateAddr
);
521 M
.needs(DCache
, CacheUnit::InitiateWriteData
);
523 M
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
528 if (!inst
->isNonSpeculative()) {
529 if ( inst
->isLoad() ) {
530 W
.needs(DCache
, CacheUnit::CompleteReadData
);
532 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
533 } else if ( inst
->isStore() ) {
534 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
536 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
539 // Finally, Execute Speculative Data
540 if (inst
->isMemRef()) {
541 if (inst
->isLoad()) {
542 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
543 W
.needs(DCache
, CacheUnit::InitiateReadData
);
545 W
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
546 W
.needs(DCache
, CacheUnit::CompleteReadData
);
548 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
549 } else if (inst
->isStore()) {
550 if ( inst
->numSrcRegs() >= 2 ) {
551 W
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
553 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
554 W
.needs(DCache
, CacheUnit::InitiateWriteData
);
556 W
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
557 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
559 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
562 W
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
566 W
.needs(Grad
, GraduationUnit::CheckFault
);
568 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
569 W
.needs(RegManager
, UseDefUnit::WriteDestReg
, idx
);
572 if (inst
->isControl())
573 W
.needs(BPred
, BranchPredictor::UpdatePredictor
);
575 W
.needs(Grad
, GraduationUnit::GraduateInst
);
577 // Insert Back Schedule into our cache of
578 // resource schedules
579 addToSkedCache(inst
, res_sked
);
581 DPRINTF(SkedCache
, "Back End Sked Created for instruction: %s (%08p)\n",
582 inst
->instName(), inst
->getMachInst());
589 InOrderCPU::regStats()
591 /* Register the Resource Pool's stats here.*/
594 /* Register for each Pipeline Stage */
595 for (int stage_num
=0; stage_num
< ThePipeline::NumStages
; stage_num
++) {
596 pipelineStage
[stage_num
]->regStats();
599 /* Register any of the InOrderCPU's stats here.*/
601 .name(name() + ".instsPerContextSwitch")
602 .desc("Instructions Committed Per Context Switch")
603 .prereq(instsPerCtxtSwitch
);
606 .name(name() + ".contextSwitches")
607 .desc("Number of context switches");
610 .name(name() + ".comLoads")
611 .desc("Number of Load instructions committed");
614 .name(name() + ".comStores")
615 .desc("Number of Store instructions committed");
618 .name(name() + ".comBranches")
619 .desc("Number of Branches instructions committed");
622 .name(name() + ".comNops")
623 .desc("Number of Nop instructions committed");
626 .name(name() + ".comNonSpec")
627 .desc("Number of Non-Speculative instructions committed");
630 .name(name() + ".comInts")
631 .desc("Number of Integer instructions committed");
634 .name(name() + ".comFloats")
635 .desc("Number of Floating Point instructions committed");
638 .name(name() + ".timesIdled")
639 .desc("Number of times that the entire CPU went into an idle state and"
640 " unscheduled itself")
644 .name(name() + ".idleCycles")
645 .desc("Number of cycles cpu's stages were not processed");
648 .name(name() + ".runCycles")
649 .desc("Number of cycles cpu stages are processed.");
652 .name(name() + ".activity")
653 .desc("Percentage of cycles cpu is active")
655 activity
= (runCycles
/ numCycles
) * 100;
659 .name(name() + ".threadCycles")
660 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
663 .name(name() + ".smtCycles")
664 .desc("Total number of cycles that the CPU was in SMT-mode");
668 .name(name() + ".committedInsts")
669 .desc("Number of Instructions committed (Per-Thread)");
673 .name(name() + ".committedOps")
674 .desc("Number of Ops committed (Per-Thread)");
678 .name(name() + ".smtCommittedInsts")
679 .desc("Number of SMT Instructions committed (Per-Thread)");
682 .name(name() + ".committedInsts_total")
683 .desc("Number of Instructions committed (Total)");
686 .name(name() + ".cpi")
687 .desc("CPI: Cycles Per Instruction (Per-Thread)")
689 cpi
= numCycles
/ committedInsts
;
692 .name(name() + ".smt_cpi")
693 .desc("CPI: Total SMT-CPI")
695 smtCpi
= smtCycles
/ smtCommittedInsts
;
698 .name(name() + ".cpi_total")
699 .desc("CPI: Total CPI of All Threads")
701 totalCpi
= numCycles
/ totalCommittedInsts
;
704 .name(name() + ".ipc")
705 .desc("IPC: Instructions Per Cycle (Per-Thread)")
707 ipc
= committedInsts
/ numCycles
;
710 .name(name() + ".smt_ipc")
711 .desc("IPC: Total SMT-IPC")
713 smtIpc
= smtCommittedInsts
/ smtCycles
;
716 .name(name() + ".ipc_total")
717 .desc("IPC: Total IPC of All Threads")
719 totalIpc
= totalCommittedInsts
/ numCycles
;
728 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
732 checkForInterrupts();
734 bool pipes_idle
= true;
735 //Tick each of the stages
736 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
737 pipelineStage
[stNum
]->tick();
739 pipes_idle
= pipes_idle
&& pipelineStage
[stNum
]->idle
;
747 // Now advance the time buffers one tick
748 timeBuffer
.advance();
749 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
750 stageQueue
[sqNum
]->advance();
752 activityRec
.advance();
754 // Any squashed events, or insts then remove them now
755 cleanUpRemovedEvents();
756 cleanUpRemovedInsts();
758 // Re-schedule CPU for this cycle
759 if (!tickEvent
.scheduled()) {
760 if (_status
== SwitchedOut
) {
762 lastRunningCycle
= curTick();
763 } else if (!activityRec
.active()) {
764 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
765 lastRunningCycle
= curTick();
768 //Tick next_tick = curTick() + cycles(1);
769 //tickEvent.schedule(next_tick);
770 schedule(&tickEvent
, nextCycle(curTick() + 1));
771 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n",
772 nextCycle(curTick() + 1));
777 updateThreadPriority();
784 if (!deferRegistration
) {
785 registerThreadContexts();
788 // Set inSyscall so that the CPU doesn't squash when initially
789 // setting up registers.
790 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
791 thread
[tid
]->inSyscall
= true;
794 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
795 ThreadContext
*src_tc
= threadContexts
[tid
];
796 TheISA::initCPU(src_tc
, src_tc
->contextId());
797 // Initialise the ThreadContext's memory proxies
798 thread
[tid
]->initMemProxies(thread
[tid
]->getTC());
803 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
804 thread
[tid
]->inSyscall
= false;
806 // Call Initializiation Routine for Resource Pool
811 InOrderCPU::hwrei(ThreadID tid
)
813 #if THE_ISA == ALPHA_ISA
814 // Need to clear the lock flag upon returning from an interrupt.
815 setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG
, false, tid
);
817 thread
[tid
]->kernelStats
->hwrei();
818 // FIXME: XXX check for interrupts? XXX
826 InOrderCPU::simPalCheck(int palFunc
, ThreadID tid
)
828 #if THE_ISA == ALPHA_ISA
829 if (this->thread
[tid
]->kernelStats
)
830 this->thread
[tid
]->kernelStats
->callpal(palFunc
,
831 this->threadContexts
[tid
]);
836 if (--System::numSystemsRunning
== 0)
837 exitSimLoop("all cpus halted");
842 if (this->system
->breakpoint())
851 InOrderCPU::checkForInterrupts()
853 for (int i
= 0; i
< threadContexts
.size(); i
++) {
854 ThreadContext
*tc
= threadContexts
[i
];
856 if (interrupts
->checkInterrupts(tc
)) {
857 Fault interrupt
= interrupts
->getInterrupt(tc
);
859 if (interrupt
!= NoFault
) {
860 DPRINTF(Interrupt
, "Processing Intterupt for [tid:%i].\n",
863 ThreadID tid
= tc
->threadId();
864 interrupts
->updateIntrInfo(tc
);
866 // Squash from Last Stage in Pipeline
867 unsigned last_stage
= NumStages
- 1;
868 dummyTrapInst
[tid
]->squashingStage
= last_stage
;
869 pipelineStage
[last_stage
]->setupSquash(dummyTrapInst
[tid
],
872 // By default, setupSquash will always squash from stage + 1
873 pipelineStage
[BackEndStartStage
- 1]->setupSquash(dummyTrapInst
[tid
],
876 // Schedule Squash Through-out Resource Pool
877 resPool
->scheduleEvent(
878 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
,
879 dummyTrapInst
[tid
], 0);
881 // Finally, Setup Trap to happen at end of cycle
882 trapContext(interrupt
, tid
, dummyTrapInst
[tid
]);
889 InOrderCPU::getInterrupts()
891 // Check if there are any outstanding interrupts
892 return interrupts
->getInterrupt(threadContexts
[0]);
896 InOrderCPU::processInterrupts(Fault interrupt
)
898 // Check for interrupts here. For now can copy the code that
899 // exists within isa_fullsys_traits.hh. Also assume that thread 0
900 // is the one that handles the interrupts.
901 // @todo: Possibly consolidate the interrupt checking code.
902 // @todo: Allow other threads to handle interrupts.
904 assert(interrupt
!= NoFault
);
905 interrupts
->updateIntrInfo(threadContexts
[0]);
907 DPRINTF(InOrderCPU
, "Interrupt %s being handled\n", interrupt
->name());
909 // Note: Context ID ok here? Impl. of FS mode needs to revisit this
910 trap(interrupt
, threadContexts
[0]->contextId(), dummyBufferInst
);
914 InOrderCPU::trapContext(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
916 scheduleCpuEvent(Trap
, fault
, tid
, inst
, delay
);
917 trapPending
[tid
] = true;
921 InOrderCPU::trap(Fault fault
, ThreadID tid
, DynInstPtr inst
)
923 fault
->invoke(tcBase(tid
), inst
->staticInst
);
924 removePipelineStalls(tid
);
928 InOrderCPU::squashFromMemStall(DynInstPtr inst
, ThreadID tid
, int delay
)
930 scheduleCpuEvent(SquashFromMemStall
, NoFault
, tid
, inst
, delay
);
935 InOrderCPU::squashDueToMemStall(int stage_num
, InstSeqNum seq_num
,
938 DPRINTF(InOrderCPU
, "Squashing Pipeline Stages Due to Memory Stall...\n");
940 // Squash all instructions in each stage including
941 // instruction that caused the squash (seq_num - 1)
942 // NOTE: The stage bandwidth needs to be cleared so thats why
943 // the stalling instruction is squashed as well. The stalled
944 // instruction is previously placed in another intermediate buffer
945 // while it's stall is being handled.
946 InstSeqNum squash_seq_num
= seq_num
- 1;
948 for (int stNum
=stage_num
; stNum
>= 0 ; stNum
--) {
949 pipelineStage
[stNum
]->squashDueToMemStall(squash_seq_num
, tid
);
954 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
955 ThreadID tid
, DynInstPtr inst
,
956 unsigned delay
, CPUEventPri event_pri
)
958 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, inst
,
961 Tick sked_tick
= nextCycle(curTick() + ticks(delay
));
963 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
964 eventNames
[c_event
], curTick() + delay
, tid
);
965 schedule(cpu_event
, sked_tick
);
967 cpu_event
->process();
968 cpuEventRemoveList
.push(cpu_event
);
971 // Broadcast event to the Resource Pool
972 // Need to reset tid just in case this is a dummy instruction
974 resPool
->scheduleEvent(c_event
, inst
, 0, 0, tid
);
978 InOrderCPU::isThreadActive(ThreadID tid
)
980 list
<ThreadID
>::iterator isActive
=
981 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
983 return (isActive
!= activeThreads
.end());
987 InOrderCPU::isThreadReady(ThreadID tid
)
989 list
<ThreadID
>::iterator isReady
=
990 std::find(readyThreads
.begin(), readyThreads
.end(), tid
);
992 return (isReady
!= readyThreads
.end());
996 InOrderCPU::isThreadSuspended(ThreadID tid
)
998 list
<ThreadID
>::iterator isSuspended
=
999 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
1001 return (isSuspended
!= suspendedThreads
.end());
1005 InOrderCPU::activateNextReadyThread()
1007 if (readyThreads
.size() >= 1) {
1008 ThreadID ready_tid
= readyThreads
.front();
1010 // Activate in Pipeline
1011 activateThread(ready_tid
);
1013 // Activate in Resource Pool
1014 resPool
->activateThread(ready_tid
);
1016 list
<ThreadID
>::iterator ready_it
=
1017 std::find(readyThreads
.begin(), readyThreads
.end(), ready_tid
);
1018 readyThreads
.erase(ready_it
);
1021 "Attempting to activate new thread, but No Ready Threads to"
1024 "Unable to switch to next active thread.\n");
1029 InOrderCPU::activateThread(ThreadID tid
)
1031 if (isThreadSuspended(tid
)) {
1033 "Removing [tid:%i] from suspended threads list.\n", tid
);
1035 list
<ThreadID
>::iterator susp_it
=
1036 std::find(suspendedThreads
.begin(), suspendedThreads
.end(),
1038 suspendedThreads
.erase(susp_it
);
1041 if (threadModel
== SwitchOnCacheMiss
&&
1042 numActiveThreads() == 1) {
1044 "Ignoring activation of [tid:%i], since [tid:%i] is "
1045 "already running.\n", tid
, activeThreadId());
1047 DPRINTF(InOrderCPU
,"Placing [tid:%i] on ready threads list\n",
1050 readyThreads
.push_back(tid
);
1052 } else if (!isThreadActive(tid
)) {
1054 "Adding [tid:%i] to active threads list.\n", tid
);
1055 activeThreads
.push_back(tid
);
1057 activateThreadInPipeline(tid
);
1059 thread
[tid
]->lastActivate
= curTick();
1061 tcBase(tid
)->setStatus(ThreadContext::Active
);
1070 InOrderCPU::activateThreadInPipeline(ThreadID tid
)
1072 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
1073 pipelineStage
[stNum
]->activateThread(tid
);
1078 InOrderCPU::deactivateContext(ThreadID tid
, int delay
)
1080 DPRINTF(InOrderCPU
,"[tid:%i]: Deactivating ...\n", tid
);
1082 scheduleCpuEvent(DeactivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1084 // Be sure to signal that there's some activity so the CPU doesn't
1085 // deschedule itself.
1086 activityRec
.activity();
1092 InOrderCPU::deactivateThread(ThreadID tid
)
1094 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
1096 if (isThreadActive(tid
)) {
1097 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
1099 list
<ThreadID
>::iterator thread_it
=
1100 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
1102 removePipelineStalls(*thread_it
);
1104 activeThreads
.erase(thread_it
);
1106 // Ideally, this should be triggered from the
1107 // suspendContext/Thread functions
1108 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1111 assert(!isThreadActive(tid
));
1115 InOrderCPU::removePipelineStalls(ThreadID tid
)
1117 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
1120 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
1121 pipelineStage
[stNum
]->removeStalls(tid
);
1127 InOrderCPU::updateThreadPriority()
1129 if (activeThreads
.size() > 1)
1131 //DEFAULT TO ROUND ROBIN SCHEME
1132 //e.g. Move highest priority to end of thread list
1133 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
1135 unsigned high_thread
= *list_begin
;
1137 activeThreads
.erase(list_begin
);
1139 activeThreads
.push_back(high_thread
);
1144 InOrderCPU::tickThreadStats()
1146 /** Keep track of cycles that each thread is active */
1147 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
1148 while (thread_it
!= activeThreads
.end()) {
1149 threadCycles
[*thread_it
]++;
1153 // Keep track of cycles where SMT is active
1154 if (activeThreads
.size() > 1) {
1160 InOrderCPU::activateContext(ThreadID tid
, int delay
)
1162 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
1165 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1167 // Be sure to signal that there's some activity so the CPU doesn't
1168 // deschedule itself.
1169 activityRec
.activity();
1175 InOrderCPU::activateNextReadyContext(int delay
)
1177 DPRINTF(InOrderCPU
,"Activating next ready thread\n");
1179 scheduleCpuEvent(ActivateNextReadyThread
, NoFault
, 0/*tid*/, dummyInst
[0],
1180 delay
, ActivateNextReadyThread_Pri
);
1182 // Be sure to signal that there's some activity so the CPU doesn't
1183 // deschedule itself.
1184 activityRec
.activity();
1190 InOrderCPU::haltContext(ThreadID tid
)
1192 DPRINTF(InOrderCPU
, "[tid:%i]: Calling Halt Context...\n", tid
);
1194 scheduleCpuEvent(HaltThread
, NoFault
, tid
, dummyInst
[tid
]);
1196 activityRec
.activity();
1200 InOrderCPU::haltThread(ThreadID tid
)
1202 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Halted Threads List...\n", tid
);
1203 deactivateThread(tid
);
1204 squashThreadInPipeline(tid
);
1205 haltedThreads
.push_back(tid
);
1207 tcBase(tid
)->setStatus(ThreadContext::Halted
);
1209 if (threadModel
== SwitchOnCacheMiss
) {
1210 activateNextReadyContext();
1215 InOrderCPU::suspendContext(ThreadID tid
)
1217 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, dummyInst
[tid
]);
1221 InOrderCPU::suspendThread(ThreadID tid
)
1223 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Suspended Threads List...\n",
1225 deactivateThread(tid
);
1226 suspendedThreads
.push_back(tid
);
1227 thread
[tid
]->lastSuspend
= curTick();
1229 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1233 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
1235 //Squash all instructions in each stage
1236 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
1237 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
1242 InOrderCPU::getPipeStage(int stage_num
)
1244 return pipelineStage
[stage_num
];
1249 InOrderCPU::flattenRegIdx(RegIndex reg_idx
, RegType
®_type
, ThreadID tid
)
1251 if (reg_idx
< FP_Base_DepTag
) {
1253 return isa
[tid
].flattenIntIndex(reg_idx
);
1254 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1255 reg_type
= FloatType
;
1256 reg_idx
-= FP_Base_DepTag
;
1257 return isa
[tid
].flattenFloatIndex(reg_idx
);
1259 reg_type
= MiscType
;
1260 return reg_idx
- TheISA::Ctrl_Base_DepTag
;
1265 InOrderCPU::readIntReg(RegIndex reg_idx
, ThreadID tid
)
1267 DPRINTF(IntRegs
, "[tid:%i]: Reading Int. Reg %i as %x\n",
1268 tid
, reg_idx
, intRegs
[tid
][reg_idx
]);
1270 return intRegs
[tid
][reg_idx
];
1274 InOrderCPU::readFloatReg(RegIndex reg_idx
, ThreadID tid
)
1276 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1277 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1279 return floatRegs
.f
[tid
][reg_idx
];
1283 InOrderCPU::readFloatRegBits(RegIndex reg_idx
, ThreadID tid
)
1285 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1286 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1288 return floatRegs
.i
[tid
][reg_idx
];
1292 InOrderCPU::setIntReg(RegIndex reg_idx
, uint64_t val
, ThreadID tid
)
1294 if (reg_idx
== TheISA::ZeroReg
) {
1295 DPRINTF(IntRegs
, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1296 "(Int. Reg %i) to %x\n", tid
, reg_idx
, val
);
1299 DPRINTF(IntRegs
, "[tid:%i]: Setting Int. Reg %i to %x\n",
1302 intRegs
[tid
][reg_idx
] = val
;
1308 InOrderCPU::setFloatReg(RegIndex reg_idx
, FloatReg val
, ThreadID tid
)
1310 floatRegs
.f
[tid
][reg_idx
] = val
;
1311 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1314 floatRegs
.i
[tid
][reg_idx
],
1315 floatRegs
.f
[tid
][reg_idx
]);
1320 InOrderCPU::setFloatRegBits(RegIndex reg_idx
, FloatRegBits val
, ThreadID tid
)
1322 floatRegs
.i
[tid
][reg_idx
] = val
;
1323 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1326 floatRegs
.i
[tid
][reg_idx
],
1327 floatRegs
.f
[tid
][reg_idx
]);
1331 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
1333 // If Default value is set, then retrieve target thread
1334 if (tid
== InvalidThreadID
) {
1335 tid
= TheISA::getTargetThread(tcBase(tid
));
1338 if (reg_idx
< FP_Base_DepTag
) {
1339 // Integer Register File
1340 return readIntReg(reg_idx
, tid
);
1341 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1342 // Float Register File
1343 reg_idx
-= FP_Base_DepTag
;
1344 return readFloatRegBits(reg_idx
, tid
);
1346 reg_idx
-= Ctrl_Base_DepTag
;
1347 return readMiscReg(reg_idx
, tid
); // Misc. Register File
1351 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
1354 // If Default value is set, then retrieve target thread
1355 if (tid
== InvalidThreadID
) {
1356 tid
= TheISA::getTargetThread(tcBase(tid
));
1359 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
1360 setIntReg(reg_idx
, val
, tid
);
1361 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
1362 reg_idx
-= FP_Base_DepTag
;
1363 setFloatRegBits(reg_idx
, val
, tid
);
1365 reg_idx
-= Ctrl_Base_DepTag
;
1366 setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
1371 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1373 return isa
[tid
].readMiscRegNoEffect(misc_reg
);
1377 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
1379 return isa
[tid
].readMiscReg(misc_reg
, tcBase(tid
));
1383 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1385 isa
[tid
].setMiscRegNoEffect(misc_reg
, val
);
1389 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1391 isa
[tid
].setMiscReg(misc_reg
, val
, tcBase(tid
));
1396 InOrderCPU::addInst(DynInstPtr inst
)
1398 ThreadID tid
= inst
->readTid();
1400 instList
[tid
].push_back(inst
);
1402 return --(instList
[tid
].end());
1406 InOrderCPU::findInst(InstSeqNum seq_num
, ThreadID tid
)
1408 ListIt it
= instList
[tid
].begin();
1409 ListIt end
= instList
[tid
].end();
1412 if ((*it
)->seqNum
== seq_num
)
1414 else if ((*it
)->seqNum
> seq_num
)
1420 return instList
[tid
].end();
1424 InOrderCPU::updateContextSwitchStats()
1426 // Set Average Stat Here, then reset to 0
1427 instsPerCtxtSwitch
= instsPerSwitch
;
1433 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1435 // Set the nextPC to be fetched if this is the last instruction
1438 // This contributes to the precise state of the CPU
1439 // which can be used when restoring a thread to the CPU after after any
1440 // type of context switching activity (fork, exception, etc.)
1441 TheISA::PCState comm_pc
= inst
->pcState();
1442 lastCommittedPC
[tid
] = comm_pc
;
1443 TheISA::advancePC(comm_pc
, inst
->staticInst
);
1444 pcState(comm_pc
, tid
);
1446 //@todo: may be unnecessary with new-ISA-specific branch handling code
1447 if (inst
->isControl()) {
1448 thread
[tid
]->lastGradIsBranch
= true;
1449 thread
[tid
]->lastBranchPC
= inst
->pcState();
1450 TheISA::advancePC(thread
[tid
]->lastBranchPC
, inst
->staticInst
);
1452 thread
[tid
]->lastGradIsBranch
= false;
1456 // Finalize Trace Data For Instruction
1457 if (inst
->traceData
) {
1458 //inst->traceData->setCycle(curTick());
1459 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1460 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1461 inst
->traceData
->dump();
1462 delete inst
->traceData
;
1463 inst
->traceData
= NULL
;
1466 // Increment active thread's instruction count
1469 // Increment thread-state's instruction count
1470 thread
[tid
]->numInst
++;
1471 thread
[tid
]->numOp
++;
1473 // Increment thread-state's instruction stats
1474 thread
[tid
]->numInsts
++;
1475 thread
[tid
]->numOps
++;
1477 // Count committed insts per thread stats
1478 if (!inst
->isMicroop() || inst
->isLastMicroop()) {
1479 committedInsts
[tid
]++;
1481 // Count total insts committed stat
1482 totalCommittedInsts
++;
1485 committedOps
[tid
]++;
1487 // Count SMT-committed insts per thread stat
1488 if (numActiveThreads() > 1) {
1489 if (!inst
->isMicroop() || inst
->isLastMicroop())
1490 smtCommittedInsts
[tid
]++;
1493 // Instruction-Mix Stats
1494 if (inst
->isLoad()) {
1496 } else if (inst
->isStore()) {
1498 } else if (inst
->isControl()) {
1500 } else if (inst
->isNop()) {
1502 } else if (inst
->isNonSpeculative()) {
1504 } else if (inst
->isInteger()) {
1506 } else if (inst
->isFloating()) {
1510 // Check for instruction-count-based events.
1511 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numOp
);
1513 // Finally, remove instruction from CPU
1517 // currently unused function, but substitute repetitive code w/this function
1520 InOrderCPU::addToRemoveList(DynInstPtr inst
)
1522 removeInstsThisCycle
= true;
1523 if (!inst
->isRemoveList()) {
1524 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1525 "[sn:%lli] to remove list\n",
1526 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1527 inst
->setRemoveList();
1528 removeList
.push(inst
->getInstListIt());
1530 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1531 "[sn:%lli], already remove list\n",
1532 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1538 InOrderCPU::removeInst(DynInstPtr inst
)
1540 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %s "
1542 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1544 removeInstsThisCycle
= true;
1546 // Remove the instruction.
1547 if (!inst
->isRemoveList()) {
1548 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1549 "[sn:%lli] to remove list\n",
1550 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1551 inst
->setRemoveList();
1552 removeList
.push(inst
->getInstListIt());
1554 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1555 "[sn:%lli], already on remove list\n",
1556 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1562 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1564 //assert(!instList[tid].empty());
1566 removeInstsThisCycle
= true;
1568 ListIt inst_iter
= instList
[tid
].end();
1572 DPRINTF(InOrderCPU
, "Squashing instructions from CPU instruction "
1573 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1574 tid
, seq_num
, (*inst_iter
)->seqNum
);
1576 while ((*inst_iter
)->seqNum
> seq_num
) {
1578 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1580 squashInstIt(inst_iter
, tid
);
1591 InOrderCPU::squashInstIt(const ListIt inst_it
, ThreadID tid
)
1593 DynInstPtr inst
= (*inst_it
);
1594 if (inst
->threadNumber
== tid
) {
1595 DPRINTF(InOrderCPU
, "Squashing instruction, "
1596 "[tid:%i] [sn:%lli] PC %s\n",
1601 inst
->setSquashed();
1602 archRegDepMap
[tid
].remove(inst
);
1604 if (!inst
->isRemoveList()) {
1605 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1606 "[sn:%lli] to remove list\n",
1607 inst
->threadNumber
, inst
->pcState(),
1609 inst
->setRemoveList();
1610 removeList
.push(inst_it
);
1612 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i]"
1613 " PC %s [sn:%lli], already on remove list\n",
1614 inst
->threadNumber
, inst
->pcState(),
1624 InOrderCPU::cleanUpRemovedInsts()
1626 while (!removeList
.empty()) {
1627 DPRINTF(InOrderCPU
, "Removing instruction, "
1628 "[tid:%i] [sn:%lli] PC %s\n",
1629 (*removeList
.front())->threadNumber
,
1630 (*removeList
.front())->seqNum
,
1631 (*removeList
.front())->pcState());
1633 DynInstPtr inst
= *removeList
.front();
1634 ThreadID tid
= inst
->threadNumber
;
1636 // Remove From Register Dependency Map, If Necessary
1637 // archRegDepMap[tid].remove(inst);
1639 // Clear if Non-Speculative
1640 if (inst
->staticInst
&&
1641 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1642 nonSpecInstActive
[tid
] == true) {
1643 nonSpecInstActive
[tid
] = false;
1646 inst
->onInstList
= false;
1648 instList
[tid
].erase(removeList
.front());
1653 removeInstsThisCycle
= false;
1657 InOrderCPU::cleanUpRemovedEvents()
1659 while (!cpuEventRemoveList
.empty()) {
1660 Event
*cpu_event
= cpuEventRemoveList
.front();
1661 cpuEventRemoveList
.pop();
1668 InOrderCPU::dumpInsts()
1672 ListIt inst_list_it
= instList
[0].begin();
1674 cprintf("Dumping Instruction List\n");
1676 while (inst_list_it
!= instList
[0].end()) {
1677 cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1679 num
, (*inst_list_it
)->pcState(),
1680 (*inst_list_it
)->threadNumber
,
1681 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1682 (*inst_list_it
)->isSquashed());
1689 InOrderCPU::wakeCPU()
1691 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1692 DPRINTF(Activity
, "CPU already running.\n");
1696 DPRINTF(Activity
, "Waking up CPU\n");
1698 Tick extra_cycles
= tickToCycles((curTick() - 1) - lastRunningCycle
);
1700 idleCycles
+= extra_cycles
;
1701 for (int stage_num
= 0; stage_num
< NumStages
; stage_num
++) {
1702 pipelineStage
[stage_num
]->idleCycles
+= extra_cycles
;
1705 numCycles
+= extra_cycles
;
1707 schedule(&tickEvent
, nextCycle(curTick()));
1710 // Lots of copied full system code...place into BaseCPU class?
1712 InOrderCPU::wakeup()
1714 if (thread
[0]->status() != ThreadContext::Suspended
)
1719 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1720 threadContexts
[0]->activate();
1724 InOrderCPU::syscallContext(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
1726 // Syscall must be non-speculative, so squash from last stage
1727 unsigned squash_stage
= NumStages
- 1;
1728 inst
->setSquashInfo(squash_stage
);
1730 // Squash In Pipeline Stage
1731 pipelineStage
[squash_stage
]->setupSquash(inst
, tid
);
1733 // Schedule Squash Through-out Resource Pool
1734 resPool
->scheduleEvent(
1735 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
, inst
, 0);
1736 scheduleCpuEvent(Syscall
, fault
, tid
, inst
, delay
, Syscall_Pri
);
1740 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1742 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1744 DPRINTF(Activity
,"Activity: syscall() called.\n");
1746 // Temporarily increase this by one to account for the syscall
1748 ++(this->thread
[tid
]->funcExeInst
);
1750 // Execute the actual syscall.
1751 this->thread
[tid
]->syscall(callnum
);
1753 // Decrease funcExeInst by one as the normal commit will handle
1755 --(this->thread
[tid
]->funcExeInst
);
1757 // Clear Non-Speculative Block Variable
1758 nonSpecInstActive
[tid
] = false;
1762 InOrderCPU::getITBPtr()
1764 CacheUnit
*itb_res
= resPool
->getInstUnit();
1765 return itb_res
->tlb();
1770 InOrderCPU::getDTBPtr()
1772 return resPool
->getDataUnit()->tlb();
1776 InOrderCPU::getDecoderPtr()
1778 return &resPool
->getInstUnit()->decoder
;
1782 InOrderCPU::read(DynInstPtr inst
, Addr addr
,
1783 uint8_t *data
, unsigned size
, unsigned flags
)
1785 return resPool
->getDataUnit()->read(inst
, addr
, data
, size
, flags
);
1789 InOrderCPU::write(DynInstPtr inst
, uint8_t *data
, unsigned size
,
1790 Addr addr
, unsigned flags
, uint64_t *write_res
)
1792 return resPool
->getDataUnit()->write(inst
, data
, size
, addr
, flags
,