src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007 MIPS Technologies, Inc.
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Korey Sewell
  41  *
  42  */
  43
  44 #include <algorithm>
  45
  46 #include "arch/utility.hh"
  47 #include "base/bigint.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/inorder/resources/cache_unit.hh"
  50 #include "cpu/inorder/resources/resource_list.hh"
  51 #include "cpu/inorder/cpu.hh"
  52 #include "cpu/inorder/first_stage.hh"
  53 #include "cpu/inorder/inorder_dyn_inst.hh"
  54 #include "cpu/inorder/pipeline_traits.hh"
  55 #include "cpu/inorder/resource_pool.hh"
  56 #include "cpu/inorder/thread_context.hh"
  57 #include "cpu/inorder/thread_state.hh"
  58 #include "cpu/activity.hh"
  59 #include "cpu/base.hh"
  60 #include "cpu/exetrace.hh"
  61 #include "cpu/quiesce_event.hh"
  62 #include "cpu/simple_thread.hh"
  63 #include "cpu/thread_context.hh"
  64 #include "debug/Activity.hh"
  65 #include "debug/InOrderCPU.hh"
  66 #include "debug/InOrderCachePort.hh"
  67 #include "debug/Interrupt.hh"
  68 #include "debug/Quiesce.hh"
  69 #include "debug/RefCount.hh"
  70 #include "debug/SkedCache.hh"
  71 #include "params/InOrderCPU.hh"
  72 #include "sim/full_system.hh"
  73 #include "sim/process.hh"
  74 #include "sim/stat_control.hh"
  75 #include "sim/system.hh"
  76
  77 #if THE_ISA == ALPHA_ISA
  78 #include "arch/alpha/osfpal.hh"
  79 #endif
  80
  81 using namespace std;
  82 using namespace TheISA;
  83 using namespace ThePipeline;
  84
  85 InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit) :
  86     CpuPort(_cacheUnit->name() + "-cache-port", _cacheUnit->cpu),
  87     cacheUnit(_cacheUnit)
  88 { }
  89
  90 bool
  91 InOrderCPU::CachePort::recvTiming(Packet *pkt)
  92 {
  93     if (pkt->isError())
  94         DPRINTF(InOrderCachePort, "Got error packet back for address: %x\n",
  95                 pkt->getAddr());
  96     else if (pkt->isResponse())
  97         cacheUnit->processCacheCompletion(pkt);
  98     else {
  99         //@note: depending on consistency model, update here
 100         DPRINTF(InOrderCachePort, "Received snoop pkt %x,Ignoring\n",
 101                 pkt->getAddr());
 102     }
 103
 104     return true;
 105 }
 106
 107 void
 108 InOrderCPU::CachePort::recvRetry()
 109 {
 110     cacheUnit->recvRetry();
 111 }
 112
 113 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
 114   : Event(CPU_Tick_Pri), cpu(c)
 115 { }
 116
 117
 118 void
 119 InOrderCPU::TickEvent::process()
 120 {
 121     cpu->tick();
 122 }
 123
 124
 125 const char *
 126 InOrderCPU::TickEvent::description() const
 127 {
 128     return "InOrderCPU tick event";
 129 }
 130
 131 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
 132                                Fault fault, ThreadID _tid, DynInstPtr inst,
 133                                CPUEventPri event_pri)
 134     : Event(event_pri), cpu(_cpu)
 135 {
 136     setEvent(e_type, fault, _tid, inst);
 137 }
 138
 139
 140 std::string InOrderCPU::eventNames[NumCPUEvents] =
 141 {
 142     "ActivateThread",
 143     "ActivateNextReadyThread",
 144     "DeactivateThread",
 145     "HaltThread",
 146     "SuspendThread",
 147     "Trap",
 148     "Syscall",
 149     "SquashFromMemStall",
 150     "UpdatePCs"
 151 };
 152
 153 void
 154 InOrderCPU::CPUEvent::process()
 155 {
 156     switch (cpuEventType)
 157     {
 158       case ActivateThread:
 159         cpu->activateThread(tid);
 160         cpu->resPool->activateThread(tid);
 161         break;
 162
 163       case ActivateNextReadyThread:
 164         cpu->activateNextReadyThread();
 165         break;
 166
 167       case DeactivateThread:
 168         cpu->deactivateThread(tid);
 169         cpu->resPool->deactivateThread(tid);
 170         break;
 171
 172       case HaltThread:
 173         cpu->haltThread(tid);
 174         cpu->resPool->deactivateThread(tid);
 175         break;
 176
 177       case SuspendThread:
 178         cpu->suspendThread(tid);
 179         cpu->resPool->suspendThread(tid);
 180         break;
 181
 182       case SquashFromMemStall:
 183         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 184         cpu->resPool->squashDueToMemStall(inst, inst->squashingStage,
 185                                           inst->seqNum, tid);
 186         break;
 187
 188       case Trap:
 189         DPRINTF(InOrderCPU, "Trapping CPU\n");
 190         cpu->trap(fault, tid, inst);
 191         cpu->resPool->trap(fault, tid, inst);
 192         cpu->trapPending[tid] = false;
 193         break;
 194
 195       case Syscall:
 196         cpu->syscall(inst->syscallNum, tid);
 197         cpu->resPool->trap(fault, tid, inst);
 198         break;
 199
 200       default:
 201         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 202     }
 203
 204     cpu->cpuEventRemoveList.push(this);
 205 }
 206
 207
 208
 209 const char *
 210 InOrderCPU::CPUEvent::description() const
 211 {
 212     return "InOrderCPU event";
 213 }
 214
 215 void
 216 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 217 {
 218     assert(!scheduled() || squashed());
 219     cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
 220 }
 221
 222 void
 223 InOrderCPU::CPUEvent::unscheduleEvent()
 224 {
 225     if (scheduled())
 226         squash();
 227 }
 228
 229 InOrderCPU::InOrderCPU(Params *params)
 230     : BaseCPU(params),
 231       cpu_id(params->cpu_id),
 232       coreType("default"),
 233       _status(Idle),
 234       tickEvent(this),
 235       stageWidth(params->stageWidth),
 236       resPool(new ResourcePool(this, params)),
 237       timeBuffer(2 , 2),
 238       dataPort(resPool->getDataUnit()),
 239       instPort(resPool->getInstUnit()),
 240       removeInstsThisCycle(false),
 241       activityRec(params->name, NumStages, 10, params->activity),
 242       system(params->system),
 243 #ifdef DEBUG
 244       cpuEventNum(0),
 245       resReqCount(0),
 246 #endif // DEBUG
 247       drainCount(0),
 248       deferRegistration(false/*params->deferRegistration*/),
 249       stageTracing(params->stageTracing),
 250       lastRunningCycle(0),
 251       instsPerSwitch(0)
 252 {
 253     cpu_params = params;
 254
 255     // Resize for Multithreading CPUs
 256     thread.resize(numThreads);
 257
 258     ThreadID active_threads = params->workload.size();
 259     if (FullSystem) {
 260         active_threads = 1;
 261     } else {
 262         active_threads = params->workload.size();
 263
 264         if (active_threads > MaxThreads) {
 265             panic("Workload Size too large. Increase the 'MaxThreads'"
 266                   "in your InOrder implementation or "
 267                   "edit your workload size.");
 268         }
 269
 270
 271         if (active_threads > 1) {
 272             threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 273
 274             if (threadModel == SMT) {
 275                 DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 276             } else if (threadModel == SwitchOnCacheMiss) {
 277                 DPRINTF(InOrderCPU, "Setting Thread Model to "
 278                         "Switch On Cache Miss\n");
 279             }
 280
 281         } else {
 282             threadModel = Single;
 283         }
 284     }
 285
 286     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 287         pc[tid].set(0);
 288         lastCommittedPC[tid].set(0);
 289
 290         if (FullSystem) {
 291             // SMT is not supported in FS mode yet.
 292             assert(numThreads == 1);
 293             thread[tid] = new Thread(this, 0, NULL);
 294         } else {
 295             if (tid < (ThreadID)params->workload.size()) {
 296                 DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 297                         tid, params->workload[tid]->prog_fname);
 298                 thread[tid] =
 299                     new Thread(this, tid, params->workload[tid]);
 300             } else {
 301                 //Allocate Empty thread so M5 can use later
 302                 //when scheduling threads to CPU
 303                 Process* dummy_proc = params->workload[0];
 304                 thread[tid] = new Thread(this, tid, dummy_proc);
 305             }
 306
 307             // Eventually set this with parameters...
 308             asid[tid] = tid;
 309         }
 310
 311         // Setup the TC that will serve as the interface to the threads/CPU.
 312         InOrderThreadContext *tc = new InOrderThreadContext;
 313         tc->cpu = this;
 314         tc->thread = thread[tid];
 315
 316         // Setup quiesce event.
 317         this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
 318
 319         // Give the thread the TC.
 320         thread[tid]->tc = tc;
 321         thread[tid]->setFuncExeInst(0);
 322         globalSeqNum[tid] = 1;
 323
 324         // Add the TC to the CPU's list of TC's.
 325         this->threadContexts.push_back(tc);
 326     }
 327
 328     // Initialize TimeBuffer Stage Queues
 329     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 330         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 331         stageQueue[stNum]->id(stNum);
 332     }
 333
 334
 335     // Set Up Pipeline Stages
 336     for (int stNum=0; stNum < NumStages; stNum++) {
 337         if (stNum == 0)
 338             pipelineStage[stNum] = new FirstStage(params, stNum);
 339         else
 340             pipelineStage[stNum] = new PipelineStage(params, stNum);
 341
 342         pipelineStage[stNum]->setCPU(this);
 343         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 344         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 345
 346         // Take Care of 1st/Nth stages
 347         if (stNum > 0)
 348             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 349         if (stNum < NumStages - 1)
 350             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 351     }
 352
 353     // Initialize thread specific variables
 354     for (ThreadID tid = 0; tid < numThreads; tid++) {
 355         archRegDepMap[tid].setCPU(this);
 356
 357         nonSpecInstActive[tid] = false;
 358         nonSpecSeqNum[tid] = 0;
 359
 360         squashSeqNum[tid] = MaxAddr;
 361         lastSquashCycle[tid] = 0;
 362
 363         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 364         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 365         isa[tid].clear();
 366
 367         // Define dummy instructions and resource requests to be used.
 368         dummyInst[tid] = new InOrderDynInst(this,
 369                                             thread[tid],
 370                                             0,
 371                                             tid,
 372                                             asid[tid]);
 373
 374         dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
 375
 376
 377         if (FullSystem) {
 378             // Use this dummy inst to force squashing behind every instruction
 379             // in pipeline
 380             dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
 381             dummyTrapInst[tid]->seqNum = 0;
 382             dummyTrapInst[tid]->squashSeqNum = 0;
 383             dummyTrapInst[tid]->setTid(tid);
 384         }
 385
 386         trapPending[tid] = false;
 387
 388     }
 389
 390     // InOrderCPU always requires an interrupt controller.
 391     if (!params->defer_registration && !interrupts) {
 392         fatal("InOrderCPU %s has no interrupt controller.\n"
 393               "Ensure createInterruptController() is called.\n", name());
 394     }
 395
 396     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 397     dummyReqInst->setSquashed();
 398     dummyReqInst->resetInstCount();
 399
 400     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 401     dummyBufferInst->setSquashed();
 402     dummyBufferInst->resetInstCount();
 403
 404     endOfSkedIt = skedCache.end();
 405     frontEndSked = createFrontEndSked();
 406     faultSked = createFaultSked();
 407
 408     lastRunningCycle = curTick();
 409
 410     lockAddr = 0;
 411     lockFlag = false;
 412
 413     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 414     scheduleTickEvent(0);
 415 }
 416
 417 InOrderCPU::~InOrderCPU()
 418 {
 419     delete resPool;
 420
 421     SkedCacheIt sked_it = skedCache.begin();
 422     SkedCacheIt sked_end = skedCache.end();
 423
 424     while (sked_it != sked_end) {
 425         delete (*sked_it).second;
 426         sked_it++;
 427     }
 428     skedCache.clear();
 429 }
 430
 431 m5::hash_map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
 432
 433 RSkedPtr
 434 InOrderCPU::createFrontEndSked()
 435 {
 436     RSkedPtr res_sked = new ResourceSked();
 437     int stage_num = 0;
 438     StageScheduler F(res_sked, stage_num++);
 439     StageScheduler D(res_sked, stage_num++);
 440
 441     // FETCH
 442     F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
 443     F.needs(ICache, FetchUnit::InitiateFetch);
 444
 445     // DECODE
 446     D.needs(ICache, FetchUnit::CompleteFetch);
 447     D.needs(Decode, DecodeUnit::DecodeInst);
 448     D.needs(BPred, BranchPredictor::PredictBranch);
 449     D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
 450
 451
 452     DPRINTF(SkedCache, "Resource Sked created for instruction Front End\n");
 453
 454     return res_sked;
 455 }
 456
 457 RSkedPtr
 458 InOrderCPU::createFaultSked()
 459 {
 460     RSkedPtr res_sked = new ResourceSked();
 461     StageScheduler W(res_sked, NumStages - 1);
 462     W.needs(Grad, GraduationUnit::CheckFault);
 463     DPRINTF(SkedCache, "Resource Sked created for instruction Faults\n");
 464     return res_sked;
 465 }
 466
 467 RSkedPtr
 468 InOrderCPU::createBackEndSked(DynInstPtr inst)
 469 {
 470     RSkedPtr res_sked = lookupSked(inst);
 471     if (res_sked != NULL) {
 472         DPRINTF(SkedCache, "Found %s in sked cache.\n",
 473                 inst->instName());
 474         return res_sked;
 475     } else {
 476         res_sked = new ResourceSked();
 477     }
 478
 479     int stage_num = ThePipeline::BackEndStartStage;
 480     StageScheduler X(res_sked, stage_num++);
 481     StageScheduler M(res_sked, stage_num++);
 482     StageScheduler W(res_sked, stage_num++);
 483
 484     if (!inst->staticInst) {
 485         warn_once("Static Instruction Object Not Set. Can't Create"
 486                   " Back End Schedule");
 487         return NULL;
 488     }
 489
 490     // EXECUTE
 491     X.needs(RegManager, UseDefUnit::MarkDestRegs);
 492     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 493         if (!idx || !inst->isStore()) {
 494             X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
 495         }
 496     }
 497
 498     //@todo: schedule non-spec insts to operate on this cycle
 499     // as long as all previous insts are done
 500     if ( inst->isNonSpeculative() ) {
 501         // skip execution of non speculative insts until later
 502     } else if ( inst->isMemRef() ) {
 503         if ( inst->isLoad() ) {
 504             X.needs(AGEN, AGENUnit::GenerateAddr);
 505         }
 506     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 507         X.needs(MDU, MultDivUnit::StartMultDiv);
 508     } else {
 509         X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 510     }
 511
 512     // MEMORY
 513     if (!inst->isNonSpeculative()) {
 514         if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 515             M.needs(MDU, MultDivUnit::EndMultDiv);
 516         }
 517
 518         if ( inst->isLoad() ) {
 519             M.needs(DCache, CacheUnit::InitiateReadData);
 520             if (inst->splitInst)
 521                 M.needs(DCache, CacheUnit::InitSecondSplitRead);
 522         } else if ( inst->isStore() ) {
 523             for (int i = 1; i < inst->numSrcRegs(); i++ ) {
 524                 M.needs(RegManager, UseDefUnit::ReadSrcReg, i);
 525             }
 526             M.needs(AGEN, AGENUnit::GenerateAddr);
 527             M.needs(DCache, CacheUnit::InitiateWriteData);
 528             if (inst->splitInst)
 529                 M.needs(DCache, CacheUnit::InitSecondSplitWrite);
 530         }
 531     }
 532
 533     // WRITEBACK
 534     if (!inst->isNonSpeculative()) {
 535         if ( inst->isLoad() ) {
 536             W.needs(DCache, CacheUnit::CompleteReadData);
 537             if (inst->splitInst)
 538                 W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
 539         } else if ( inst->isStore() ) {
 540             W.needs(DCache, CacheUnit::CompleteWriteData);
 541             if (inst->splitInst)
 542                 W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
 543         }
 544     } else {
 545         // Finally, Execute Speculative Data
 546         if (inst->isMemRef()) {
 547             if (inst->isLoad()) {
 548                 W.needs(AGEN, AGENUnit::GenerateAddr);
 549                 W.needs(DCache, CacheUnit::InitiateReadData);
 550                 if (inst->splitInst)
 551                     W.needs(DCache, CacheUnit::InitSecondSplitRead);
 552                 W.needs(DCache, CacheUnit::CompleteReadData);
 553                 if (inst->splitInst)
 554                     W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
 555             } else if (inst->isStore()) {
 556                 if ( inst->numSrcRegs() >= 2 ) {
 557                     W.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 558                 }
 559                 W.needs(AGEN, AGENUnit::GenerateAddr);
 560                 W.needs(DCache, CacheUnit::InitiateWriteData);
 561                 if (inst->splitInst)
 562                     W.needs(DCache, CacheUnit::InitSecondSplitWrite);
 563                 W.needs(DCache, CacheUnit::CompleteWriteData);
 564                 if (inst->splitInst)
 565                     W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
 566             }
 567         } else {
 568             W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 569         }
 570     }
 571
 572     W.needs(Grad, GraduationUnit::CheckFault);
 573
 574     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 575         W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
 576     }
 577
 578     if (inst->isControl())
 579         W.needs(BPred, BranchPredictor::UpdatePredictor);
 580
 581     W.needs(Grad, GraduationUnit::GraduateInst);
 582
 583     // Insert Back Schedule into our cache of
 584     // resource schedules
 585     addToSkedCache(inst, res_sked);
 586
 587     DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
 588             inst->instName(), inst->getMachInst());
 589     res_sked->print();
 590
 591     return res_sked;
 592 }
 593
 594 void
 595 InOrderCPU::regStats()
 596 {
 597     /* Register the Resource Pool's stats here.*/
 598     resPool->regStats();
 599
 600     /* Register for each Pipeline Stage */
 601     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 602         pipelineStage[stage_num]->regStats();
 603     }
 604
 605     /* Register any of the InOrderCPU's stats here.*/
 606     instsPerCtxtSwitch
 607         .name(name() + ".instsPerContextSwitch")
 608         .desc("Instructions Committed Per Context Switch")
 609         .prereq(instsPerCtxtSwitch);
 610
 611     numCtxtSwitches
 612         .name(name() + ".contextSwitches")
 613         .desc("Number of context switches");
 614
 615     comLoads
 616         .name(name() + ".comLoads")
 617         .desc("Number of Load instructions committed");
 618
 619     comStores
 620         .name(name() + ".comStores")
 621         .desc("Number of Store instructions committed");
 622
 623     comBranches
 624         .name(name() + ".comBranches")
 625         .desc("Number of Branches instructions committed");
 626
 627     comNops
 628         .name(name() + ".comNops")
 629         .desc("Number of Nop instructions committed");
 630
 631     comNonSpec
 632         .name(name() + ".comNonSpec")
 633         .desc("Number of Non-Speculative instructions committed");
 634
 635     comInts
 636         .name(name() + ".comInts")
 637         .desc("Number of Integer instructions committed");
 638
 639     comFloats
 640         .name(name() + ".comFloats")
 641         .desc("Number of Floating Point instructions committed");
 642
 643     timesIdled
 644         .name(name() + ".timesIdled")
 645         .desc("Number of times that the entire CPU went into an idle state and"
 646               " unscheduled itself")
 647         .prereq(timesIdled);
 648
 649     idleCycles
 650         .name(name() + ".idleCycles")
 651         .desc("Number of cycles cpu's stages were not processed");
 652
 653     runCycles
 654         .name(name() + ".runCycles")
 655         .desc("Number of cycles cpu stages are processed.");
 656
 657     activity
 658         .name(name() + ".activity")
 659         .desc("Percentage of cycles cpu is active")
 660         .precision(6);
 661     activity = (runCycles / numCycles) * 100;
 662
 663     threadCycles
 664         .init(numThreads)
 665         .name(name() + ".threadCycles")
 666         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 667
 668     smtCycles
 669         .name(name() + ".smtCycles")
 670         .desc("Total number of cycles that the CPU was in SMT-mode");
 671
 672     committedInsts
 673         .init(numThreads)
 674         .name(name() + ".committedInsts")
 675         .desc("Number of Instructions committed (Per-Thread)");
 676
 677     committedOps
 678         .init(numThreads)
 679         .name(name() + ".committedOps")
 680         .desc("Number of Ops committed (Per-Thread)");
 681
 682     smtCommittedInsts
 683         .init(numThreads)
 684         .name(name() + ".smtCommittedInsts")
 685         .desc("Number of SMT Instructions committed (Per-Thread)");
 686
 687     totalCommittedInsts
 688         .name(name() + ".committedInsts_total")
 689         .desc("Number of Instructions committed (Total)");
 690
 691     cpi
 692         .name(name() + ".cpi")
 693         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 694         .precision(6);
 695     cpi = numCycles / committedInsts;
 696
 697     smtCpi
 698         .name(name() + ".smt_cpi")
 699         .desc("CPI: Total SMT-CPI")
 700         .precision(6);
 701     smtCpi = smtCycles / smtCommittedInsts;
 702
 703     totalCpi
 704         .name(name() + ".cpi_total")
 705         .desc("CPI: Total CPI of All Threads")
 706         .precision(6);
 707     totalCpi = numCycles / totalCommittedInsts;
 708
 709     ipc
 710         .name(name() + ".ipc")
 711         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 712         .precision(6);
 713     ipc =  committedInsts / numCycles;
 714
 715     smtIpc
 716         .name(name() + ".smt_ipc")
 717         .desc("IPC: Total SMT-IPC")
 718         .precision(6);
 719     smtIpc = smtCommittedInsts / smtCycles;
 720
 721     totalIpc
 722         .name(name() + ".ipc_total")
 723         .desc("IPC: Total IPC of All Threads")
 724         .precision(6);
 725         totalIpc =  totalCommittedInsts / numCycles;
 726
 727     BaseCPU::regStats();
 728 }
 729
 730
 731 void
 732 InOrderCPU::tick()
 733 {
 734     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 735
 736     ++numCycles;
 737
 738     checkForInterrupts();
 739
 740     bool pipes_idle = true;
 741     //Tick each of the stages
 742     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 743         pipelineStage[stNum]->tick();
 744
 745         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 746     }
 747
 748     if (pipes_idle)
 749         idleCycles++;
 750     else
 751         runCycles++;
 752
 753     // Now advance the time buffers one tick
 754     timeBuffer.advance();
 755     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 756         stageQueue[sqNum]->advance();
 757     }
 758     activityRec.advance();
 759
 760     // Any squashed events, or insts then remove them now
 761     cleanUpRemovedEvents();
 762     cleanUpRemovedInsts();
 763
 764     // Re-schedule CPU for this cycle
 765     if (!tickEvent.scheduled()) {
 766         if (_status == SwitchedOut) {
 767             // increment stat
 768             lastRunningCycle = curTick();
 769         } else if (!activityRec.active()) {
 770             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 771             lastRunningCycle = curTick();
 772             timesIdled++;
 773         } else {
 774             //Tick next_tick = curTick() + cycles(1);
 775             //tickEvent.schedule(next_tick);
 776             schedule(&tickEvent, nextCycle(curTick() + 1));
 777             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 778                     nextCycle(curTick() + 1));
 779         }
 780     }
 781
 782     tickThreadStats();
 783     updateThreadPriority();
 784 }
 785
 786
 787 void
 788 InOrderCPU::init()
 789 {
 790     BaseCPU::init();
 791
 792     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 793         // Set inSyscall so that the CPU doesn't squash when initially
 794         // setting up registers.
 795         thread[tid]->inSyscall = true;
 796         // Initialise the ThreadContext's memory proxies
 797         thread[tid]->initMemProxies(thread[tid]->getTC());
 798     }
 799
 800     if (FullSystem) {
 801         for (ThreadID tid = 0; tid < numThreads; tid++) {
 802             ThreadContext *src_tc = threadContexts[tid];
 803             TheISA::initCPU(src_tc, src_tc->contextId());
 804         }
 805     }
 806
 807     // Clear inSyscall.
 808     for (ThreadID tid = 0; tid < numThreads; ++tid)
 809         thread[tid]->inSyscall = false;
 810
 811     // Call Initializiation Routine for Resource Pool
 812     resPool->init();
 813 }
 814
 815 Fault
 816 InOrderCPU::hwrei(ThreadID tid)
 817 {
 818 #if THE_ISA == ALPHA_ISA
 819     // Need to clear the lock flag upon returning from an interrupt.
 820     setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
 821
 822     thread[tid]->kernelStats->hwrei();
 823     // FIXME: XXX check for interrupts? XXX
 824 #endif
 825
 826     return NoFault;
 827 }
 828
 829
 830 bool
 831 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 832 {
 833 #if THE_ISA == ALPHA_ISA
 834     if (this->thread[tid]->kernelStats)
 835         this->thread[tid]->kernelStats->callpal(palFunc,
 836                                                 this->threadContexts[tid]);
 837
 838     switch (palFunc) {
 839       case PAL::halt:
 840         halt();
 841         if (--System::numSystemsRunning == 0)
 842             exitSimLoop("all cpus halted");
 843         break;
 844
 845       case PAL::bpt:
 846       case PAL::bugchk:
 847         if (this->system->breakpoint())
 848             return false;
 849         break;
 850     }
 851 #endif
 852     return true;
 853 }
 854
 855 void
 856 InOrderCPU::checkForInterrupts()
 857 {
 858     for (int i = 0; i < threadContexts.size(); i++) {
 859         ThreadContext *tc = threadContexts[i];
 860
 861         if (interrupts->checkInterrupts(tc)) {
 862             Fault interrupt = interrupts->getInterrupt(tc);
 863
 864             if (interrupt != NoFault) {
 865                 DPRINTF(Interrupt, "Processing Intterupt for [tid:%i].\n",
 866                         tc->threadId());
 867
 868                 ThreadID tid = tc->threadId();
 869                 interrupts->updateIntrInfo(tc);
 870
 871                 // Squash from Last Stage in Pipeline
 872                 unsigned last_stage = NumStages - 1;
 873                 dummyTrapInst[tid]->squashingStage = last_stage;
 874                 pipelineStage[last_stage]->setupSquash(dummyTrapInst[tid],
 875                                                        tid);
 876
 877                 // By default, setupSquash will always squash from stage + 1
 878                 pipelineStage[BackEndStartStage - 1]->setupSquash(dummyTrapInst[tid],
 879                                                                   tid);
 880
 881                 // Schedule Squash Through-out Resource Pool
 882                 resPool->scheduleEvent(
 883                     (InOrderCPU::CPUEventType)ResourcePool::SquashAll,
 884                     dummyTrapInst[tid], 0);
 885
 886                 // Finally, Setup Trap to happen at end of cycle
 887                 trapContext(interrupt, tid, dummyTrapInst[tid]);
 888             }
 889         }
 890     }
 891 }
 892
 893 Fault
 894 InOrderCPU::getInterrupts()
 895 {
 896     // Check if there are any outstanding interrupts
 897     return interrupts->getInterrupt(threadContexts[0]);
 898 }
 899
 900 void
 901 InOrderCPU::processInterrupts(Fault interrupt)
 902 {
 903     // Check for interrupts here.  For now can copy the code that
 904     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 905     // is the one that handles the interrupts.
 906     // @todo: Possibly consolidate the interrupt checking code.
 907     // @todo: Allow other threads to handle interrupts.
 908
 909     assert(interrupt != NoFault);
 910     interrupts->updateIntrInfo(threadContexts[0]);
 911
 912     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 913
 914     // Note: Context ID ok here? Impl. of FS mode needs to revisit this
 915     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 916 }
 917
 918 void
 919 InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 920 {
 921     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 922     trapPending[tid] = true;
 923 }
 924
 925 void
 926 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 927 {
 928     fault->invoke(tcBase(tid), inst->staticInst);
 929     removePipelineStalls(tid);
 930 }
 931
 932 void
 933 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 934 {
 935     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 936 }
 937
 938
 939 void
 940 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 941                                 ThreadID tid)
 942 {
 943     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 944
 945     // Squash all instructions in each stage including
 946     // instruction that caused the squash (seq_num - 1)
 947     // NOTE: The stage bandwidth needs to be cleared so thats why
 948     //       the stalling instruction is squashed as well. The stalled
 949     //       instruction is previously placed in another intermediate buffer
 950     //       while it's stall is being handled.
 951     InstSeqNum squash_seq_num = seq_num - 1;
 952
 953     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 954         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 955     }
 956 }
 957
 958 void
 959 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 960                              ThreadID tid, DynInstPtr inst,
 961                              unsigned delay, CPUEventPri event_pri)
 962 {
 963     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 964                                        event_pri);
 965
 966     Tick sked_tick = nextCycle(curTick() + ticks(delay));
 967     if (delay >= 0) {
 968         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 969                 eventNames[c_event], curTick() + delay, tid);
 970         schedule(cpu_event, sked_tick);
 971     } else {
 972         cpu_event->process();
 973         cpuEventRemoveList.push(cpu_event);
 974     }
 975
 976     // Broadcast event to the Resource Pool
 977     // Need to reset tid just in case this is a dummy instruction
 978     inst->setTid(tid);
 979     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 980 }
 981
 982 bool
 983 InOrderCPU::isThreadActive(ThreadID tid)
 984 {
 985   list<ThreadID>::iterator isActive =
 986       std::find(activeThreads.begin(), activeThreads.end(), tid);
 987
 988     return (isActive != activeThreads.end());
 989 }
 990
 991 bool
 992 InOrderCPU::isThreadReady(ThreadID tid)
 993 {
 994   list<ThreadID>::iterator isReady =
 995       std::find(readyThreads.begin(), readyThreads.end(), tid);
 996
 997     return (isReady != readyThreads.end());
 998 }
 999
1000 bool
1001 InOrderCPU::isThreadSuspended(ThreadID tid)
1002 {
1003   list<ThreadID>::iterator isSuspended =
1004       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
1005
1006     return (isSuspended != suspendedThreads.end());
1007 }
1008
1009 void
1010 InOrderCPU::activateNextReadyThread()
1011 {
1012     if (readyThreads.size() >= 1) {
1013         ThreadID ready_tid = readyThreads.front();
1014
1015         // Activate in Pipeline
1016         activateThread(ready_tid);
1017
1018         // Activate in Resource Pool
1019         resPool->activateThread(ready_tid);
1020
1021         list<ThreadID>::iterator ready_it =
1022             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
1023         readyThreads.erase(ready_it);
1024     } else {
1025         DPRINTF(InOrderCPU,
1026                 "Attempting to activate new thread, but No Ready Threads to"
1027                 "activate.\n");
1028         DPRINTF(InOrderCPU,
1029                 "Unable to switch to next active thread.\n");
1030     }
1031 }
1032
1033 void
1034 InOrderCPU::activateThread(ThreadID tid)
1035 {
1036     if (isThreadSuspended(tid)) {
1037         DPRINTF(InOrderCPU,
1038                 "Removing [tid:%i] from suspended threads list.\n", tid);
1039
1040         list<ThreadID>::iterator susp_it =
1041             std::find(suspendedThreads.begin(), suspendedThreads.end(),
1042                       tid);
1043         suspendedThreads.erase(susp_it);
1044     }
1045
1046     if (threadModel == SwitchOnCacheMiss &&
1047         numActiveThreads() == 1) {
1048         DPRINTF(InOrderCPU,
1049                 "Ignoring activation of [tid:%i], since [tid:%i] is "
1050                 "already running.\n", tid, activeThreadId());
1051
1052         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
1053                 tid);
1054
1055         readyThreads.push_back(tid);
1056
1057     } else if (!isThreadActive(tid)) {
1058         DPRINTF(InOrderCPU,
1059                 "Adding [tid:%i] to active threads list.\n", tid);
1060         activeThreads.push_back(tid);
1061
1062         activateThreadInPipeline(tid);
1063
1064         thread[tid]->lastActivate = curTick();
1065
1066         tcBase(tid)->setStatus(ThreadContext::Active);
1067
1068         wakeCPU();
1069
1070         numCtxtSwitches++;
1071     }
1072 }
1073
1074 void
1075 InOrderCPU::activateThreadInPipeline(ThreadID tid)
1076 {
1077     for (int stNum=0; stNum < NumStages; stNum++) {
1078         pipelineStage[stNum]->activateThread(tid);
1079     }
1080 }
1081
1082 void
1083 InOrderCPU::deactivateContext(ThreadID tid, int delay)
1084 {
1085     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
1086
1087     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
1088
1089     // Be sure to signal that there's some activity so the CPU doesn't
1090     // deschedule itself.
1091     activityRec.activity();
1092
1093     _status = Running;
1094 }
1095
1096 void
1097 InOrderCPU::deactivateThread(ThreadID tid)
1098 {
1099     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
1100
1101     if (isThreadActive(tid)) {
1102         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
1103                 tid);
1104         list<ThreadID>::iterator thread_it =
1105             std::find(activeThreads.begin(), activeThreads.end(), tid);
1106
1107         removePipelineStalls(*thread_it);
1108
1109         activeThreads.erase(thread_it);
1110
1111         // Ideally, this should be triggered from the
1112         // suspendContext/Thread functions
1113         tcBase(tid)->setStatus(ThreadContext::Suspended);
1114     }
1115
1116     assert(!isThreadActive(tid));
1117 }
1118
1119 void
1120 InOrderCPU::removePipelineStalls(ThreadID tid)
1121 {
1122     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
1123             tid);
1124
1125     for (int stNum = 0; stNum < NumStages ; stNum++) {
1126         pipelineStage[stNum]->removeStalls(tid);
1127     }
1128
1129 }
1130
1131 void
1132 InOrderCPU::updateThreadPriority()
1133 {
1134     if (activeThreads.size() > 1)
1135     {
1136         //DEFAULT TO ROUND ROBIN SCHEME
1137         //e.g. Move highest priority to end of thread list
1138         list<ThreadID>::iterator list_begin = activeThreads.begin();
1139
1140         unsigned high_thread = *list_begin;
1141
1142         activeThreads.erase(list_begin);
1143
1144         activeThreads.push_back(high_thread);
1145     }
1146 }
1147
1148 inline void
1149 InOrderCPU::tickThreadStats()
1150 {
1151     /** Keep track of cycles that each thread is active */
1152     list<ThreadID>::iterator thread_it = activeThreads.begin();
1153     while (thread_it != activeThreads.end()) {
1154         threadCycles[*thread_it]++;
1155         thread_it++;
1156     }
1157
1158     // Keep track of cycles where SMT is active
1159     if (activeThreads.size() > 1) {
1160         smtCycles++;
1161     }
1162 }
1163
1164 void
1165 InOrderCPU::activateContext(ThreadID tid, int delay)
1166 {
1167     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
1168
1169
1170     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
1171
1172     // Be sure to signal that there's some activity so the CPU doesn't
1173     // deschedule itself.
1174     activityRec.activity();
1175
1176     _status = Running;
1177 }
1178
1179 void
1180 InOrderCPU::activateNextReadyContext(int delay)
1181 {
1182     DPRINTF(InOrderCPU,"Activating next ready thread\n");
1183
1184     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
1185                      delay, ActivateNextReadyThread_Pri);
1186
1187     // Be sure to signal that there's some activity so the CPU doesn't
1188     // deschedule itself.
1189     activityRec.activity();
1190
1191     _status = Running;
1192 }
1193
1194 void
1195 InOrderCPU::haltContext(ThreadID tid)
1196 {
1197     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
1198
1199     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid]);
1200
1201     activityRec.activity();
1202 }
1203
1204 void
1205 InOrderCPU::haltThread(ThreadID tid)
1206 {
1207     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
1208     deactivateThread(tid);
1209     squashThreadInPipeline(tid);
1210     haltedThreads.push_back(tid);
1211
1212     tcBase(tid)->setStatus(ThreadContext::Halted);
1213
1214     if (threadModel == SwitchOnCacheMiss) {
1215         activateNextReadyContext();
1216     }
1217 }
1218
1219 void
1220 InOrderCPU::suspendContext(ThreadID tid)
1221 {
1222     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid]);
1223 }
1224
1225 void
1226 InOrderCPU::suspendThread(ThreadID tid)
1227 {
1228     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
1229             tid);
1230     deactivateThread(tid);
1231     suspendedThreads.push_back(tid);
1232     thread[tid]->lastSuspend = curTick();
1233
1234     tcBase(tid)->setStatus(ThreadContext::Suspended);
1235 }
1236
1237 void
1238 InOrderCPU::squashThreadInPipeline(ThreadID tid)
1239 {
1240     //Squash all instructions in each stage
1241     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
1242         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
1243     }
1244 }
1245
1246 PipelineStage*
1247 InOrderCPU::getPipeStage(int stage_num)
1248 {
1249     return pipelineStage[stage_num];
1250 }
1251
1252
1253 RegIndex
1254 InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
1255 {
1256     if (reg_idx < FP_Base_DepTag) {
1257         reg_type = IntType;
1258         return isa[tid].flattenIntIndex(reg_idx);
1259     } else if (reg_idx < Ctrl_Base_DepTag) {
1260         reg_type = FloatType;
1261         reg_idx -= FP_Base_DepTag;
1262         return isa[tid].flattenFloatIndex(reg_idx);
1263     } else {
1264         reg_type = MiscType;
1265         return reg_idx - TheISA::Ctrl_Base_DepTag;
1266     }
1267 }
1268
1269 uint64_t
1270 InOrderCPU::readIntReg(RegIndex reg_idx, ThreadID tid)
1271 {
1272     DPRINTF(IntRegs, "[tid:%i]: Reading Int. Reg %i as %x\n",
1273             tid, reg_idx, intRegs[tid][reg_idx]);
1274
1275     return intRegs[tid][reg_idx];
1276 }
1277
1278 FloatReg
1279 InOrderCPU::readFloatReg(RegIndex reg_idx, ThreadID tid)
1280 {
1281     DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1282             tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
1283
1284     return floatRegs.f[tid][reg_idx];
1285 }
1286
1287 FloatRegBits
1288 InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
1289 {
1290     DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1291             tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
1292
1293     return floatRegs.i[tid][reg_idx];
1294 }
1295
1296 void
1297 InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid)
1298 {
1299     if (reg_idx == TheISA::ZeroReg) {
1300         DPRINTF(IntRegs, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1301                 "(Int. Reg %i) to %x\n", tid, reg_idx, val);
1302         return;
1303     } else {
1304         DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
1305                 tid, reg_idx, val);
1306
1307         intRegs[tid][reg_idx] = val;
1308     }
1309 }
1310
1311
1312 void
1313 InOrderCPU::setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid)
1314 {
1315     floatRegs.f[tid][reg_idx] = val;
1316     DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
1317             "%x, %08f\n",
1318             tid, reg_idx,
1319             floatRegs.i[tid][reg_idx],
1320             floatRegs.f[tid][reg_idx]);
1321 }
1322
1323
1324 void
1325 InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid)
1326 {
1327     floatRegs.i[tid][reg_idx] = val;
1328     DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
1329             "%x, %08f\n",
1330             tid, reg_idx,
1331             floatRegs.i[tid][reg_idx],
1332             floatRegs.f[tid][reg_idx]);
1333 }
1334
1335 uint64_t
1336 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1337 {
1338     // If Default value is set, then retrieve target thread
1339     if (tid == InvalidThreadID) {
1340         tid = TheISA::getTargetThread(tcBase(tid));
1341     }
1342
1343     if (reg_idx < FP_Base_DepTag) {
1344         // Integer Register File
1345         return readIntReg(reg_idx, tid);
1346     } else if (reg_idx < Ctrl_Base_DepTag) {
1347         // Float Register File
1348         reg_idx -= FP_Base_DepTag;
1349         return readFloatRegBits(reg_idx, tid);
1350     } else {
1351         reg_idx -= Ctrl_Base_DepTag;
1352         return readMiscReg(reg_idx, tid);  // Misc. Register File
1353     }
1354 }
1355 void
1356 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1357                               ThreadID tid)
1358 {
1359     // If Default value is set, then retrieve target thread
1360     if (tid == InvalidThreadID) {
1361         tid = TheISA::getTargetThread(tcBase(tid));
1362     }
1363
1364     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1365         setIntReg(reg_idx, val, tid);
1366     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1367         reg_idx -= FP_Base_DepTag;
1368         setFloatRegBits(reg_idx, val, tid);
1369     } else {
1370         reg_idx -= Ctrl_Base_DepTag;
1371         setMiscReg(reg_idx, val, tid); // Misc. Register File
1372     }
1373 }
1374
1375 MiscReg
1376 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1377 {
1378     return isa[tid].readMiscRegNoEffect(misc_reg);
1379 }
1380
1381 MiscReg
1382 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1383 {
1384     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1385 }
1386
1387 void
1388 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1389 {
1390     isa[tid].setMiscRegNoEffect(misc_reg, val);
1391 }
1392
1393 void
1394 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1395 {
1396     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1397 }
1398
1399
1400 InOrderCPU::ListIt
1401 InOrderCPU::addInst(DynInstPtr inst)
1402 {
1403     ThreadID tid = inst->readTid();
1404
1405     instList[tid].push_back(inst);
1406
1407     return --(instList[tid].end());
1408 }
1409
1410 InOrderCPU::ListIt
1411 InOrderCPU::findInst(InstSeqNum seq_num, ThreadID tid)
1412 {
1413     ListIt it = instList[tid].begin();
1414     ListIt end = instList[tid].end();
1415
1416     while (it != end) {
1417         if ((*it)->seqNum == seq_num)
1418             return it;
1419         else if ((*it)->seqNum > seq_num)
1420             break;
1421
1422         it++;
1423     }
1424
1425     return instList[tid].end();
1426 }
1427
1428 void
1429 InOrderCPU::updateContextSwitchStats()
1430 {
1431     // Set Average Stat Here, then reset to 0
1432     instsPerCtxtSwitch = instsPerSwitch;
1433     instsPerSwitch = 0;
1434 }
1435
1436
1437 void
1438 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1439 {
1440     // Set the nextPC to be fetched if this is the last instruction
1441     // committed
1442     // ========
1443     // This contributes to the precise state of the CPU
1444     // which can be used when restoring a thread to the CPU after after any
1445     // type of context switching activity (fork, exception, etc.)
1446     TheISA::PCState comm_pc = inst->pcState();
1447     lastCommittedPC[tid] = comm_pc;
1448     TheISA::advancePC(comm_pc, inst->staticInst);
1449     pcState(comm_pc, tid);
1450
1451     //@todo: may be unnecessary with new-ISA-specific branch handling code
1452     if (inst->isControl()) {
1453         thread[tid]->lastGradIsBranch = true;
1454         thread[tid]->lastBranchPC = inst->pcState();
1455         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1456     } else {
1457         thread[tid]->lastGradIsBranch = false;
1458     }
1459
1460
1461     // Finalize Trace Data For Instruction
1462     if (inst->traceData) {
1463         //inst->traceData->setCycle(curTick());
1464         inst->traceData->setFetchSeq(inst->seqNum);
1465         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1466         inst->traceData->dump();
1467         delete inst->traceData;
1468         inst->traceData = NULL;
1469     }
1470
1471     // Increment active thread's instruction count
1472     instsPerSwitch++;
1473
1474     // Increment thread-state's instruction count
1475     thread[tid]->numInst++;
1476     thread[tid]->numOp++;
1477
1478     // Increment thread-state's instruction stats
1479     thread[tid]->numInsts++;
1480     thread[tid]->numOps++;
1481
1482     // Count committed insts per thread stats
1483     if (!inst->isMicroop() || inst->isLastMicroop()) {
1484         committedInsts[tid]++;
1485
1486         // Count total insts committed stat
1487         totalCommittedInsts++;
1488     }
1489
1490     committedOps[tid]++;
1491
1492     // Count SMT-committed insts per thread stat
1493     if (numActiveThreads() > 1) {
1494         if (!inst->isMicroop() || inst->isLastMicroop())
1495             smtCommittedInsts[tid]++;
1496     }
1497
1498     // Instruction-Mix Stats
1499     if (inst->isLoad()) {
1500         comLoads++;
1501     } else if (inst->isStore()) {
1502         comStores++;
1503     } else if (inst->isControl()) {
1504         comBranches++;
1505     } else if (inst->isNop()) {
1506         comNops++;
1507     } else if (inst->isNonSpeculative()) {
1508         comNonSpec++;
1509     } else if (inst->isInteger()) {
1510         comInts++;
1511     } else if (inst->isFloating()) {
1512         comFloats++;
1513     }
1514
1515     // Check for instruction-count-based events.
1516     comInstEventQueue[tid]->serviceEvents(thread[tid]->numOp);
1517
1518     // Finally, remove instruction from CPU
1519     removeInst(inst);
1520 }
1521
1522 // currently unused function, but substitute repetitive code w/this function
1523 // call
1524 void
1525 InOrderCPU::addToRemoveList(DynInstPtr inst)
1526 {
1527     removeInstsThisCycle = true;
1528     if (!inst->isRemoveList()) {
1529         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1530                 "[sn:%lli] to remove list\n",
1531                 inst->threadNumber, inst->pcState(), inst->seqNum);
1532         inst->setRemoveList();
1533         removeList.push(inst->getInstListIt());
1534     }  else {
1535         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1536                 "[sn:%lli], already remove list\n",
1537                 inst->threadNumber, inst->pcState(), inst->seqNum);
1538     }
1539
1540 }
1541
1542 void
1543 InOrderCPU::removeInst(DynInstPtr inst)
1544 {
1545     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1546             "[sn:%lli]\n",
1547             inst->threadNumber, inst->pcState(), inst->seqNum);
1548
1549     removeInstsThisCycle = true;
1550
1551     // Remove the instruction.
1552     if (!inst->isRemoveList()) {
1553         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1554                 "[sn:%lli] to remove list\n",
1555                 inst->threadNumber, inst->pcState(), inst->seqNum);
1556         inst->setRemoveList();
1557         removeList.push(inst->getInstListIt());
1558     } else {
1559         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1560                 "[sn:%lli], already on remove list\n",
1561                 inst->threadNumber, inst->pcState(), inst->seqNum);
1562     }
1563
1564 }
1565
1566 void
1567 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1568 {
1569     //assert(!instList[tid].empty());
1570
1571     removeInstsThisCycle = true;
1572
1573     ListIt inst_iter = instList[tid].end();
1574
1575     inst_iter--;
1576
1577     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1578             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1579             tid, seq_num, (*inst_iter)->seqNum);
1580
1581     while ((*inst_iter)->seqNum > seq_num) {
1582
1583         bool break_loop = (inst_iter == instList[tid].begin());
1584
1585         squashInstIt(inst_iter, tid);
1586
1587         inst_iter--;
1588
1589         if (break_loop)
1590             break;
1591     }
1592 }
1593
1594
1595 inline void
1596 InOrderCPU::squashInstIt(const ListIt inst_it, ThreadID tid)
1597 {
1598     DynInstPtr inst = (*inst_it);
1599     if (inst->threadNumber == tid) {
1600         DPRINTF(InOrderCPU, "Squashing instruction, "
1601                 "[tid:%i] [sn:%lli] PC %s\n",
1602                 inst->threadNumber,
1603                 inst->seqNum,
1604                 inst->pcState());
1605
1606         inst->setSquashed();
1607         archRegDepMap[tid].remove(inst);
1608
1609         if (!inst->isRemoveList()) {
1610             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1611                     "[sn:%lli] to remove list\n",
1612                     inst->threadNumber, inst->pcState(),
1613                     inst->seqNum);
1614             inst->setRemoveList();
1615             removeList.push(inst_it);
1616         } else {
1617             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1618                     " PC %s [sn:%lli], already on remove list\n",
1619                     inst->threadNumber, inst->pcState(),
1620                     inst->seqNum);
1621         }
1622
1623     }
1624
1625 }
1626
1627
1628 void
1629 InOrderCPU::cleanUpRemovedInsts()
1630 {
1631     while (!removeList.empty()) {
1632         DPRINTF(InOrderCPU, "Removing instruction, "
1633                 "[tid:%i] [sn:%lli] PC %s\n",
1634                 (*removeList.front())->threadNumber,
1635                 (*removeList.front())->seqNum,
1636                (*removeList.front())->pcState());
1637
1638         DynInstPtr inst = *removeList.front();
1639         ThreadID tid = inst->threadNumber;
1640
1641         // Remove From Register Dependency Map, If Necessary
1642         // archRegDepMap[tid].remove(inst);
1643
1644         // Clear if Non-Speculative
1645         if (inst->staticInst &&
1646             inst->seqNum == nonSpecSeqNum[tid] &&
1647             nonSpecInstActive[tid] == true) {
1648             nonSpecInstActive[tid] = false;
1649         }
1650
1651         inst->onInstList = false;
1652
1653         instList[tid].erase(removeList.front());
1654
1655         removeList.pop();
1656     }
1657
1658     removeInstsThisCycle = false;
1659 }
1660
1661 void
1662 InOrderCPU::cleanUpRemovedEvents()
1663 {
1664     while (!cpuEventRemoveList.empty()) {
1665         Event *cpu_event = cpuEventRemoveList.front();
1666         cpuEventRemoveList.pop();
1667         delete cpu_event;
1668     }
1669 }
1670
1671
1672 void
1673 InOrderCPU::dumpInsts()
1674 {
1675     int num = 0;
1676
1677     ListIt inst_list_it = instList[0].begin();
1678
1679     cprintf("Dumping Instruction List\n");
1680
1681     while (inst_list_it != instList[0].end()) {
1682         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1683                 "Squashed:%i\n\n",
1684                 num, (*inst_list_it)->pcState(),
1685                 (*inst_list_it)->threadNumber,
1686                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1687                 (*inst_list_it)->isSquashed());
1688         inst_list_it++;
1689         ++num;
1690     }
1691 }
1692
1693 void
1694 InOrderCPU::wakeCPU()
1695 {
1696     if (/*activityRec.active() || */tickEvent.scheduled()) {
1697         DPRINTF(Activity, "CPU already running.\n");
1698         return;
1699     }
1700
1701     DPRINTF(Activity, "Waking up CPU\n");
1702
1703     Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
1704
1705     idleCycles += extra_cycles;
1706     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1707         pipelineStage[stage_num]->idleCycles += extra_cycles;
1708     }
1709
1710     numCycles += extra_cycles;
1711
1712     schedule(&tickEvent, nextCycle(curTick()));
1713 }
1714
1715 // Lots of copied full system code...place into BaseCPU class?
1716 void
1717 InOrderCPU::wakeup()
1718 {
1719     if (thread[0]->status() != ThreadContext::Suspended)
1720         return;
1721
1722     wakeCPU();
1723
1724     DPRINTF(Quiesce, "Suspended Processor woken\n");
1725     threadContexts[0]->activate();
1726 }
1727
1728 void
1729 InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
1730 {
1731     // Syscall must be non-speculative, so squash from last stage
1732     unsigned squash_stage = NumStages - 1;
1733     inst->setSquashInfo(squash_stage);
1734
1735     // Squash In Pipeline Stage
1736     pipelineStage[squash_stage]->setupSquash(inst, tid);
1737
1738     // Schedule Squash Through-out Resource Pool
1739     resPool->scheduleEvent(
1740         (InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
1741     scheduleCpuEvent(Syscall, fault, tid, inst, delay, Syscall_Pri);
1742 }
1743
1744 void
1745 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1746 {
1747     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1748
1749     DPRINTF(Activity,"Activity: syscall() called.\n");
1750
1751     // Temporarily increase this by one to account for the syscall
1752     // instruction.
1753     ++(this->thread[tid]->funcExeInst);
1754
1755     // Execute the actual syscall.
1756     this->thread[tid]->syscall(callnum);
1757
1758     // Decrease funcExeInst by one as the normal commit will handle
1759     // incrementing it.
1760     --(this->thread[tid]->funcExeInst);
1761
1762     // Clear Non-Speculative Block Variable
1763     nonSpecInstActive[tid] = false;
1764 }
1765
1766 TheISA::TLB*
1767 InOrderCPU::getITBPtr()
1768 {
1769     CacheUnit *itb_res = resPool->getInstUnit();
1770     return itb_res->tlb();
1771 }
1772
1773
1774 TheISA::TLB*
1775 InOrderCPU::getDTBPtr()
1776 {
1777     return resPool->getDataUnit()->tlb();
1778 }
1779
1780 Decoder *
1781 InOrderCPU::getDecoderPtr()
1782 {
1783     return &resPool->getInstUnit()->decoder;
1784 }
1785
1786 Fault
1787 InOrderCPU::read(DynInstPtr inst, Addr addr,
1788                  uint8_t *data, unsigned size, unsigned flags)
1789 {
1790     return resPool->getDataUnit()->read(inst, addr, data, size, flags);
1791 }
1792
1793 Fault
1794 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1795                   Addr addr, unsigned flags, uint64_t *write_res)
1796 {
1797     return resPool->getDataUnit()->write(inst, data, size, addr, flags,
1798                                          write_res);
1799 }