2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "arch/utility.hh"
35 #include "base/bigint.hh"
36 #include "config/full_system.hh"
37 #include "config/the_isa.hh"
38 #include "cpu/inorder/resources/resource_list.hh"
39 #include "cpu/inorder/cpu.hh"
40 #include "cpu/inorder/first_stage.hh"
41 #include "cpu/inorder/inorder_dyn_inst.hh"
42 #include "cpu/inorder/pipeline_traits.hh"
43 #include "cpu/inorder/resource_pool.hh"
44 #include "cpu/inorder/thread_context.hh"
45 #include "cpu/inorder/thread_state.hh"
46 #include "cpu/activity.hh"
47 #include "cpu/base.hh"
48 #include "cpu/exetrace.hh"
49 #include "cpu/simple_thread.hh"
50 #include "cpu/thread_context.hh"
51 #include "debug/Activity.hh"
52 #include "debug/InOrderCPU.hh"
53 #include "debug/RefCount.hh"
54 #include "debug/SkedCache.hh"
55 #include "debug/Quiesce.hh"
56 #include "params/InOrderCPU.hh"
57 #include "sim/process.hh"
58 #include "sim/stat_control.hh"
61 #include "cpu/quiesce_event.hh"
62 #include "sim/system.hh"
65 #if THE_ISA == ALPHA_ISA
66 #include "arch/alpha/osfpal.hh"
70 using namespace TheISA
;
71 using namespace ThePipeline
;
73 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
74 : Event(CPU_Tick_Pri
), cpu(c
)
79 InOrderCPU::TickEvent::process()
86 InOrderCPU::TickEvent::description()
88 return "InOrderCPU tick event";
91 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
92 Fault fault
, ThreadID _tid
, DynInstPtr inst
,
93 CPUEventPri event_pri
)
94 : Event(event_pri
), cpu(_cpu
)
96 setEvent(e_type
, fault
, _tid
, inst
);
100 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
103 "ActivateNextReadyThread",
109 "SquashFromMemStall",
114 InOrderCPU::CPUEvent::process()
116 switch (cpuEventType
)
119 cpu
->activateThread(tid
);
120 cpu
->resPool
->activateThread(tid
);
123 case ActivateNextReadyThread
:
124 cpu
->activateNextReadyThread();
127 case DeactivateThread
:
128 cpu
->deactivateThread(tid
);
129 cpu
->resPool
->deactivateThread(tid
);
133 cpu
->haltThread(tid
);
134 cpu
->resPool
->deactivateThread(tid
);
138 cpu
->suspendThread(tid
);
139 cpu
->resPool
->suspendThread(tid
);
142 case SquashFromMemStall
:
143 cpu
->squashDueToMemStall(inst
->squashingStage
, inst
->seqNum
, tid
);
144 cpu
->resPool
->squashDueToMemStall(inst
, inst
->squashingStage
,
149 DPRINTF(InOrderCPU
, "Trapping CPU\n");
150 cpu
->trap(fault
, tid
, inst
);
151 cpu
->resPool
->trap(fault
, tid
, inst
);
152 cpu
->trapPending
[tid
] = false;
157 cpu
->syscall(inst
->syscallNum
, tid
);
158 cpu
->resPool
->trap(fault
, tid
, inst
);
162 fatal("Unrecognized Event Type %s", eventNames
[cpuEventType
]);
165 cpu
->cpuEventRemoveList
.push(this);
171 InOrderCPU::CPUEvent::description()
173 return "InOrderCPU event";
177 InOrderCPU::CPUEvent::scheduleEvent(int delay
)
179 assert(!scheduled() || squashed());
180 cpu
->reschedule(this, cpu
->nextCycle(curTick() + cpu
->ticks(delay
)), true);
184 InOrderCPU::CPUEvent::unscheduleEvent()
190 InOrderCPU::InOrderCPU(Params
*params
)
192 cpu_id(params
->cpu_id
),
196 stageWidth(params
->stageWidth
),
198 removeInstsThisCycle(false),
199 activityRec(params
->name
, NumStages
, 10, params
->activity
),
201 system(params
->system
),
202 #endif // FULL_SYSTEM
208 deferRegistration(false/*params->deferRegistration*/),
209 stageTracing(params
->stageTracing
),
215 resPool
= new ResourcePool(this, params
);
217 // Resize for Multithreading CPUs
218 thread
.resize(numThreads
);
221 ThreadID active_threads
= params
->workload
.size();
223 if (active_threads
> MaxThreads
) {
224 panic("Workload Size too large. Increase the 'MaxThreads'"
225 "in your InOrder implementation or "
226 "edit your workload size.");
230 if (active_threads
> 1) {
231 threadModel
= (InOrderCPU::ThreadModel
) params
->threadModel
;
233 if (threadModel
== SMT
) {
234 DPRINTF(InOrderCPU
, "Setting Thread Model to SMT.\n");
235 } else if (threadModel
== SwitchOnCacheMiss
) {
236 DPRINTF(InOrderCPU
, "Setting Thread Model to "
237 "Switch On Cache Miss\n");
241 threadModel
= Single
;
248 // Bind the fetch & data ports from the resource pool.
249 fetchPortIdx
= resPool
->getPortIdx(params
->fetchMemPort
);
250 if (fetchPortIdx
== 0) {
251 fatal("Unable to find port to fetch instructions from.\n");
254 dataPortIdx
= resPool
->getPortIdx(params
->dataMemPort
);
255 if (dataPortIdx
== 0) {
256 fatal("Unable to find port for data.\n");
259 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
261 lastCommittedPC
[tid
].set(0);
264 // SMT is not supported in FS mode yet.
265 assert(numThreads
== 1);
266 thread
[tid
] = new Thread(this, 0);
268 if (tid
< (ThreadID
)params
->workload
.size()) {
269 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
270 tid
, params
->workload
[tid
]->prog_fname
);
272 new Thread(this, tid
, params
->workload
[tid
]);
274 //Allocate Empty thread so M5 can use later
275 //when scheduling threads to CPU
276 Process
* dummy_proc
= params
->workload
[0];
277 thread
[tid
] = new Thread(this, tid
, dummy_proc
);
280 // Eventually set this with parameters...
284 // Setup the TC that will serve as the interface to the threads/CPU.
285 InOrderThreadContext
*tc
= new InOrderThreadContext
;
287 tc
->thread
= thread
[tid
];
290 // Setup quiesce event.
291 this->thread
[tid
]->quiesceEvent
= new EndQuiesceEvent(tc
);
294 // Give the thread the TC.
295 thread
[tid
]->tc
= tc
;
296 thread
[tid
]->setFuncExeInst(0);
297 globalSeqNum
[tid
] = 1;
299 // Add the TC to the CPU's list of TC's.
300 this->threadContexts
.push_back(tc
);
303 // Initialize TimeBuffer Stage Queues
304 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
305 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
306 stageQueue
[stNum
]->id(stNum
);
310 // Set Up Pipeline Stages
311 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
313 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
315 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
317 pipelineStage
[stNum
]->setCPU(this);
318 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
319 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
321 // Take Care of 1st/Nth stages
323 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
324 if (stNum
< NumStages
- 1)
325 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
328 // Initialize thread specific variables
329 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
330 archRegDepMap
[tid
].setCPU(this);
332 nonSpecInstActive
[tid
] = false;
333 nonSpecSeqNum
[tid
] = 0;
335 squashSeqNum
[tid
] = MaxAddr
;
336 lastSquashCycle
[tid
] = 0;
338 memset(intRegs
[tid
], 0, sizeof(intRegs
[tid
]));
339 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
342 // Define dummy instructions and resource requests to be used.
343 dummyInst
[tid
] = new InOrderDynInst(this,
349 dummyReq
[tid
] = new ResourceRequest(resPool
->getResource(0));
352 // Use this dummy inst to force squashing behind every instruction
354 dummyTrapInst
[tid
] = new InOrderDynInst(this, NULL
, 0, 0, 0);
355 dummyTrapInst
[tid
]->seqNum
= 0;
356 dummyTrapInst
[tid
]->squashSeqNum
= 0;
357 dummyTrapInst
[tid
]->setTid(tid
);
360 trapPending
[tid
] = false;
364 dummyReqInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
365 dummyReqInst
->setSquashed();
366 dummyReqInst
->resetInstCount();
368 dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
369 dummyBufferInst
->setSquashed();
370 dummyBufferInst
->resetInstCount();
372 endOfSkedIt
= skedCache
.end();
373 frontEndSked
= createFrontEndSked();
374 faultSked
= createFaultSked();
376 lastRunningCycle
= curTick();
381 // Schedule First Tick Event, CPU will reschedule itself from here on out.
382 scheduleTickEvent(0);
385 InOrderCPU::~InOrderCPU()
389 SkedCacheIt sked_it
= skedCache
.begin();
390 SkedCacheIt sked_end
= skedCache
.end();
392 while (sked_it
!= sked_end
) {
393 delete (*sked_it
).second
;
399 m5::hash_map
<InOrderCPU::SkedID
, ThePipeline::RSkedPtr
> InOrderCPU::skedCache
;
402 InOrderCPU::createFrontEndSked()
404 RSkedPtr res_sked
= new ResourceSked();
406 StageScheduler
F(res_sked
, stage_num
++);
407 StageScheduler
D(res_sked
, stage_num
++);
410 F
.needs(FetchSeq
, FetchSeqUnit::AssignNextPC
);
411 F
.needs(ICache
, FetchUnit::InitiateFetch
);
414 D
.needs(ICache
, FetchUnit::CompleteFetch
);
415 D
.needs(Decode
, DecodeUnit::DecodeInst
);
416 D
.needs(BPred
, BranchPredictor::PredictBranch
);
417 D
.needs(FetchSeq
, FetchSeqUnit::UpdateTargetPC
);
420 DPRINTF(SkedCache
, "Resource Sked created for instruction Front End\n");
426 InOrderCPU::createFaultSked()
428 RSkedPtr res_sked
= new ResourceSked();
429 StageScheduler
W(res_sked
, NumStages
- 1);
430 W
.needs(Grad
, GraduationUnit::CheckFault
);
431 DPRINTF(SkedCache
, "Resource Sked created for instruction Faults\n");
436 InOrderCPU::createBackEndSked(DynInstPtr inst
)
438 RSkedPtr res_sked
= lookupSked(inst
);
439 if (res_sked
!= NULL
) {
440 DPRINTF(SkedCache
, "Found %s in sked cache.\n",
444 res_sked
= new ResourceSked();
447 int stage_num
= ThePipeline::BackEndStartStage
;
448 StageScheduler
X(res_sked
, stage_num
++);
449 StageScheduler
M(res_sked
, stage_num
++);
450 StageScheduler
W(res_sked
, stage_num
++);
452 if (!inst
->staticInst
) {
453 warn_once("Static Instruction Object Not Set. Can't Create"
454 " Back End Schedule");
459 X
.needs(RegManager
, UseDefUnit::MarkDestRegs
);
460 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
461 if (!idx
|| !inst
->isStore()) {
462 X
.needs(RegManager
, UseDefUnit::ReadSrcReg
, idx
);
466 //@todo: schedule non-spec insts to operate on this cycle
467 // as long as all previous insts are done
468 if ( inst
->isNonSpeculative() ) {
469 // skip execution of non speculative insts until later
470 } else if ( inst
->isMemRef() ) {
471 if ( inst
->isLoad() ) {
472 X
.needs(AGEN
, AGENUnit::GenerateAddr
);
474 } else if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
475 X
.needs(MDU
, MultDivUnit::StartMultDiv
);
477 X
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
481 if (!inst
->isNonSpeculative()) {
482 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
483 M
.needs(MDU
, MultDivUnit::EndMultDiv
);
486 if ( inst
->isLoad() ) {
487 M
.needs(DCache
, CacheUnit::InitiateReadData
);
489 M
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
490 } else if ( inst
->isStore() ) {
491 for (int i
= 1; i
< inst
->numSrcRegs(); i
++ ) {
492 M
.needs(RegManager
, UseDefUnit::ReadSrcReg
, i
);
494 M
.needs(AGEN
, AGENUnit::GenerateAddr
);
495 M
.needs(DCache
, CacheUnit::InitiateWriteData
);
497 M
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
502 if (!inst
->isNonSpeculative()) {
503 if ( inst
->isLoad() ) {
504 W
.needs(DCache
, CacheUnit::CompleteReadData
);
506 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
507 } else if ( inst
->isStore() ) {
508 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
510 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
513 // Finally, Execute Speculative Data
514 if (inst
->isMemRef()) {
515 if (inst
->isLoad()) {
516 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
517 W
.needs(DCache
, CacheUnit::InitiateReadData
);
519 W
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
520 W
.needs(DCache
, CacheUnit::CompleteReadData
);
522 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
523 } else if (inst
->isStore()) {
524 if ( inst
->numSrcRegs() >= 2 ) {
525 W
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
527 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
528 W
.needs(DCache
, CacheUnit::InitiateWriteData
);
530 W
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
531 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
533 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
536 W
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
540 W
.needs(Grad
, GraduationUnit::CheckFault
);
542 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
543 W
.needs(RegManager
, UseDefUnit::WriteDestReg
, idx
);
546 if (inst
->isControl())
547 W
.needs(BPred
, BranchPredictor::UpdatePredictor
);
549 W
.needs(Grad
, GraduationUnit::GraduateInst
);
551 // Insert Back Schedule into our cache of
552 // resource schedules
553 addToSkedCache(inst
, res_sked
);
555 DPRINTF(SkedCache
, "Back End Sked Created for instruction: %s (%08p)\n",
556 inst
->instName(), inst
->getMachInst());
563 InOrderCPU::regStats()
565 /* Register the Resource Pool's stats here.*/
568 /* Register for each Pipeline Stage */
569 for (int stage_num
=0; stage_num
< ThePipeline::NumStages
; stage_num
++) {
570 pipelineStage
[stage_num
]->regStats();
573 /* Register any of the InOrderCPU's stats here.*/
575 .name(name() + ".instsPerContextSwitch")
576 .desc("Instructions Committed Per Context Switch")
577 .prereq(instsPerCtxtSwitch
);
580 .name(name() + ".contextSwitches")
581 .desc("Number of context switches");
584 .name(name() + ".comLoads")
585 .desc("Number of Load instructions committed");
588 .name(name() + ".comStores")
589 .desc("Number of Store instructions committed");
592 .name(name() + ".comBranches")
593 .desc("Number of Branches instructions committed");
596 .name(name() + ".comNops")
597 .desc("Number of Nop instructions committed");
600 .name(name() + ".comNonSpec")
601 .desc("Number of Non-Speculative instructions committed");
604 .name(name() + ".comInts")
605 .desc("Number of Integer instructions committed");
608 .name(name() + ".comFloats")
609 .desc("Number of Floating Point instructions committed");
612 .name(name() + ".timesIdled")
613 .desc("Number of times that the entire CPU went into an idle state and"
614 " unscheduled itself")
618 .name(name() + ".idleCycles")
619 .desc("Number of cycles cpu's stages were not processed");
622 .name(name() + ".runCycles")
623 .desc("Number of cycles cpu stages are processed.");
626 .name(name() + ".activity")
627 .desc("Percentage of cycles cpu is active")
629 activity
= (runCycles
/ numCycles
) * 100;
633 .name(name() + ".threadCycles")
634 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
637 .name(name() + ".smtCycles")
638 .desc("Total number of cycles that the CPU was in SMT-mode");
642 .name(name() + ".committedInsts")
643 .desc("Number of Instructions Simulated (Per-Thread)");
647 .name(name() + ".smtCommittedInsts")
648 .desc("Number of SMT Instructions Simulated (Per-Thread)");
651 .name(name() + ".committedInsts_total")
652 .desc("Number of Instructions Simulated (Total)");
655 .name(name() + ".cpi")
656 .desc("CPI: Cycles Per Instruction (Per-Thread)")
658 cpi
= numCycles
/ committedInsts
;
661 .name(name() + ".smt_cpi")
662 .desc("CPI: Total SMT-CPI")
664 smtCpi
= smtCycles
/ smtCommittedInsts
;
667 .name(name() + ".cpi_total")
668 .desc("CPI: Total CPI of All Threads")
670 totalCpi
= numCycles
/ totalCommittedInsts
;
673 .name(name() + ".ipc")
674 .desc("IPC: Instructions Per Cycle (Per-Thread)")
676 ipc
= committedInsts
/ numCycles
;
679 .name(name() + ".smt_ipc")
680 .desc("IPC: Total SMT-IPC")
682 smtIpc
= smtCommittedInsts
/ smtCycles
;
685 .name(name() + ".ipc_total")
686 .desc("IPC: Total IPC of All Threads")
688 totalIpc
= totalCommittedInsts
/ numCycles
;
697 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
702 checkForInterrupts();
705 bool pipes_idle
= true;
706 //Tick each of the stages
707 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
708 pipelineStage
[stNum
]->tick();
710 pipes_idle
= pipes_idle
&& pipelineStage
[stNum
]->idle
;
718 // Now advance the time buffers one tick
719 timeBuffer
.advance();
720 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
721 stageQueue
[sqNum
]->advance();
723 activityRec
.advance();
725 // Any squashed events, or insts then remove them now
726 cleanUpRemovedEvents();
727 cleanUpRemovedInsts();
729 // Re-schedule CPU for this cycle
730 if (!tickEvent
.scheduled()) {
731 if (_status
== SwitchedOut
) {
733 lastRunningCycle
= curTick();
734 } else if (!activityRec
.active()) {
735 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
736 lastRunningCycle
= curTick();
739 //Tick next_tick = curTick() + cycles(1);
740 //tickEvent.schedule(next_tick);
741 schedule(&tickEvent
, nextCycle(curTick() + 1));
742 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n",
743 nextCycle(curTick() + 1));
748 updateThreadPriority();
755 if (!deferRegistration
) {
756 registerThreadContexts();
759 // Set inSyscall so that the CPU doesn't squash when initially
760 // setting up registers.
761 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
762 thread
[tid
]->inSyscall
= true;
765 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
766 ThreadContext
*src_tc
= threadContexts
[tid
];
767 TheISA::initCPU(src_tc
, src_tc
->contextId());
768 // Initialise the ThreadContext's memory proxies
769 thread
[tid
]->initMemProxies(thread
[tid
]->getTC());
774 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
775 thread
[tid
]->inSyscall
= false;
777 // Call Initializiation Routine for Resource Pool
782 InOrderCPU::getPort(const std::string
&if_name
, int idx
)
784 return resPool
->getPort(if_name
, idx
);
789 InOrderCPU::hwrei(ThreadID tid
)
791 #if THE_ISA == ALPHA_ISA
792 // Need to clear the lock flag upon returning from an interrupt.
793 setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG
, false, tid
);
795 thread
[tid
]->kernelStats
->hwrei();
796 // FIXME: XXX check for interrupts? XXX
804 InOrderCPU::simPalCheck(int palFunc
, ThreadID tid
)
806 #if THE_ISA == ALPHA_ISA
807 if (this->thread
[tid
]->kernelStats
)
808 this->thread
[tid
]->kernelStats
->callpal(palFunc
,
809 this->threadContexts
[tid
]);
814 if (--System::numSystemsRunning
== 0)
815 exitSimLoop("all cpus halted");
820 if (this->system
->breakpoint())
829 InOrderCPU::checkForInterrupts()
831 for (int i
= 0; i
< threadContexts
.size(); i
++) {
832 ThreadContext
*tc
= threadContexts
[i
];
834 if (interrupts
->checkInterrupts(tc
)) {
835 Fault interrupt
= interrupts
->getInterrupt(tc
);
837 if (interrupt
!= NoFault
) {
838 DPRINTF(Interrupt
, "Processing Intterupt for [tid:%i].\n",
841 ThreadID tid
= tc
->threadId();
842 interrupts
->updateIntrInfo(tc
);
844 // Squash from Last Stage in Pipeline
845 unsigned last_stage
= NumStages
- 1;
846 dummyTrapInst
[tid
]->squashingStage
= last_stage
;
847 pipelineStage
[last_stage
]->setupSquash(dummyTrapInst
[tid
],
850 // By default, setupSquash will always squash from stage + 1
851 pipelineStage
[BackEndStartStage
- 1]->setupSquash(dummyTrapInst
[tid
],
854 // Schedule Squash Through-out Resource Pool
855 resPool
->scheduleEvent(
856 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
,
857 dummyTrapInst
[tid
], 0);
859 // Finally, Setup Trap to happen at end of cycle
860 trapContext(interrupt
, tid
, dummyTrapInst
[tid
]);
867 InOrderCPU::getInterrupts()
869 // Check if there are any outstanding interrupts
870 return interrupts
->getInterrupt(threadContexts
[0]);
875 InOrderCPU::processInterrupts(Fault interrupt
)
877 // Check for interrupts here. For now can copy the code that
878 // exists within isa_fullsys_traits.hh. Also assume that thread 0
879 // is the one that handles the interrupts.
880 // @todo: Possibly consolidate the interrupt checking code.
881 // @todo: Allow other threads to handle interrupts.
883 assert(interrupt
!= NoFault
);
884 interrupts
->updateIntrInfo(threadContexts
[0]);
886 DPRINTF(InOrderCPU
, "Interrupt %s being handled\n", interrupt
->name());
888 // Note: Context ID ok here? Impl. of FS mode needs to revisit this
889 trap(interrupt
, threadContexts
[0]->contextId(), dummyBufferInst
);
895 InOrderCPU::trapContext(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
897 scheduleCpuEvent(Trap
, fault
, tid
, inst
, delay
);
898 trapPending
[tid
] = true;
902 InOrderCPU::trap(Fault fault
, ThreadID tid
, DynInstPtr inst
)
904 fault
->invoke(tcBase(tid
), inst
->staticInst
);
905 removePipelineStalls(tid
);
909 InOrderCPU::squashFromMemStall(DynInstPtr inst
, ThreadID tid
, int delay
)
911 scheduleCpuEvent(SquashFromMemStall
, NoFault
, tid
, inst
, delay
);
916 InOrderCPU::squashDueToMemStall(int stage_num
, InstSeqNum seq_num
,
919 DPRINTF(InOrderCPU
, "Squashing Pipeline Stages Due to Memory Stall...\n");
921 // Squash all instructions in each stage including
922 // instruction that caused the squash (seq_num - 1)
923 // NOTE: The stage bandwidth needs to be cleared so thats why
924 // the stalling instruction is squashed as well. The stalled
925 // instruction is previously placed in another intermediate buffer
926 // while it's stall is being handled.
927 InstSeqNum squash_seq_num
= seq_num
- 1;
929 for (int stNum
=stage_num
; stNum
>= 0 ; stNum
--) {
930 pipelineStage
[stNum
]->squashDueToMemStall(squash_seq_num
, tid
);
935 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
936 ThreadID tid
, DynInstPtr inst
,
937 unsigned delay
, CPUEventPri event_pri
)
939 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, inst
,
942 Tick sked_tick
= nextCycle(curTick() + ticks(delay
));
944 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
945 eventNames
[c_event
], curTick() + delay
, tid
);
946 schedule(cpu_event
, sked_tick
);
948 cpu_event
->process();
949 cpuEventRemoveList
.push(cpu_event
);
952 // Broadcast event to the Resource Pool
953 // Need to reset tid just in case this is a dummy instruction
955 resPool
->scheduleEvent(c_event
, inst
, 0, 0, tid
);
959 InOrderCPU::isThreadActive(ThreadID tid
)
961 list
<ThreadID
>::iterator isActive
=
962 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
964 return (isActive
!= activeThreads
.end());
968 InOrderCPU::isThreadReady(ThreadID tid
)
970 list
<ThreadID
>::iterator isReady
=
971 std::find(readyThreads
.begin(), readyThreads
.end(), tid
);
973 return (isReady
!= readyThreads
.end());
977 InOrderCPU::isThreadSuspended(ThreadID tid
)
979 list
<ThreadID
>::iterator isSuspended
=
980 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
982 return (isSuspended
!= suspendedThreads
.end());
986 InOrderCPU::activateNextReadyThread()
988 if (readyThreads
.size() >= 1) {
989 ThreadID ready_tid
= readyThreads
.front();
991 // Activate in Pipeline
992 activateThread(ready_tid
);
994 // Activate in Resource Pool
995 resPool
->activateThread(ready_tid
);
997 list
<ThreadID
>::iterator ready_it
=
998 std::find(readyThreads
.begin(), readyThreads
.end(), ready_tid
);
999 readyThreads
.erase(ready_it
);
1002 "Attempting to activate new thread, but No Ready Threads to"
1005 "Unable to switch to next active thread.\n");
1010 InOrderCPU::activateThread(ThreadID tid
)
1012 if (isThreadSuspended(tid
)) {
1014 "Removing [tid:%i] from suspended threads list.\n", tid
);
1016 list
<ThreadID
>::iterator susp_it
=
1017 std::find(suspendedThreads
.begin(), suspendedThreads
.end(),
1019 suspendedThreads
.erase(susp_it
);
1022 if (threadModel
== SwitchOnCacheMiss
&&
1023 numActiveThreads() == 1) {
1025 "Ignoring activation of [tid:%i], since [tid:%i] is "
1026 "already running.\n", tid
, activeThreadId());
1028 DPRINTF(InOrderCPU
,"Placing [tid:%i] on ready threads list\n",
1031 readyThreads
.push_back(tid
);
1033 } else if (!isThreadActive(tid
)) {
1035 "Adding [tid:%i] to active threads list.\n", tid
);
1036 activeThreads
.push_back(tid
);
1038 activateThreadInPipeline(tid
);
1040 thread
[tid
]->lastActivate
= curTick();
1042 tcBase(tid
)->setStatus(ThreadContext::Active
);
1051 InOrderCPU::activateThreadInPipeline(ThreadID tid
)
1053 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
1054 pipelineStage
[stNum
]->activateThread(tid
);
1059 InOrderCPU::deactivateContext(ThreadID tid
, int delay
)
1061 DPRINTF(InOrderCPU
,"[tid:%i]: Deactivating ...\n", tid
);
1063 scheduleCpuEvent(DeactivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1065 // Be sure to signal that there's some activity so the CPU doesn't
1066 // deschedule itself.
1067 activityRec
.activity();
1073 InOrderCPU::deactivateThread(ThreadID tid
)
1075 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
1077 if (isThreadActive(tid
)) {
1078 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
1080 list
<ThreadID
>::iterator thread_it
=
1081 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
1083 removePipelineStalls(*thread_it
);
1085 activeThreads
.erase(thread_it
);
1087 // Ideally, this should be triggered from the
1088 // suspendContext/Thread functions
1089 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1092 assert(!isThreadActive(tid
));
1096 InOrderCPU::removePipelineStalls(ThreadID tid
)
1098 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
1101 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
1102 pipelineStage
[stNum
]->removeStalls(tid
);
1108 InOrderCPU::updateThreadPriority()
1110 if (activeThreads
.size() > 1)
1112 //DEFAULT TO ROUND ROBIN SCHEME
1113 //e.g. Move highest priority to end of thread list
1114 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
1116 unsigned high_thread
= *list_begin
;
1118 activeThreads
.erase(list_begin
);
1120 activeThreads
.push_back(high_thread
);
1125 InOrderCPU::tickThreadStats()
1127 /** Keep track of cycles that each thread is active */
1128 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
1129 while (thread_it
!= activeThreads
.end()) {
1130 threadCycles
[*thread_it
]++;
1134 // Keep track of cycles where SMT is active
1135 if (activeThreads
.size() > 1) {
1141 InOrderCPU::activateContext(ThreadID tid
, int delay
)
1143 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
1146 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1148 // Be sure to signal that there's some activity so the CPU doesn't
1149 // deschedule itself.
1150 activityRec
.activity();
1156 InOrderCPU::activateNextReadyContext(int delay
)
1158 DPRINTF(InOrderCPU
,"Activating next ready thread\n");
1160 scheduleCpuEvent(ActivateNextReadyThread
, NoFault
, 0/*tid*/, dummyInst
[0],
1161 delay
, ActivateNextReadyThread_Pri
);
1163 // Be sure to signal that there's some activity so the CPU doesn't
1164 // deschedule itself.
1165 activityRec
.activity();
1171 InOrderCPU::haltContext(ThreadID tid
, int delay
)
1173 DPRINTF(InOrderCPU
, "[tid:%i]: Calling Halt Context...\n", tid
);
1175 scheduleCpuEvent(HaltThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1177 activityRec
.activity();
1181 InOrderCPU::haltThread(ThreadID tid
)
1183 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Halted Threads List...\n", tid
);
1184 deactivateThread(tid
);
1185 squashThreadInPipeline(tid
);
1186 haltedThreads
.push_back(tid
);
1188 tcBase(tid
)->setStatus(ThreadContext::Halted
);
1190 if (threadModel
== SwitchOnCacheMiss
) {
1191 activateNextReadyContext();
1196 InOrderCPU::suspendContext(ThreadID tid
, int delay
)
1198 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1202 InOrderCPU::suspendThread(ThreadID tid
)
1204 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Suspended Threads List...\n",
1206 deactivateThread(tid
);
1207 suspendedThreads
.push_back(tid
);
1208 thread
[tid
]->lastSuspend
= curTick();
1210 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1214 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
1216 //Squash all instructions in each stage
1217 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
1218 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
1223 InOrderCPU::getPipeStage(int stage_num
)
1225 return pipelineStage
[stage_num
];
1230 InOrderCPU::flattenRegIdx(RegIndex reg_idx
, RegType
®_type
, ThreadID tid
)
1232 if (reg_idx
< FP_Base_DepTag
) {
1234 return isa
[tid
].flattenIntIndex(reg_idx
);
1235 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1236 reg_type
= FloatType
;
1237 reg_idx
-= FP_Base_DepTag
;
1238 return isa
[tid
].flattenFloatIndex(reg_idx
);
1240 reg_type
= MiscType
;
1241 return reg_idx
- TheISA::Ctrl_Base_DepTag
;
1246 InOrderCPU::readIntReg(RegIndex reg_idx
, ThreadID tid
)
1248 DPRINTF(IntRegs
, "[tid:%i]: Reading Int. Reg %i as %x\n",
1249 tid
, reg_idx
, intRegs
[tid
][reg_idx
]);
1251 return intRegs
[tid
][reg_idx
];
1255 InOrderCPU::readFloatReg(RegIndex reg_idx
, ThreadID tid
)
1257 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1258 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1260 return floatRegs
.f
[tid
][reg_idx
];
1264 InOrderCPU::readFloatRegBits(RegIndex reg_idx
, ThreadID tid
)
1266 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1267 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1269 return floatRegs
.i
[tid
][reg_idx
];
1273 InOrderCPU::setIntReg(RegIndex reg_idx
, uint64_t val
, ThreadID tid
)
1275 if (reg_idx
== TheISA::ZeroReg
) {
1276 DPRINTF(IntRegs
, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1277 "(Int. Reg %i) to %x\n", tid
, reg_idx
, val
);
1280 DPRINTF(IntRegs
, "[tid:%i]: Setting Int. Reg %i to %x\n",
1283 intRegs
[tid
][reg_idx
] = val
;
1289 InOrderCPU::setFloatReg(RegIndex reg_idx
, FloatReg val
, ThreadID tid
)
1291 floatRegs
.f
[tid
][reg_idx
] = val
;
1292 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1295 floatRegs
.i
[tid
][reg_idx
],
1296 floatRegs
.f
[tid
][reg_idx
]);
1301 InOrderCPU::setFloatRegBits(RegIndex reg_idx
, FloatRegBits val
, ThreadID tid
)
1303 floatRegs
.i
[tid
][reg_idx
] = val
;
1304 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1307 floatRegs
.i
[tid
][reg_idx
],
1308 floatRegs
.f
[tid
][reg_idx
]);
1312 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
1314 // If Default value is set, then retrieve target thread
1315 if (tid
== InvalidThreadID
) {
1316 tid
= TheISA::getTargetThread(tcBase(tid
));
1319 if (reg_idx
< FP_Base_DepTag
) {
1320 // Integer Register File
1321 return readIntReg(reg_idx
, tid
);
1322 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1323 // Float Register File
1324 reg_idx
-= FP_Base_DepTag
;
1325 return readFloatRegBits(reg_idx
, tid
);
1327 reg_idx
-= Ctrl_Base_DepTag
;
1328 return readMiscReg(reg_idx
, tid
); // Misc. Register File
1332 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
1335 // If Default value is set, then retrieve target thread
1336 if (tid
== InvalidThreadID
) {
1337 tid
= TheISA::getTargetThread(tcBase(tid
));
1340 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
1341 setIntReg(reg_idx
, val
, tid
);
1342 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
1343 reg_idx
-= FP_Base_DepTag
;
1344 setFloatRegBits(reg_idx
, val
, tid
);
1346 reg_idx
-= Ctrl_Base_DepTag
;
1347 setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
1352 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1354 return isa
[tid
].readMiscRegNoEffect(misc_reg
);
1358 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
1360 return isa
[tid
].readMiscReg(misc_reg
, tcBase(tid
));
1364 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1366 isa
[tid
].setMiscRegNoEffect(misc_reg
, val
);
1370 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1372 isa
[tid
].setMiscReg(misc_reg
, val
, tcBase(tid
));
1377 InOrderCPU::addInst(DynInstPtr inst
)
1379 ThreadID tid
= inst
->readTid();
1381 instList
[tid
].push_back(inst
);
1383 return --(instList
[tid
].end());
1387 InOrderCPU::findInst(InstSeqNum seq_num
, ThreadID tid
)
1389 ListIt it
= instList
[tid
].begin();
1390 ListIt end
= instList
[tid
].end();
1393 if ((*it
)->seqNum
== seq_num
)
1395 else if ((*it
)->seqNum
> seq_num
)
1401 return instList
[tid
].end();
1405 InOrderCPU::updateContextSwitchStats()
1407 // Set Average Stat Here, then reset to 0
1408 instsPerCtxtSwitch
= instsPerSwitch
;
1414 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1416 // Set the nextPC to be fetched if this is the last instruction
1419 // This contributes to the precise state of the CPU
1420 // which can be used when restoring a thread to the CPU after after any
1421 // type of context switching activity (fork, exception, etc.)
1422 TheISA::PCState comm_pc
= inst
->pcState();
1423 lastCommittedPC
[tid
] = comm_pc
;
1424 TheISA::advancePC(comm_pc
, inst
->staticInst
);
1425 pcState(comm_pc
, tid
);
1427 //@todo: may be unnecessary with new-ISA-specific branch handling code
1428 if (inst
->isControl()) {
1429 thread
[tid
]->lastGradIsBranch
= true;
1430 thread
[tid
]->lastBranchPC
= inst
->pcState();
1431 TheISA::advancePC(thread
[tid
]->lastBranchPC
, inst
->staticInst
);
1433 thread
[tid
]->lastGradIsBranch
= false;
1437 // Finalize Trace Data For Instruction
1438 if (inst
->traceData
) {
1439 //inst->traceData->setCycle(curTick());
1440 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1441 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1442 inst
->traceData
->dump();
1443 delete inst
->traceData
;
1444 inst
->traceData
= NULL
;
1447 // Increment active thread's instruction count
1450 // Increment thread-state's instruction count
1451 thread
[tid
]->numInst
++;
1453 // Increment thread-state's instruction stats
1454 thread
[tid
]->numInsts
++;
1456 // Count committed insts per thread stats
1457 committedInsts
[tid
]++;
1459 // Count total insts committed stat
1460 totalCommittedInsts
++;
1462 // Count SMT-committed insts per thread stat
1463 if (numActiveThreads() > 1) {
1464 smtCommittedInsts
[tid
]++;
1467 // Instruction-Mix Stats
1468 if (inst
->isLoad()) {
1470 } else if (inst
->isStore()) {
1472 } else if (inst
->isControl()) {
1474 } else if (inst
->isNop()) {
1476 } else if (inst
->isNonSpeculative()) {
1478 } else if (inst
->isInteger()) {
1480 } else if (inst
->isFloating()) {
1484 // Check for instruction-count-based events.
1485 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numInst
);
1487 // Finally, remove instruction from CPU
1491 // currently unused function, but substitute repetitive code w/this function
1494 InOrderCPU::addToRemoveList(DynInstPtr inst
)
1496 removeInstsThisCycle
= true;
1497 if (!inst
->isRemoveList()) {
1498 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1499 "[sn:%lli] to remove list\n",
1500 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1501 inst
->setRemoveList();
1502 removeList
.push(inst
->getInstListIt());
1504 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1505 "[sn:%lli], already remove list\n",
1506 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1512 InOrderCPU::removeInst(DynInstPtr inst
)
1514 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %s "
1516 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1518 removeInstsThisCycle
= true;
1520 // Remove the instruction.
1521 if (!inst
->isRemoveList()) {
1522 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1523 "[sn:%lli] to remove list\n",
1524 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1525 inst
->setRemoveList();
1526 removeList
.push(inst
->getInstListIt());
1528 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1529 "[sn:%lli], already on remove list\n",
1530 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1536 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1538 //assert(!instList[tid].empty());
1540 removeInstsThisCycle
= true;
1542 ListIt inst_iter
= instList
[tid
].end();
1546 DPRINTF(InOrderCPU
, "Squashing instructions from CPU instruction "
1547 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1548 tid
, seq_num
, (*inst_iter
)->seqNum
);
1550 while ((*inst_iter
)->seqNum
> seq_num
) {
1552 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1554 squashInstIt(inst_iter
, tid
);
1565 InOrderCPU::squashInstIt(const ListIt inst_it
, ThreadID tid
)
1567 DynInstPtr inst
= (*inst_it
);
1568 if (inst
->threadNumber
== tid
) {
1569 DPRINTF(InOrderCPU
, "Squashing instruction, "
1570 "[tid:%i] [sn:%lli] PC %s\n",
1575 inst
->setSquashed();
1576 archRegDepMap
[tid
].remove(inst
);
1578 if (!inst
->isRemoveList()) {
1579 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1580 "[sn:%lli] to remove list\n",
1581 inst
->threadNumber
, inst
->pcState(),
1583 inst
->setRemoveList();
1584 removeList
.push(inst_it
);
1586 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i]"
1587 " PC %s [sn:%lli], already on remove list\n",
1588 inst
->threadNumber
, inst
->pcState(),
1598 InOrderCPU::cleanUpRemovedInsts()
1600 while (!removeList
.empty()) {
1601 DPRINTF(InOrderCPU
, "Removing instruction, "
1602 "[tid:%i] [sn:%lli] PC %s\n",
1603 (*removeList
.front())->threadNumber
,
1604 (*removeList
.front())->seqNum
,
1605 (*removeList
.front())->pcState());
1607 DynInstPtr inst
= *removeList
.front();
1608 ThreadID tid
= inst
->threadNumber
;
1610 // Remove From Register Dependency Map, If Necessary
1611 // archRegDepMap[tid].remove(inst);
1613 // Clear if Non-Speculative
1614 if (inst
->staticInst
&&
1615 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1616 nonSpecInstActive
[tid
] == true) {
1617 nonSpecInstActive
[tid
] = false;
1620 inst
->onInstList
= false;
1622 instList
[tid
].erase(removeList
.front());
1627 removeInstsThisCycle
= false;
1631 InOrderCPU::cleanUpRemovedEvents()
1633 while (!cpuEventRemoveList
.empty()) {
1634 Event
*cpu_event
= cpuEventRemoveList
.front();
1635 cpuEventRemoveList
.pop();
1642 InOrderCPU::dumpInsts()
1646 ListIt inst_list_it
= instList
[0].begin();
1648 cprintf("Dumping Instruction List\n");
1650 while (inst_list_it
!= instList
[0].end()) {
1651 cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1653 num
, (*inst_list_it
)->pcState(),
1654 (*inst_list_it
)->threadNumber
,
1655 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1656 (*inst_list_it
)->isSquashed());
1663 InOrderCPU::wakeCPU()
1665 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1666 DPRINTF(Activity
, "CPU already running.\n");
1670 DPRINTF(Activity
, "Waking up CPU\n");
1672 Tick extra_cycles
= tickToCycles((curTick() - 1) - lastRunningCycle
);
1674 idleCycles
+= extra_cycles
;
1675 for (int stage_num
= 0; stage_num
< NumStages
; stage_num
++) {
1676 pipelineStage
[stage_num
]->idleCycles
+= extra_cycles
;
1679 numCycles
+= extra_cycles
;
1681 schedule(&tickEvent
, nextCycle(curTick()));
1685 // Lots of copied full system code...place into BaseCPU class?
1687 InOrderCPU::wakeup()
1689 if (thread
[0]->status() != ThreadContext::Suspended
)
1694 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1695 threadContexts
[0]->activate();
1701 InOrderCPU::syscallContext(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
1703 // Syscall must be non-speculative, so squash from last stage
1704 unsigned squash_stage
= NumStages
- 1;
1705 inst
->setSquashInfo(squash_stage
);
1707 // Squash In Pipeline Stage
1708 pipelineStage
[squash_stage
]->setupSquash(inst
, tid
);
1710 // Schedule Squash Through-out Resource Pool
1711 resPool
->scheduleEvent(
1712 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
, inst
, 0);
1713 scheduleCpuEvent(Syscall
, fault
, tid
, inst
, delay
, Syscall_Pri
);
1717 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1719 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1721 DPRINTF(Activity
,"Activity: syscall() called.\n");
1723 // Temporarily increase this by one to account for the syscall
1725 ++(this->thread
[tid
]->funcExeInst
);
1727 // Execute the actual syscall.
1728 this->thread
[tid
]->syscall(callnum
);
1730 // Decrease funcExeInst by one as the normal commit will handle
1732 --(this->thread
[tid
]->funcExeInst
);
1734 // Clear Non-Speculative Block Variable
1735 nonSpecInstActive
[tid
] = false;
1740 InOrderCPU::getITBPtr()
1742 CacheUnit
*itb_res
=
1743 dynamic_cast<CacheUnit
*>(resPool
->getResource(fetchPortIdx
));
1744 return itb_res
->tlb();
1749 InOrderCPU::getDTBPtr()
1751 CacheUnit
*dtb_res
=
1752 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1753 return dtb_res
->tlb();
1757 InOrderCPU::getDecoderPtr()
1759 FetchUnit
*fetch_res
=
1760 dynamic_cast<FetchUnit
*>(resPool
->getResource(fetchPortIdx
));
1761 return &fetch_res
->decoder
;
1765 InOrderCPU::read(DynInstPtr inst
, Addr addr
,
1766 uint8_t *data
, unsigned size
, unsigned flags
)
1768 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1769 // you want to run w/out caches?
1770 CacheUnit
*cache_res
=
1771 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1773 return cache_res
->read(inst
, addr
, data
, size
, flags
);
1777 InOrderCPU::write(DynInstPtr inst
, uint8_t *data
, unsigned size
,
1778 Addr addr
, unsigned flags
, uint64_t *write_res
)
1780 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1781 // you want to run w/out caches?
1782 CacheUnit
*cache_res
=
1783 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1784 return cache_res
->write(inst
, data
, size
, addr
, flags
, write_res
);