2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "arch/utility.hh"
35 #include "base/bigint.hh"
36 #include "config/the_isa.hh"
37 #include "cpu/inorder/resources/resource_list.hh"
38 #include "cpu/inorder/cpu.hh"
39 #include "cpu/inorder/first_stage.hh"
40 #include "cpu/inorder/inorder_dyn_inst.hh"
41 #include "cpu/inorder/pipeline_traits.hh"
42 #include "cpu/inorder/resource_pool.hh"
43 #include "cpu/inorder/thread_context.hh"
44 #include "cpu/inorder/thread_state.hh"
45 #include "cpu/activity.hh"
46 #include "cpu/base.hh"
47 #include "cpu/exetrace.hh"
48 #include "cpu/quiesce_event.hh"
49 #include "cpu/simple_thread.hh"
50 #include "cpu/thread_context.hh"
51 #include "debug/Activity.hh"
52 #include "debug/InOrderCPU.hh"
53 #include "debug/Interrupt.hh"
54 #include "debug/RefCount.hh"
55 #include "debug/SkedCache.hh"
56 #include "debug/Quiesce.hh"
57 #include "mem/translating_port.hh"
58 #include "params/InOrderCPU.hh"
59 #include "sim/full_system.hh"
60 #include "sim/process.hh"
61 #include "sim/stat_control.hh"
62 #include "sim/system.hh"
64 #if THE_ISA == ALPHA_ISA
65 #include "arch/alpha/osfpal.hh"
69 using namespace TheISA
;
70 using namespace ThePipeline
;
72 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
73 : Event(CPU_Tick_Pri
), cpu(c
)
78 InOrderCPU::TickEvent::process()
85 InOrderCPU::TickEvent::description()
87 return "InOrderCPU tick event";
90 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
91 Fault fault
, ThreadID _tid
, DynInstPtr inst
,
92 CPUEventPri event_pri
)
93 : Event(event_pri
), cpu(_cpu
)
95 setEvent(e_type
, fault
, _tid
, inst
);
99 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
102 "ActivateNextReadyThread",
108 "SquashFromMemStall",
113 InOrderCPU::CPUEvent::process()
115 switch (cpuEventType
)
118 cpu
->activateThread(tid
);
119 cpu
->resPool
->activateThread(tid
);
122 case ActivateNextReadyThread
:
123 cpu
->activateNextReadyThread();
126 case DeactivateThread
:
127 cpu
->deactivateThread(tid
);
128 cpu
->resPool
->deactivateThread(tid
);
132 cpu
->haltThread(tid
);
133 cpu
->resPool
->deactivateThread(tid
);
137 cpu
->suspendThread(tid
);
138 cpu
->resPool
->suspendThread(tid
);
141 case SquashFromMemStall
:
142 cpu
->squashDueToMemStall(inst
->squashingStage
, inst
->seqNum
, tid
);
143 cpu
->resPool
->squashDueToMemStall(inst
, inst
->squashingStage
,
148 DPRINTF(InOrderCPU
, "Trapping CPU\n");
149 cpu
->trap(fault
, tid
, inst
);
150 cpu
->resPool
->trap(fault
, tid
, inst
);
151 cpu
->trapPending
[tid
] = false;
155 cpu
->syscall(inst
->syscallNum
, tid
);
156 cpu
->resPool
->trap(fault
, tid
, inst
);
160 fatal("Unrecognized Event Type %s", eventNames
[cpuEventType
]);
163 cpu
->cpuEventRemoveList
.push(this);
169 InOrderCPU::CPUEvent::description()
171 return "InOrderCPU event";
175 InOrderCPU::CPUEvent::scheduleEvent(int delay
)
177 assert(!scheduled() || squashed());
178 cpu
->reschedule(this, cpu
->nextCycle(curTick() + cpu
->ticks(delay
)), true);
182 InOrderCPU::CPUEvent::unscheduleEvent()
188 InOrderCPU::InOrderCPU(Params
*params
)
190 cpu_id(params
->cpu_id
),
194 stageWidth(params
->stageWidth
),
196 removeInstsThisCycle(false),
197 activityRec(params
->name
, NumStages
, 10, params
->activity
),
198 system(params
->system
),
204 deferRegistration(false/*params->deferRegistration*/),
205 stageTracing(params
->stageTracing
),
209 ThreadID active_threads
;
212 resPool
= new ResourcePool(this, params
);
214 // Resize for Multithreading CPUs
215 thread
.resize(numThreads
);
220 active_threads
= params
->workload
.size();
222 if (active_threads
> MaxThreads
) {
223 panic("Workload Size too large. Increase the 'MaxThreads'"
224 "in your InOrder implementation or "
225 "edit your workload size.");
229 if (active_threads
> 1) {
230 threadModel
= (InOrderCPU::ThreadModel
) params
->threadModel
;
232 if (threadModel
== SMT
) {
233 DPRINTF(InOrderCPU
, "Setting Thread Model to SMT.\n");
234 } else if (threadModel
== SwitchOnCacheMiss
) {
235 DPRINTF(InOrderCPU
, "Setting Thread Model to "
236 "Switch On Cache Miss\n");
240 threadModel
= Single
;
244 // Bind the fetch & data ports from the resource pool.
245 fetchPortIdx
= resPool
->getPortIdx(params
->fetchMemPort
);
246 if (fetchPortIdx
== 0) {
247 fatal("Unable to find port to fetch instructions from.\n");
250 dataPortIdx
= resPool
->getPortIdx(params
->dataMemPort
);
251 if (dataPortIdx
== 0) {
252 fatal("Unable to find port for data.\n");
255 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
257 lastCommittedPC
[tid
].set(0);
260 // SMT is not supported in FS mode yet.
261 assert(numThreads
== 1);
262 thread
[tid
] = new Thread(this, 0, NULL
);
264 if (tid
< (ThreadID
)params
->workload
.size()) {
265 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
266 tid
, params
->workload
[tid
]->prog_fname
);
268 new Thread(this, tid
, params
->workload
[tid
]);
270 //Allocate Empty thread so M5 can use later
271 //when scheduling threads to CPU
272 Process
* dummy_proc
= params
->workload
[0];
273 thread
[tid
] = new Thread(this, tid
, dummy_proc
);
276 // Eventually set this with parameters...
280 // Setup the TC that will serve as the interface to the threads/CPU.
281 InOrderThreadContext
*tc
= new InOrderThreadContext
;
283 tc
->thread
= thread
[tid
];
285 // Setup quiesce event.
286 this->thread
[tid
]->quiesceEvent
= new EndQuiesceEvent(tc
);
288 // Give the thread the TC.
289 thread
[tid
]->tc
= tc
;
290 thread
[tid
]->setFuncExeInst(0);
291 globalSeqNum
[tid
] = 1;
293 // Add the TC to the CPU's list of TC's.
294 this->threadContexts
.push_back(tc
);
297 // Initialize TimeBuffer Stage Queues
298 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
299 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
300 stageQueue
[stNum
]->id(stNum
);
304 // Set Up Pipeline Stages
305 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
307 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
309 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
311 pipelineStage
[stNum
]->setCPU(this);
312 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
313 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
315 // Take Care of 1st/Nth stages
317 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
318 if (stNum
< NumStages
- 1)
319 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
322 // Initialize thread specific variables
323 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
324 archRegDepMap
[tid
].setCPU(this);
326 nonSpecInstActive
[tid
] = false;
327 nonSpecSeqNum
[tid
] = 0;
329 squashSeqNum
[tid
] = MaxAddr
;
330 lastSquashCycle
[tid
] = 0;
332 memset(intRegs
[tid
], 0, sizeof(intRegs
[tid
]));
333 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
336 // Define dummy instructions and resource requests to be used.
337 dummyInst
[tid
] = new InOrderDynInst(this,
343 dummyReq
[tid
] = new ResourceRequest(resPool
->getResource(0));
347 // Use this dummy inst to force squashing behind every instruction
349 dummyTrapInst
[tid
] = new InOrderDynInst(this, NULL
, 0, 0, 0);
350 dummyTrapInst
[tid
]->seqNum
= 0;
351 dummyTrapInst
[tid
]->squashSeqNum
= 0;
352 dummyTrapInst
[tid
]->setTid(tid
);
355 trapPending
[tid
] = false;
359 dummyReqInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
360 dummyReqInst
->setSquashed();
361 dummyReqInst
->resetInstCount();
363 dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
364 dummyBufferInst
->setSquashed();
365 dummyBufferInst
->resetInstCount();
367 endOfSkedIt
= skedCache
.end();
368 frontEndSked
= createFrontEndSked();
369 faultSked
= createFaultSked();
371 lastRunningCycle
= curTick();
376 // Schedule First Tick Event, CPU will reschedule itself from here on out.
377 scheduleTickEvent(0);
380 InOrderCPU::~InOrderCPU()
384 SkedCacheIt sked_it
= skedCache
.begin();
385 SkedCacheIt sked_end
= skedCache
.end();
387 while (sked_it
!= sked_end
) {
388 delete (*sked_it
).second
;
394 m5::hash_map
<InOrderCPU::SkedID
, ThePipeline::RSkedPtr
> InOrderCPU::skedCache
;
397 InOrderCPU::createFrontEndSked()
399 RSkedPtr res_sked
= new ResourceSked();
401 StageScheduler
F(res_sked
, stage_num
++);
402 StageScheduler
D(res_sked
, stage_num
++);
405 F
.needs(FetchSeq
, FetchSeqUnit::AssignNextPC
);
406 F
.needs(ICache
, FetchUnit::InitiateFetch
);
409 D
.needs(ICache
, FetchUnit::CompleteFetch
);
410 D
.needs(Decode
, DecodeUnit::DecodeInst
);
411 D
.needs(BPred
, BranchPredictor::PredictBranch
);
412 D
.needs(FetchSeq
, FetchSeqUnit::UpdateTargetPC
);
415 DPRINTF(SkedCache
, "Resource Sked created for instruction Front End\n");
421 InOrderCPU::createFaultSked()
423 RSkedPtr res_sked
= new ResourceSked();
424 StageScheduler
W(res_sked
, NumStages
- 1);
425 W
.needs(Grad
, GraduationUnit::CheckFault
);
426 DPRINTF(SkedCache
, "Resource Sked created for instruction Faults\n");
431 InOrderCPU::createBackEndSked(DynInstPtr inst
)
433 RSkedPtr res_sked
= lookupSked(inst
);
434 if (res_sked
!= NULL
) {
435 DPRINTF(SkedCache
, "Found %s in sked cache.\n",
439 res_sked
= new ResourceSked();
442 int stage_num
= ThePipeline::BackEndStartStage
;
443 StageScheduler
X(res_sked
, stage_num
++);
444 StageScheduler
M(res_sked
, stage_num
++);
445 StageScheduler
W(res_sked
, stage_num
++);
447 if (!inst
->staticInst
) {
448 warn_once("Static Instruction Object Not Set. Can't Create"
449 " Back End Schedule");
454 X
.needs(RegManager
, UseDefUnit::MarkDestRegs
);
455 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
456 if (!idx
|| !inst
->isStore()) {
457 X
.needs(RegManager
, UseDefUnit::ReadSrcReg
, idx
);
461 //@todo: schedule non-spec insts to operate on this cycle
462 // as long as all previous insts are done
463 if ( inst
->isNonSpeculative() ) {
464 // skip execution of non speculative insts until later
465 } else if ( inst
->isMemRef() ) {
466 if ( inst
->isLoad() ) {
467 X
.needs(AGEN
, AGENUnit::GenerateAddr
);
469 } else if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
470 X
.needs(MDU
, MultDivUnit::StartMultDiv
);
472 X
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
476 if (!inst
->isNonSpeculative()) {
477 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
478 M
.needs(MDU
, MultDivUnit::EndMultDiv
);
481 if ( inst
->isLoad() ) {
482 M
.needs(DCache
, CacheUnit::InitiateReadData
);
484 M
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
485 } else if ( inst
->isStore() ) {
486 for (int i
= 1; i
< inst
->numSrcRegs(); i
++ ) {
487 M
.needs(RegManager
, UseDefUnit::ReadSrcReg
, i
);
489 M
.needs(AGEN
, AGENUnit::GenerateAddr
);
490 M
.needs(DCache
, CacheUnit::InitiateWriteData
);
492 M
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
497 if (!inst
->isNonSpeculative()) {
498 if ( inst
->isLoad() ) {
499 W
.needs(DCache
, CacheUnit::CompleteReadData
);
501 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
502 } else if ( inst
->isStore() ) {
503 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
505 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
508 // Finally, Execute Speculative Data
509 if (inst
->isMemRef()) {
510 if (inst
->isLoad()) {
511 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
512 W
.needs(DCache
, CacheUnit::InitiateReadData
);
514 W
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
515 W
.needs(DCache
, CacheUnit::CompleteReadData
);
517 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
518 } else if (inst
->isStore()) {
519 if ( inst
->numSrcRegs() >= 2 ) {
520 W
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
522 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
523 W
.needs(DCache
, CacheUnit::InitiateWriteData
);
525 W
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
526 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
528 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
531 W
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
535 W
.needs(Grad
, GraduationUnit::CheckFault
);
537 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
538 W
.needs(RegManager
, UseDefUnit::WriteDestReg
, idx
);
541 if (inst
->isControl())
542 W
.needs(BPred
, BranchPredictor::UpdatePredictor
);
544 W
.needs(Grad
, GraduationUnit::GraduateInst
);
546 // Insert Back Schedule into our cache of
547 // resource schedules
548 addToSkedCache(inst
, res_sked
);
550 DPRINTF(SkedCache
, "Back End Sked Created for instruction: %s (%08p)\n",
551 inst
->instName(), inst
->getMachInst());
558 InOrderCPU::regStats()
560 /* Register the Resource Pool's stats here.*/
563 /* Register for each Pipeline Stage */
564 for (int stage_num
=0; stage_num
< ThePipeline::NumStages
; stage_num
++) {
565 pipelineStage
[stage_num
]->regStats();
568 /* Register any of the InOrderCPU's stats here.*/
570 .name(name() + ".instsPerContextSwitch")
571 .desc("Instructions Committed Per Context Switch")
572 .prereq(instsPerCtxtSwitch
);
575 .name(name() + ".contextSwitches")
576 .desc("Number of context switches");
579 .name(name() + ".comLoads")
580 .desc("Number of Load instructions committed");
583 .name(name() + ".comStores")
584 .desc("Number of Store instructions committed");
587 .name(name() + ".comBranches")
588 .desc("Number of Branches instructions committed");
591 .name(name() + ".comNops")
592 .desc("Number of Nop instructions committed");
595 .name(name() + ".comNonSpec")
596 .desc("Number of Non-Speculative instructions committed");
599 .name(name() + ".comInts")
600 .desc("Number of Integer instructions committed");
603 .name(name() + ".comFloats")
604 .desc("Number of Floating Point instructions committed");
607 .name(name() + ".timesIdled")
608 .desc("Number of times that the entire CPU went into an idle state and"
609 " unscheduled itself")
613 .name(name() + ".idleCycles")
614 .desc("Number of cycles cpu's stages were not processed");
617 .name(name() + ".runCycles")
618 .desc("Number of cycles cpu stages are processed.");
621 .name(name() + ".activity")
622 .desc("Percentage of cycles cpu is active")
624 activity
= (runCycles
/ numCycles
) * 100;
628 .name(name() + ".threadCycles")
629 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
632 .name(name() + ".smtCycles")
633 .desc("Total number of cycles that the CPU was in SMT-mode");
637 .name(name() + ".committedInsts")
638 .desc("Number of Instructions Simulated (Per-Thread)");
642 .name(name() + ".smtCommittedInsts")
643 .desc("Number of SMT Instructions Simulated (Per-Thread)");
646 .name(name() + ".committedInsts_total")
647 .desc("Number of Instructions Simulated (Total)");
650 .name(name() + ".cpi")
651 .desc("CPI: Cycles Per Instruction (Per-Thread)")
653 cpi
= numCycles
/ committedInsts
;
656 .name(name() + ".smt_cpi")
657 .desc("CPI: Total SMT-CPI")
659 smtCpi
= smtCycles
/ smtCommittedInsts
;
662 .name(name() + ".cpi_total")
663 .desc("CPI: Total CPI of All Threads")
665 totalCpi
= numCycles
/ totalCommittedInsts
;
668 .name(name() + ".ipc")
669 .desc("IPC: Instructions Per Cycle (Per-Thread)")
671 ipc
= committedInsts
/ numCycles
;
674 .name(name() + ".smt_ipc")
675 .desc("IPC: Total SMT-IPC")
677 smtIpc
= smtCommittedInsts
/ smtCycles
;
680 .name(name() + ".ipc_total")
681 .desc("IPC: Total IPC of All Threads")
683 totalIpc
= totalCommittedInsts
/ numCycles
;
692 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
696 checkForInterrupts();
698 bool pipes_idle
= true;
699 //Tick each of the stages
700 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
701 pipelineStage
[stNum
]->tick();
703 pipes_idle
= pipes_idle
&& pipelineStage
[stNum
]->idle
;
711 // Now advance the time buffers one tick
712 timeBuffer
.advance();
713 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
714 stageQueue
[sqNum
]->advance();
716 activityRec
.advance();
718 // Any squashed events, or insts then remove them now
719 cleanUpRemovedEvents();
720 cleanUpRemovedInsts();
722 // Re-schedule CPU for this cycle
723 if (!tickEvent
.scheduled()) {
724 if (_status
== SwitchedOut
) {
726 lastRunningCycle
= curTick();
727 } else if (!activityRec
.active()) {
728 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
729 lastRunningCycle
= curTick();
732 //Tick next_tick = curTick() + cycles(1);
733 //tickEvent.schedule(next_tick);
734 schedule(&tickEvent
, nextCycle(curTick() + 1));
735 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n",
736 nextCycle(curTick() + 1));
741 updateThreadPriority();
748 if (!deferRegistration
) {
749 registerThreadContexts();
752 // Set inSyscall so that the CPU doesn't squash when initially
753 // setting up registers.
754 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
755 thread
[tid
]->inSyscall
= true;
758 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
759 ThreadContext
*src_tc
= threadContexts
[tid
];
760 TheISA::initCPU(src_tc
, src_tc
->contextId());
765 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
766 thread
[tid
]->inSyscall
= false;
768 // Call Initializiation Routine for Resource Pool
773 InOrderCPU::getPort(const std::string
&if_name
, int idx
)
775 return resPool
->getPort(if_name
, idx
);
779 InOrderCPU::hwrei(ThreadID tid
)
781 #if THE_ISA == ALPHA_ISA
782 // Need to clear the lock flag upon returning from an interrupt.
783 setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG
, false, tid
);
785 thread
[tid
]->kernelStats
->hwrei();
786 // FIXME: XXX check for interrupts? XXX
794 InOrderCPU::simPalCheck(int palFunc
, ThreadID tid
)
796 #if THE_ISA == ALPHA_ISA
797 if (this->thread
[tid
]->kernelStats
)
798 this->thread
[tid
]->kernelStats
->callpal(palFunc
,
799 this->threadContexts
[tid
]);
804 if (--System::numSystemsRunning
== 0)
805 exitSimLoop("all cpus halted");
810 if (this->system
->breakpoint())
819 InOrderCPU::checkForInterrupts()
821 for (int i
= 0; i
< threadContexts
.size(); i
++) {
822 ThreadContext
*tc
= threadContexts
[i
];
824 if (interrupts
->checkInterrupts(tc
)) {
825 Fault interrupt
= interrupts
->getInterrupt(tc
);
827 if (interrupt
!= NoFault
) {
828 DPRINTF(Interrupt
, "Processing Intterupt for [tid:%i].\n",
831 ThreadID tid
= tc
->threadId();
832 interrupts
->updateIntrInfo(tc
);
834 // Squash from Last Stage in Pipeline
835 unsigned last_stage
= NumStages
- 1;
836 dummyTrapInst
[tid
]->squashingStage
= last_stage
;
837 pipelineStage
[last_stage
]->setupSquash(dummyTrapInst
[tid
],
840 // By default, setupSquash will always squash from stage + 1
841 pipelineStage
[BackEndStartStage
- 1]->setupSquash(dummyTrapInst
[tid
],
844 // Schedule Squash Through-out Resource Pool
845 resPool
->scheduleEvent(
846 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
,
847 dummyTrapInst
[tid
], 0);
849 // Finally, Setup Trap to happen at end of cycle
850 trapContext(interrupt
, tid
, dummyTrapInst
[tid
]);
857 InOrderCPU::getInterrupts()
859 // Check if there are any outstanding interrupts
860 return interrupts
->getInterrupt(threadContexts
[0]);
865 InOrderCPU::processInterrupts(Fault interrupt
)
867 // Check for interrupts here. For now can copy the code that
868 // exists within isa_fullsys_traits.hh. Also assume that thread 0
869 // is the one that handles the interrupts.
870 // @todo: Possibly consolidate the interrupt checking code.
871 // @todo: Allow other threads to handle interrupts.
873 assert(interrupt
!= NoFault
);
874 interrupts
->updateIntrInfo(threadContexts
[0]);
876 DPRINTF(InOrderCPU
, "Interrupt %s being handled\n", interrupt
->name());
878 // Note: Context ID ok here? Impl. of FS mode needs to revisit this
879 trap(interrupt
, threadContexts
[0]->contextId(), dummyBufferInst
);
883 InOrderCPU::updateMemPorts()
885 // Update all ThreadContext's memory ports (Functional/Virtual
887 ThreadID size
= thread
.size();
888 for (ThreadID i
= 0; i
< size
; ++i
)
889 thread
[i
]->connectMemPorts(thread
[i
]->getTC());
893 InOrderCPU::trapContext(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
895 scheduleCpuEvent(Trap
, fault
, tid
, inst
, delay
);
896 trapPending
[tid
] = true;
900 InOrderCPU::trap(Fault fault
, ThreadID tid
, DynInstPtr inst
)
902 fault
->invoke(tcBase(tid
), inst
->staticInst
);
903 removePipelineStalls(tid
);
907 InOrderCPU::squashFromMemStall(DynInstPtr inst
, ThreadID tid
, int delay
)
909 scheduleCpuEvent(SquashFromMemStall
, NoFault
, tid
, inst
, delay
);
914 InOrderCPU::squashDueToMemStall(int stage_num
, InstSeqNum seq_num
,
917 DPRINTF(InOrderCPU
, "Squashing Pipeline Stages Due to Memory Stall...\n");
919 // Squash all instructions in each stage including
920 // instruction that caused the squash (seq_num - 1)
921 // NOTE: The stage bandwidth needs to be cleared so thats why
922 // the stalling instruction is squashed as well. The stalled
923 // instruction is previously placed in another intermediate buffer
924 // while it's stall is being handled.
925 InstSeqNum squash_seq_num
= seq_num
- 1;
927 for (int stNum
=stage_num
; stNum
>= 0 ; stNum
--) {
928 pipelineStage
[stNum
]->squashDueToMemStall(squash_seq_num
, tid
);
933 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
934 ThreadID tid
, DynInstPtr inst
,
935 unsigned delay
, CPUEventPri event_pri
)
937 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, inst
,
940 Tick sked_tick
= nextCycle(curTick() + ticks(delay
));
942 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
943 eventNames
[c_event
], curTick() + delay
, tid
);
944 schedule(cpu_event
, sked_tick
);
946 cpu_event
->process();
947 cpuEventRemoveList
.push(cpu_event
);
950 // Broadcast event to the Resource Pool
951 // Need to reset tid just in case this is a dummy instruction
953 resPool
->scheduleEvent(c_event
, inst
, 0, 0, tid
);
957 InOrderCPU::isThreadActive(ThreadID tid
)
959 list
<ThreadID
>::iterator isActive
=
960 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
962 return (isActive
!= activeThreads
.end());
966 InOrderCPU::isThreadReady(ThreadID tid
)
968 list
<ThreadID
>::iterator isReady
=
969 std::find(readyThreads
.begin(), readyThreads
.end(), tid
);
971 return (isReady
!= readyThreads
.end());
975 InOrderCPU::isThreadSuspended(ThreadID tid
)
977 list
<ThreadID
>::iterator isSuspended
=
978 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
980 return (isSuspended
!= suspendedThreads
.end());
984 InOrderCPU::activateNextReadyThread()
986 if (readyThreads
.size() >= 1) {
987 ThreadID ready_tid
= readyThreads
.front();
989 // Activate in Pipeline
990 activateThread(ready_tid
);
992 // Activate in Resource Pool
993 resPool
->activateThread(ready_tid
);
995 list
<ThreadID
>::iterator ready_it
=
996 std::find(readyThreads
.begin(), readyThreads
.end(), ready_tid
);
997 readyThreads
.erase(ready_it
);
1000 "Attempting to activate new thread, but No Ready Threads to"
1003 "Unable to switch to next active thread.\n");
1008 InOrderCPU::activateThread(ThreadID tid
)
1010 if (isThreadSuspended(tid
)) {
1012 "Removing [tid:%i] from suspended threads list.\n", tid
);
1014 list
<ThreadID
>::iterator susp_it
=
1015 std::find(suspendedThreads
.begin(), suspendedThreads
.end(),
1017 suspendedThreads
.erase(susp_it
);
1020 if (threadModel
== SwitchOnCacheMiss
&&
1021 numActiveThreads() == 1) {
1023 "Ignoring activation of [tid:%i], since [tid:%i] is "
1024 "already running.\n", tid
, activeThreadId());
1026 DPRINTF(InOrderCPU
,"Placing [tid:%i] on ready threads list\n",
1029 readyThreads
.push_back(tid
);
1031 } else if (!isThreadActive(tid
)) {
1033 "Adding [tid:%i] to active threads list.\n", tid
);
1034 activeThreads
.push_back(tid
);
1036 activateThreadInPipeline(tid
);
1038 thread
[tid
]->lastActivate
= curTick();
1040 tcBase(tid
)->setStatus(ThreadContext::Active
);
1049 InOrderCPU::activateThreadInPipeline(ThreadID tid
)
1051 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
1052 pipelineStage
[stNum
]->activateThread(tid
);
1057 InOrderCPU::deactivateContext(ThreadID tid
, int delay
)
1059 DPRINTF(InOrderCPU
,"[tid:%i]: Deactivating ...\n", tid
);
1061 scheduleCpuEvent(DeactivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1063 // Be sure to signal that there's some activity so the CPU doesn't
1064 // deschedule itself.
1065 activityRec
.activity();
1071 InOrderCPU::deactivateThread(ThreadID tid
)
1073 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
1075 if (isThreadActive(tid
)) {
1076 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
1078 list
<ThreadID
>::iterator thread_it
=
1079 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
1081 removePipelineStalls(*thread_it
);
1083 activeThreads
.erase(thread_it
);
1085 // Ideally, this should be triggered from the
1086 // suspendContext/Thread functions
1087 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1090 assert(!isThreadActive(tid
));
1094 InOrderCPU::removePipelineStalls(ThreadID tid
)
1096 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
1099 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
1100 pipelineStage
[stNum
]->removeStalls(tid
);
1106 InOrderCPU::updateThreadPriority()
1108 if (activeThreads
.size() > 1)
1110 //DEFAULT TO ROUND ROBIN SCHEME
1111 //e.g. Move highest priority to end of thread list
1112 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
1113 list
<ThreadID
>::iterator list_end
= activeThreads
.end();
1115 unsigned high_thread
= *list_begin
;
1117 activeThreads
.erase(list_begin
);
1119 activeThreads
.push_back(high_thread
);
1124 InOrderCPU::tickThreadStats()
1126 /** Keep track of cycles that each thread is active */
1127 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
1128 while (thread_it
!= activeThreads
.end()) {
1129 threadCycles
[*thread_it
]++;
1133 // Keep track of cycles where SMT is active
1134 if (activeThreads
.size() > 1) {
1140 InOrderCPU::activateContext(ThreadID tid
, int delay
)
1142 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
1145 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1147 // Be sure to signal that there's some activity so the CPU doesn't
1148 // deschedule itself.
1149 activityRec
.activity();
1155 InOrderCPU::activateNextReadyContext(int delay
)
1157 DPRINTF(InOrderCPU
,"Activating next ready thread\n");
1159 scheduleCpuEvent(ActivateNextReadyThread
, NoFault
, 0/*tid*/, dummyInst
[0],
1160 delay
, ActivateNextReadyThread_Pri
);
1162 // Be sure to signal that there's some activity so the CPU doesn't
1163 // deschedule itself.
1164 activityRec
.activity();
1170 InOrderCPU::haltContext(ThreadID tid
, int delay
)
1172 DPRINTF(InOrderCPU
, "[tid:%i]: Calling Halt Context...\n", tid
);
1174 scheduleCpuEvent(HaltThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1176 activityRec
.activity();
1180 InOrderCPU::haltThread(ThreadID tid
)
1182 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Halted Threads List...\n", tid
);
1183 deactivateThread(tid
);
1184 squashThreadInPipeline(tid
);
1185 haltedThreads
.push_back(tid
);
1187 tcBase(tid
)->setStatus(ThreadContext::Halted
);
1189 if (threadModel
== SwitchOnCacheMiss
) {
1190 activateNextReadyContext();
1195 InOrderCPU::suspendContext(ThreadID tid
, int delay
)
1197 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1201 InOrderCPU::suspendThread(ThreadID tid
)
1203 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Suspended Threads List...\n",
1205 deactivateThread(tid
);
1206 suspendedThreads
.push_back(tid
);
1207 thread
[tid
]->lastSuspend
= curTick();
1209 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1213 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
1215 //Squash all instructions in each stage
1216 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
1217 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
1222 InOrderCPU::getPipeStage(int stage_num
)
1224 return pipelineStage
[stage_num
];
1229 InOrderCPU::flattenRegIdx(RegIndex reg_idx
, RegType
®_type
, ThreadID tid
)
1231 if (reg_idx
< FP_Base_DepTag
) {
1233 return isa
[tid
].flattenIntIndex(reg_idx
);
1234 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1235 reg_type
= FloatType
;
1236 reg_idx
-= FP_Base_DepTag
;
1237 return isa
[tid
].flattenFloatIndex(reg_idx
);
1239 reg_type
= MiscType
;
1240 return reg_idx
- TheISA::Ctrl_Base_DepTag
;
1245 InOrderCPU::readIntReg(RegIndex reg_idx
, ThreadID tid
)
1247 DPRINTF(IntRegs
, "[tid:%i]: Reading Int. Reg %i as %x\n",
1248 tid
, reg_idx
, intRegs
[tid
][reg_idx
]);
1250 return intRegs
[tid
][reg_idx
];
1254 InOrderCPU::readFloatReg(RegIndex reg_idx
, ThreadID tid
)
1256 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1257 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1259 return floatRegs
.f
[tid
][reg_idx
];
1263 InOrderCPU::readFloatRegBits(RegIndex reg_idx
, ThreadID tid
)
1265 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1266 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1268 return floatRegs
.i
[tid
][reg_idx
];
1272 InOrderCPU::setIntReg(RegIndex reg_idx
, uint64_t val
, ThreadID tid
)
1274 if (reg_idx
== TheISA::ZeroReg
) {
1275 DPRINTF(IntRegs
, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1276 "(Int. Reg %i) to %x\n", tid
, reg_idx
, val
);
1279 DPRINTF(IntRegs
, "[tid:%i]: Setting Int. Reg %i to %x\n",
1282 intRegs
[tid
][reg_idx
] = val
;
1288 InOrderCPU::setFloatReg(RegIndex reg_idx
, FloatReg val
, ThreadID tid
)
1290 floatRegs
.f
[tid
][reg_idx
] = val
;
1291 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1294 floatRegs
.i
[tid
][reg_idx
],
1295 floatRegs
.f
[tid
][reg_idx
]);
1300 InOrderCPU::setFloatRegBits(RegIndex reg_idx
, FloatRegBits val
, ThreadID tid
)
1302 floatRegs
.i
[tid
][reg_idx
] = val
;
1303 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1306 floatRegs
.i
[tid
][reg_idx
],
1307 floatRegs
.f
[tid
][reg_idx
]);
1311 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
1313 // If Default value is set, then retrieve target thread
1314 if (tid
== InvalidThreadID
) {
1315 tid
= TheISA::getTargetThread(tcBase(tid
));
1318 if (reg_idx
< FP_Base_DepTag
) {
1319 // Integer Register File
1320 return readIntReg(reg_idx
, tid
);
1321 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1322 // Float Register File
1323 reg_idx
-= FP_Base_DepTag
;
1324 return readFloatRegBits(reg_idx
, tid
);
1326 reg_idx
-= Ctrl_Base_DepTag
;
1327 return readMiscReg(reg_idx
, tid
); // Misc. Register File
1331 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
1334 // If Default value is set, then retrieve target thread
1335 if (tid
== InvalidThreadID
) {
1336 tid
= TheISA::getTargetThread(tcBase(tid
));
1339 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
1340 setIntReg(reg_idx
, val
, tid
);
1341 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
1342 reg_idx
-= FP_Base_DepTag
;
1343 setFloatRegBits(reg_idx
, val
, tid
);
1345 reg_idx
-= Ctrl_Base_DepTag
;
1346 setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
1351 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1353 return isa
[tid
].readMiscRegNoEffect(misc_reg
);
1357 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
1359 return isa
[tid
].readMiscReg(misc_reg
, tcBase(tid
));
1363 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1365 isa
[tid
].setMiscRegNoEffect(misc_reg
, val
);
1369 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1371 isa
[tid
].setMiscReg(misc_reg
, val
, tcBase(tid
));
1376 InOrderCPU::addInst(DynInstPtr inst
)
1378 ThreadID tid
= inst
->readTid();
1380 instList
[tid
].push_back(inst
);
1382 return --(instList
[tid
].end());
1386 InOrderCPU::findInst(InstSeqNum seq_num
, ThreadID tid
)
1388 ListIt it
= instList
[tid
].begin();
1389 ListIt end
= instList
[tid
].end();
1392 if ((*it
)->seqNum
== seq_num
)
1394 else if ((*it
)->seqNum
> seq_num
)
1400 return instList
[tid
].end();
1404 InOrderCPU::updateContextSwitchStats()
1406 // Set Average Stat Here, then reset to 0
1407 instsPerCtxtSwitch
= instsPerSwitch
;
1413 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1415 // Set the nextPC to be fetched if this is the last instruction
1418 // This contributes to the precise state of the CPU
1419 // which can be used when restoring a thread to the CPU after after any
1420 // type of context switching activity (fork, exception, etc.)
1421 TheISA::PCState comm_pc
= inst
->pcState();
1422 lastCommittedPC
[tid
] = comm_pc
;
1423 TheISA::advancePC(comm_pc
, inst
->staticInst
);
1424 pcState(comm_pc
, tid
);
1426 //@todo: may be unnecessary with new-ISA-specific branch handling code
1427 if (inst
->isControl()) {
1428 thread
[tid
]->lastGradIsBranch
= true;
1429 thread
[tid
]->lastBranchPC
= inst
->pcState();
1430 TheISA::advancePC(thread
[tid
]->lastBranchPC
, inst
->staticInst
);
1432 thread
[tid
]->lastGradIsBranch
= false;
1436 // Finalize Trace Data For Instruction
1437 if (inst
->traceData
) {
1438 //inst->traceData->setCycle(curTick());
1439 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1440 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1441 inst
->traceData
->dump();
1442 delete inst
->traceData
;
1443 inst
->traceData
= NULL
;
1446 // Increment active thread's instruction count
1449 // Increment thread-state's instruction count
1450 thread
[tid
]->numInst
++;
1452 // Increment thread-state's instruction stats
1453 thread
[tid
]->numInsts
++;
1455 // Count committed insts per thread stats
1456 committedInsts
[tid
]++;
1458 // Count total insts committed stat
1459 totalCommittedInsts
++;
1461 // Count SMT-committed insts per thread stat
1462 if (numActiveThreads() > 1) {
1463 smtCommittedInsts
[tid
]++;
1466 // Instruction-Mix Stats
1467 if (inst
->isLoad()) {
1469 } else if (inst
->isStore()) {
1471 } else if (inst
->isControl()) {
1473 } else if (inst
->isNop()) {
1475 } else if (inst
->isNonSpeculative()) {
1477 } else if (inst
->isInteger()) {
1479 } else if (inst
->isFloating()) {
1483 // Check for instruction-count-based events.
1484 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numInst
);
1486 // Finally, remove instruction from CPU
1490 // currently unused function, but substitute repetitive code w/this function
1493 InOrderCPU::addToRemoveList(DynInstPtr inst
)
1495 removeInstsThisCycle
= true;
1496 if (!inst
->isRemoveList()) {
1497 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1498 "[sn:%lli] to remove list\n",
1499 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1500 inst
->setRemoveList();
1501 removeList
.push(inst
->getInstListIt());
1503 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1504 "[sn:%lli], already remove list\n",
1505 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1511 InOrderCPU::removeInst(DynInstPtr inst
)
1513 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %s "
1515 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1517 removeInstsThisCycle
= true;
1519 // Remove the instruction.
1520 if (!inst
->isRemoveList()) {
1521 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1522 "[sn:%lli] to remove list\n",
1523 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1524 inst
->setRemoveList();
1525 removeList
.push(inst
->getInstListIt());
1527 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1528 "[sn:%lli], already on remove list\n",
1529 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1535 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1537 //assert(!instList[tid].empty());
1539 removeInstsThisCycle
= true;
1541 ListIt inst_iter
= instList
[tid
].end();
1545 DPRINTF(InOrderCPU
, "Squashing instructions from CPU instruction "
1546 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1547 tid
, seq_num
, (*inst_iter
)->seqNum
);
1549 while ((*inst_iter
)->seqNum
> seq_num
) {
1551 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1553 squashInstIt(inst_iter
, tid
);
1564 InOrderCPU::squashInstIt(const ListIt inst_it
, ThreadID tid
)
1566 DynInstPtr inst
= (*inst_it
);
1567 if (inst
->threadNumber
== tid
) {
1568 DPRINTF(InOrderCPU
, "Squashing instruction, "
1569 "[tid:%i] [sn:%lli] PC %s\n",
1574 inst
->setSquashed();
1575 archRegDepMap
[tid
].remove(inst
);
1577 if (!inst
->isRemoveList()) {
1578 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1579 "[sn:%lli] to remove list\n",
1580 inst
->threadNumber
, inst
->pcState(),
1582 inst
->setRemoveList();
1583 removeList
.push(inst_it
);
1585 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i]"
1586 " PC %s [sn:%lli], already on remove list\n",
1587 inst
->threadNumber
, inst
->pcState(),
1597 InOrderCPU::cleanUpRemovedInsts()
1599 while (!removeList
.empty()) {
1600 DPRINTF(InOrderCPU
, "Removing instruction, "
1601 "[tid:%i] [sn:%lli] PC %s\n",
1602 (*removeList
.front())->threadNumber
,
1603 (*removeList
.front())->seqNum
,
1604 (*removeList
.front())->pcState());
1606 DynInstPtr inst
= *removeList
.front();
1607 ThreadID tid
= inst
->threadNumber
;
1609 // Remove From Register Dependency Map, If Necessary
1610 // archRegDepMap[tid].remove(inst);
1612 // Clear if Non-Speculative
1613 if (inst
->staticInst
&&
1614 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1615 nonSpecInstActive
[tid
] == true) {
1616 nonSpecInstActive
[tid
] = false;
1619 inst
->onInstList
= false;
1621 instList
[tid
].erase(removeList
.front());
1626 removeInstsThisCycle
= false;
1630 InOrderCPU::cleanUpRemovedEvents()
1632 while (!cpuEventRemoveList
.empty()) {
1633 Event
*cpu_event
= cpuEventRemoveList
.front();
1634 cpuEventRemoveList
.pop();
1641 InOrderCPU::dumpInsts()
1645 ListIt inst_list_it
= instList
[0].begin();
1647 cprintf("Dumping Instruction List\n");
1649 while (inst_list_it
!= instList
[0].end()) {
1650 cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1652 num
, (*inst_list_it
)->pcState(),
1653 (*inst_list_it
)->threadNumber
,
1654 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1655 (*inst_list_it
)->isSquashed());
1662 InOrderCPU::wakeCPU()
1664 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1665 DPRINTF(Activity
, "CPU already running.\n");
1669 DPRINTF(Activity
, "Waking up CPU\n");
1671 Tick extra_cycles
= tickToCycles((curTick() - 1) - lastRunningCycle
);
1673 idleCycles
+= extra_cycles
;
1674 for (int stage_num
= 0; stage_num
< NumStages
; stage_num
++) {
1675 pipelineStage
[stage_num
]->idleCycles
+= extra_cycles
;
1678 numCycles
+= extra_cycles
;
1680 schedule(&tickEvent
, nextCycle(curTick()));
1683 // Lots of copied full system code...place into BaseCPU class?
1685 InOrderCPU::wakeup()
1687 if (thread
[0]->status() != ThreadContext::Suspended
)
1692 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1693 threadContexts
[0]->activate();
1697 InOrderCPU::syscallContext(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
1699 // Syscall must be non-speculative, so squash from last stage
1700 unsigned squash_stage
= NumStages
- 1;
1701 inst
->setSquashInfo(squash_stage
);
1703 // Squash In Pipeline Stage
1704 pipelineStage
[squash_stage
]->setupSquash(inst
, tid
);
1706 // Schedule Squash Through-out Resource Pool
1707 resPool
->scheduleEvent(
1708 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
, inst
, 0);
1709 scheduleCpuEvent(Syscall
, fault
, tid
, inst
, delay
, Syscall_Pri
);
1713 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1715 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1717 DPRINTF(Activity
,"Activity: syscall() called.\n");
1719 // Temporarily increase this by one to account for the syscall
1721 ++(this->thread
[tid
]->funcExeInst
);
1723 // Execute the actual syscall.
1724 this->thread
[tid
]->syscall(callnum
);
1726 // Decrease funcExeInst by one as the normal commit will handle
1728 --(this->thread
[tid
]->funcExeInst
);
1730 // Clear Non-Speculative Block Variable
1731 nonSpecInstActive
[tid
] = false;
1735 InOrderCPU::getITBPtr()
1737 CacheUnit
*itb_res
=
1738 dynamic_cast<CacheUnit
*>(resPool
->getResource(fetchPortIdx
));
1739 return itb_res
->tlb();
1744 InOrderCPU::getDTBPtr()
1746 CacheUnit
*dtb_res
=
1747 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1748 return dtb_res
->tlb();
1752 InOrderCPU::getDecoderPtr()
1754 FetchUnit
*fetch_res
=
1755 dynamic_cast<FetchUnit
*>(resPool
->getResource(fetchPortIdx
));
1756 return &fetch_res
->decoder
;
1760 InOrderCPU::read(DynInstPtr inst
, Addr addr
,
1761 uint8_t *data
, unsigned size
, unsigned flags
)
1763 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1764 // you want to run w/out caches?
1765 CacheUnit
*cache_res
=
1766 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1768 return cache_res
->read(inst
, addr
, data
, size
, flags
);
1772 InOrderCPU::write(DynInstPtr inst
, uint8_t *data
, unsigned size
,
1773 Addr addr
, unsigned flags
, uint64_t *write_res
)
1775 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1776 // you want to run w/out caches?
1777 CacheUnit
*cache_res
=
1778 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1779 return cache_res
->write(inst
, data
, size
, addr
, flags
, write_res
);