2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "arch/utility.hh"
35 #include "base/bigint.hh"
36 #include "config/full_system.hh"
37 #include "config/the_isa.hh"
38 #include "cpu/inorder/resources/resource_list.hh"
39 #include "cpu/inorder/cpu.hh"
40 #include "cpu/inorder/first_stage.hh"
41 #include "cpu/inorder/inorder_dyn_inst.hh"
42 #include "cpu/inorder/pipeline_traits.hh"
43 #include "cpu/inorder/resource_pool.hh"
44 #include "cpu/inorder/thread_context.hh"
45 #include "cpu/inorder/thread_state.hh"
46 #include "cpu/activity.hh"
47 #include "cpu/base.hh"
48 #include "cpu/exetrace.hh"
49 #include "cpu/simple_thread.hh"
50 #include "cpu/thread_context.hh"
51 #include "debug/Activity.hh"
52 #include "debug/InOrderCPU.hh"
53 #include "debug/RefCount.hh"
54 #include "debug/SkedCache.hh"
55 #include "mem/translating_port.hh"
56 #include "params/InOrderCPU.hh"
57 #include "sim/process.hh"
58 #include "sim/stat_control.hh"
61 #include "cpu/quiesce_event.hh"
62 #include "sim/system.hh"
65 #if THE_ISA == ALPHA_ISA
66 #include "arch/alpha/osfpal.hh"
70 using namespace TheISA
;
71 using namespace ThePipeline
;
73 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
74 : Event(CPU_Tick_Pri
), cpu(c
)
79 InOrderCPU::TickEvent::process()
86 InOrderCPU::TickEvent::description()
88 return "InOrderCPU tick event";
91 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
92 Fault fault
, ThreadID _tid
, DynInstPtr inst
,
93 unsigned event_pri_offset
)
94 : Event(Event::Priority((unsigned int)CPU_Tick_Pri
+ event_pri_offset
)),
97 setEvent(e_type
, fault
, _tid
, inst
);
101 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
104 "ActivateNextReadyThread",
110 "SquashFromMemStall",
115 InOrderCPU::CPUEvent::process()
117 switch (cpuEventType
)
120 cpu
->activateThread(tid
);
123 case ActivateNextReadyThread
:
124 cpu
->activateNextReadyThread();
127 case DeactivateThread
:
128 cpu
->deactivateThread(tid
);
132 cpu
->haltThread(tid
);
136 cpu
->suspendThread(tid
);
139 case SquashFromMemStall
:
140 cpu
->squashDueToMemStall(inst
->squashingStage
, inst
->seqNum
, tid
);
144 DPRINTF(InOrderCPU
, "Trapping CPU\n");
145 cpu
->trap(fault
, tid
, inst
);
146 cpu
->resPool
->trap(fault
, tid
, inst
);
150 fatal("Unrecognized Event Type %s", eventNames
[cpuEventType
]);
153 cpu
->cpuEventRemoveList
.push(this);
159 InOrderCPU::CPUEvent::description()
161 return "InOrderCPU event";
165 InOrderCPU::CPUEvent::scheduleEvent(int delay
)
167 assert(!scheduled() || squashed());
168 cpu
->reschedule(this, cpu
->nextCycle(curTick() + cpu
->ticks(delay
)), true);
172 InOrderCPU::CPUEvent::unscheduleEvent()
178 InOrderCPU::InOrderCPU(Params
*params
)
180 cpu_id(params
->cpu_id
),
184 stageWidth(params
->stageWidth
),
186 removeInstsThisCycle(false),
187 activityRec(params
->name
, NumStages
, 10, params
->activity
),
189 system(params
->system
),
190 physmem(system
->physmem
),
191 #endif // FULL_SYSTEM
197 deferRegistration(false/*params->deferRegistration*/),
198 stageTracing(params
->stageTracing
),
201 ThreadID active_threads
;
204 resPool
= new ResourcePool(this, params
);
206 // Resize for Multithreading CPUs
207 thread
.resize(numThreads
);
212 active_threads
= params
->workload
.size();
214 if (active_threads
> MaxThreads
) {
215 panic("Workload Size too large. Increase the 'MaxThreads'"
216 "in your InOrder implementation or "
217 "edit your workload size.");
221 if (active_threads
> 1) {
222 threadModel
= (InOrderCPU::ThreadModel
) params
->threadModel
;
224 if (threadModel
== SMT
) {
225 DPRINTF(InOrderCPU
, "Setting Thread Model to SMT.\n");
226 } else if (threadModel
== SwitchOnCacheMiss
) {
227 DPRINTF(InOrderCPU
, "Setting Thread Model to "
228 "Switch On Cache Miss\n");
232 threadModel
= Single
;
239 // Bind the fetch & data ports from the resource pool.
240 fetchPortIdx
= resPool
->getPortIdx(params
->fetchMemPort
);
241 if (fetchPortIdx
== 0) {
242 fatal("Unable to find port to fetch instructions from.\n");
245 dataPortIdx
= resPool
->getPortIdx(params
->dataMemPort
);
246 if (dataPortIdx
== 0) {
247 fatal("Unable to find port for data.\n");
250 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
252 // SMT is not supported in FS mode yet.
253 assert(numThreads
== 1);
254 thread
[tid
] = new Thread(this, 0);
256 if (tid
< (ThreadID
)params
->workload
.size()) {
257 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
258 tid
, params
->workload
[tid
]->prog_fname
);
260 new Thread(this, tid
, params
->workload
[tid
]);
262 //Allocate Empty thread so M5 can use later
263 //when scheduling threads to CPU
264 Process
* dummy_proc
= params
->workload
[0];
265 thread
[tid
] = new Thread(this, tid
, dummy_proc
);
268 // Eventually set this with parameters...
272 // Setup the TC that will serve as the interface to the threads/CPU.
273 InOrderThreadContext
*tc
= new InOrderThreadContext
;
275 tc
->thread
= thread
[tid
];
277 // Give the thread the TC.
278 thread
[tid
]->tc
= tc
;
279 thread
[tid
]->setFuncExeInst(0);
280 globalSeqNum
[tid
] = 1;
282 // Add the TC to the CPU's list of TC's.
283 this->threadContexts
.push_back(tc
);
286 // Initialize TimeBuffer Stage Queues
287 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
288 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
289 stageQueue
[stNum
]->id(stNum
);
293 // Set Up Pipeline Stages
294 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
296 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
298 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
300 pipelineStage
[stNum
]->setCPU(this);
301 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
302 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
304 // Take Care of 1st/Nth stages
306 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
307 if (stNum
< NumStages
- 1)
308 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
311 // Initialize thread specific variables
312 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
313 archRegDepMap
[tid
].setCPU(this);
315 nonSpecInstActive
[tid
] = false;
316 nonSpecSeqNum
[tid
] = 0;
318 squashSeqNum
[tid
] = MaxAddr
;
319 lastSquashCycle
[tid
] = 0;
321 memset(intRegs
[tid
], 0, sizeof(intRegs
[tid
]));
322 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
325 // Define dummy instructions and resource requests to be used.
326 dummyInst
[tid
] = new InOrderDynInst(this,
332 dummyReq
[tid
] = new ResourceRequest(resPool
->getResource(0));
335 dummyReqInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
336 dummyReqInst
->setSquashed();
337 dummyReqInst
->resetInstCount();
339 dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
340 dummyBufferInst
->setSquashed();
341 dummyBufferInst
->resetInstCount();
343 endOfSkedIt
= skedCache
.end();
344 frontEndSked
= createFrontEndSked();
346 lastRunningCycle
= curTick();
348 // Reset CPU to reset state.
350 Fault resetFault
= new ResetFault();
351 resetFault
->invoke(tcBase());
355 // Schedule First Tick Event, CPU will reschedule itself from here on out.
356 scheduleTickEvent(0);
359 InOrderCPU::~InOrderCPU()
363 SkedCacheIt sked_it
= skedCache
.begin();
364 SkedCacheIt sked_end
= skedCache
.end();
366 while (sked_it
!= sked_end
) {
367 delete (*sked_it
).second
;
373 m5::hash_map
<InOrderCPU::SkedID
, ThePipeline::RSkedPtr
> InOrderCPU::skedCache
;
376 InOrderCPU::createFrontEndSked()
378 RSkedPtr res_sked
= new ResourceSked();
380 StageScheduler
F(res_sked
, stage_num
++);
381 StageScheduler
D(res_sked
, stage_num
++);
384 F
.needs(FetchSeq
, FetchSeqUnit::AssignNextPC
);
385 F
.needs(ICache
, FetchUnit::InitiateFetch
);
388 D
.needs(ICache
, FetchUnit::CompleteFetch
);
389 D
.needs(Decode
, DecodeUnit::DecodeInst
);
390 D
.needs(BPred
, BranchPredictor::PredictBranch
);
391 D
.needs(FetchSeq
, FetchSeqUnit::UpdateTargetPC
);
394 DPRINTF(SkedCache
, "Resource Sked created for instruction \"front_end\"\n");
400 InOrderCPU::createBackEndSked(DynInstPtr inst
)
402 RSkedPtr res_sked
= lookupSked(inst
);
403 if (res_sked
!= NULL
) {
404 DPRINTF(SkedCache
, "Found %s in sked cache.\n",
408 res_sked
= new ResourceSked();
411 int stage_num
= ThePipeline::BackEndStartStage
;
412 StageScheduler
X(res_sked
, stage_num
++);
413 StageScheduler
M(res_sked
, stage_num
++);
414 StageScheduler
W(res_sked
, stage_num
++);
416 if (!inst
->staticInst
) {
417 warn_once("Static Instruction Object Not Set. Can't Create"
418 " Back End Schedule");
423 X
.needs(RegManager
, UseDefUnit::MarkDestRegs
);
424 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
425 if (!idx
|| !inst
->isStore()) {
426 X
.needs(RegManager
, UseDefUnit::ReadSrcReg
, idx
);
430 //@todo: schedule non-spec insts to operate on this cycle
431 // as long as all previous insts are done
432 if ( inst
->isNonSpeculative() ) {
433 // skip execution of non speculative insts until later
434 } else if ( inst
->isMemRef() ) {
435 if ( inst
->isLoad() ) {
436 X
.needs(AGEN
, AGENUnit::GenerateAddr
);
438 } else if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
439 X
.needs(MDU
, MultDivUnit::StartMultDiv
);
441 X
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
445 if (!inst
->isNonSpeculative()) {
446 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
447 M
.needs(MDU
, MultDivUnit::EndMultDiv
);
450 if ( inst
->isLoad() ) {
451 M
.needs(DCache
, CacheUnit::InitiateReadData
);
453 M
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
454 } else if ( inst
->isStore() ) {
455 for (int i
= 1; i
< inst
->numSrcRegs(); i
++ ) {
456 M
.needs(RegManager
, UseDefUnit::ReadSrcReg
, i
);
458 M
.needs(AGEN
, AGENUnit::GenerateAddr
);
459 M
.needs(DCache
, CacheUnit::InitiateWriteData
);
461 M
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
466 if (!inst
->isNonSpeculative()) {
467 if ( inst
->isLoad() ) {
468 W
.needs(DCache
, CacheUnit::CompleteReadData
);
470 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
471 } else if ( inst
->isStore() ) {
472 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
474 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
477 // Finally, Execute Speculative Data
478 if (inst
->isMemRef()) {
479 if (inst
->isLoad()) {
480 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
481 W
.needs(DCache
, CacheUnit::InitiateReadData
);
483 W
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
484 W
.needs(DCache
, CacheUnit::CompleteReadData
);
486 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
487 } else if (inst
->isStore()) {
488 if ( inst
->numSrcRegs() >= 2 ) {
489 W
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
491 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
492 W
.needs(DCache
, CacheUnit::InitiateWriteData
);
494 W
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
495 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
497 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
500 W
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
504 W
.needs(Grad
, GraduationUnit::GraduateInst
);
506 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
507 W
.needs(RegManager
, UseDefUnit::WriteDestReg
, idx
);
510 // Insert Back Schedule into our cache of
511 // resource schedules
512 addToSkedCache(inst
, res_sked
);
514 DPRINTF(SkedCache
, "Back End Sked Created for instruction: %s (%08p)\n",
515 inst
->instName(), inst
->getMachInst());
522 InOrderCPU::regStats()
524 /* Register the Resource Pool's stats here.*/
527 /* Register for each Pipeline Stage */
528 for (int stage_num
=0; stage_num
< ThePipeline::NumStages
; stage_num
++) {
529 pipelineStage
[stage_num
]->regStats();
532 /* Register any of the InOrderCPU's stats here.*/
534 .name(name() + ".instsPerContextSwitch")
535 .desc("Instructions Committed Per Context Switch")
536 .prereq(instsPerCtxtSwitch
);
539 .name(name() + ".contextSwitches")
540 .desc("Number of context switches");
543 .name(name() + ".comLoads")
544 .desc("Number of Load instructions committed");
547 .name(name() + ".comStores")
548 .desc("Number of Store instructions committed");
551 .name(name() + ".comBranches")
552 .desc("Number of Branches instructions committed");
555 .name(name() + ".comNops")
556 .desc("Number of Nop instructions committed");
559 .name(name() + ".comNonSpec")
560 .desc("Number of Non-Speculative instructions committed");
563 .name(name() + ".comInts")
564 .desc("Number of Integer instructions committed");
567 .name(name() + ".comFloats")
568 .desc("Number of Floating Point instructions committed");
571 .name(name() + ".timesIdled")
572 .desc("Number of times that the entire CPU went into an idle state and"
573 " unscheduled itself")
577 .name(name() + ".idleCycles")
578 .desc("Number of cycles cpu's stages were not processed");
581 .name(name() + ".runCycles")
582 .desc("Number of cycles cpu stages are processed.");
585 .name(name() + ".activity")
586 .desc("Percentage of cycles cpu is active")
588 activity
= (runCycles
/ numCycles
) * 100;
592 .name(name() + ".threadCycles")
593 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
596 .name(name() + ".smtCycles")
597 .desc("Total number of cycles that the CPU was in SMT-mode");
601 .name(name() + ".committedInsts")
602 .desc("Number of Instructions Simulated (Per-Thread)");
606 .name(name() + ".smtCommittedInsts")
607 .desc("Number of SMT Instructions Simulated (Per-Thread)");
610 .name(name() + ".committedInsts_total")
611 .desc("Number of Instructions Simulated (Total)");
614 .name(name() + ".cpi")
615 .desc("CPI: Cycles Per Instruction (Per-Thread)")
617 cpi
= numCycles
/ committedInsts
;
620 .name(name() + ".smt_cpi")
621 .desc("CPI: Total SMT-CPI")
623 smtCpi
= smtCycles
/ smtCommittedInsts
;
626 .name(name() + ".cpi_total")
627 .desc("CPI: Total CPI of All Threads")
629 totalCpi
= numCycles
/ totalCommittedInsts
;
632 .name(name() + ".ipc")
633 .desc("IPC: Instructions Per Cycle (Per-Thread)")
635 ipc
= committedInsts
/ numCycles
;
638 .name(name() + ".smt_ipc")
639 .desc("IPC: Total SMT-IPC")
641 smtIpc
= smtCommittedInsts
/ smtCycles
;
644 .name(name() + ".ipc_total")
645 .desc("IPC: Total IPC of All Threads")
647 totalIpc
= totalCommittedInsts
/ numCycles
;
656 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
660 bool pipes_idle
= true;
662 //Tick each of the stages
663 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
664 pipelineStage
[stNum
]->tick();
666 pipes_idle
= pipes_idle
&& pipelineStage
[stNum
]->idle
;
674 // Now advance the time buffers one tick
675 timeBuffer
.advance();
676 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
677 stageQueue
[sqNum
]->advance();
679 activityRec
.advance();
681 // Any squashed events, or insts then remove them now
682 cleanUpRemovedEvents();
683 cleanUpRemovedInsts();
685 // Re-schedule CPU for this cycle
686 if (!tickEvent
.scheduled()) {
687 if (_status
== SwitchedOut
) {
689 lastRunningCycle
= curTick();
690 } else if (!activityRec
.active()) {
691 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
692 lastRunningCycle
= curTick();
695 //Tick next_tick = curTick() + cycles(1);
696 //tickEvent.schedule(next_tick);
697 schedule(&tickEvent
, nextCycle(curTick() + 1));
698 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n",
699 nextCycle(curTick() + 1));
704 updateThreadPriority();
711 if (!deferRegistration
) {
712 registerThreadContexts();
715 // Set inSyscall so that the CPU doesn't squash when initially
716 // setting up registers.
717 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
718 thread
[tid
]->inSyscall
= true;
721 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
722 ThreadContext
*src_tc
= threadContexts
[tid
];
723 TheISA::initCPU(src_tc
, src_tc
->contextId());
728 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
729 thread
[tid
]->inSyscall
= false;
731 // Call Initializiation Routine for Resource Pool
736 InOrderCPU::getPort(const std::string
&if_name
, int idx
)
738 return resPool
->getPort(if_name
, idx
);
743 InOrderCPU::hwrei(ThreadID tid
)
745 panic("hwrei: Unimplemented");
752 InOrderCPU::simPalCheck(int palFunc
, ThreadID tid
)
754 panic("simPalCheck: Unimplemented");
761 InOrderCPU::getInterrupts()
763 // Check if there are any outstanding interrupts
764 return interrupts
->getInterrupt(threadContexts
[0]);
769 InOrderCPU::processInterrupts(Fault interrupt
)
771 // Check for interrupts here. For now can copy the code that
772 // exists within isa_fullsys_traits.hh. Also assume that thread 0
773 // is the one that handles the interrupts.
774 // @todo: Possibly consolidate the interrupt checking code.
775 // @todo: Allow other threads to handle interrupts.
777 assert(interrupt
!= NoFault
);
778 interrupts
->updateIntrInfo(threadContexts
[0]);
780 DPRINTF(InOrderCPU
, "Interrupt %s being handled\n", interrupt
->name());
782 // Note: Context ID ok here? Impl. of FS mode needs to revisit this
783 trap(interrupt
, threadContexts
[0]->contextId(), dummyBufferInst
);
788 InOrderCPU::updateMemPorts()
790 // Update all ThreadContext's memory ports (Functional/Virtual
792 ThreadID size
= thread
.size();
793 for (ThreadID i
= 0; i
< size
; ++i
)
794 thread
[i
]->connectMemPorts(thread
[i
]->getTC());
799 InOrderCPU::trapContext(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
801 scheduleCpuEvent(Trap
, fault
, tid
, inst
, delay
);
805 InOrderCPU::trap(Fault fault
, ThreadID tid
, DynInstPtr inst
)
807 fault
->invoke(tcBase(tid
), inst
->staticInst
);
811 InOrderCPU::squashFromMemStall(DynInstPtr inst
, ThreadID tid
, int delay
)
813 scheduleCpuEvent(SquashFromMemStall
, NoFault
, tid
, inst
, delay
);
818 InOrderCPU::squashDueToMemStall(int stage_num
, InstSeqNum seq_num
,
821 DPRINTF(InOrderCPU
, "Squashing Pipeline Stages Due to Memory Stall...\n");
823 // Squash all instructions in each stage including
824 // instruction that caused the squash (seq_num - 1)
825 // NOTE: The stage bandwidth needs to be cleared so thats why
826 // the stalling instruction is squashed as well. The stalled
827 // instruction is previously placed in another intermediate buffer
828 // while it's stall is being handled.
829 InstSeqNum squash_seq_num
= seq_num
- 1;
831 for (int stNum
=stage_num
; stNum
>= 0 ; stNum
--) {
832 pipelineStage
[stNum
]->squashDueToMemStall(squash_seq_num
, tid
);
837 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
838 ThreadID tid
, DynInstPtr inst
,
839 unsigned delay
, unsigned event_pri_offset
)
841 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, inst
,
844 Tick sked_tick
= nextCycle(curTick() + ticks(delay
));
846 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
847 eventNames
[c_event
], curTick() + delay
, tid
);
848 schedule(cpu_event
, sked_tick
);
850 cpu_event
->process();
851 cpuEventRemoveList
.push(cpu_event
);
854 // Broadcast event to the Resource Pool
855 // Need to reset tid just in case this is a dummy instruction
857 resPool
->scheduleEvent(c_event
, inst
, 0, 0, tid
);
861 InOrderCPU::isThreadActive(ThreadID tid
)
863 list
<ThreadID
>::iterator isActive
=
864 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
866 return (isActive
!= activeThreads
.end());
870 InOrderCPU::isThreadReady(ThreadID tid
)
872 list
<ThreadID
>::iterator isReady
=
873 std::find(readyThreads
.begin(), readyThreads
.end(), tid
);
875 return (isReady
!= readyThreads
.end());
879 InOrderCPU::isThreadSuspended(ThreadID tid
)
881 list
<ThreadID
>::iterator isSuspended
=
882 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
884 return (isSuspended
!= suspendedThreads
.end());
888 InOrderCPU::activateNextReadyThread()
890 if (readyThreads
.size() >= 1) {
891 ThreadID ready_tid
= readyThreads
.front();
893 // Activate in Pipeline
894 activateThread(ready_tid
);
896 // Activate in Resource Pool
897 resPool
->activateAll(ready_tid
);
899 list
<ThreadID
>::iterator ready_it
=
900 std::find(readyThreads
.begin(), readyThreads
.end(), ready_tid
);
901 readyThreads
.erase(ready_it
);
904 "Attempting to activate new thread, but No Ready Threads to"
907 "Unable to switch to next active thread.\n");
912 InOrderCPU::activateThread(ThreadID tid
)
914 if (isThreadSuspended(tid
)) {
916 "Removing [tid:%i] from suspended threads list.\n", tid
);
918 list
<ThreadID
>::iterator susp_it
=
919 std::find(suspendedThreads
.begin(), suspendedThreads
.end(),
921 suspendedThreads
.erase(susp_it
);
924 if (threadModel
== SwitchOnCacheMiss
&&
925 numActiveThreads() == 1) {
927 "Ignoring activation of [tid:%i], since [tid:%i] is "
928 "already running.\n", tid
, activeThreadId());
930 DPRINTF(InOrderCPU
,"Placing [tid:%i] on ready threads list\n",
933 readyThreads
.push_back(tid
);
935 } else if (!isThreadActive(tid
)) {
937 "Adding [tid:%i] to active threads list.\n", tid
);
938 activeThreads
.push_back(tid
);
940 activateThreadInPipeline(tid
);
942 thread
[tid
]->lastActivate
= curTick();
944 tcBase(tid
)->setStatus(ThreadContext::Active
);
953 InOrderCPU::activateThreadInPipeline(ThreadID tid
)
955 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
956 pipelineStage
[stNum
]->activateThread(tid
);
961 InOrderCPU::deactivateContext(ThreadID tid
, int delay
)
963 DPRINTF(InOrderCPU
,"[tid:%i]: Deactivating ...\n", tid
);
965 scheduleCpuEvent(DeactivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
967 // Be sure to signal that there's some activity so the CPU doesn't
968 // deschedule itself.
969 activityRec
.activity();
975 InOrderCPU::deactivateThread(ThreadID tid
)
977 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
979 if (isThreadActive(tid
)) {
980 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
982 list
<ThreadID
>::iterator thread_it
=
983 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
985 removePipelineStalls(*thread_it
);
987 activeThreads
.erase(thread_it
);
989 // Ideally, this should be triggered from the
990 // suspendContext/Thread functions
991 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
994 assert(!isThreadActive(tid
));
998 InOrderCPU::removePipelineStalls(ThreadID tid
)
1000 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
1003 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
1004 pipelineStage
[stNum
]->removeStalls(tid
);
1010 InOrderCPU::updateThreadPriority()
1012 if (activeThreads
.size() > 1)
1014 //DEFAULT TO ROUND ROBIN SCHEME
1015 //e.g. Move highest priority to end of thread list
1016 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
1017 list
<ThreadID
>::iterator list_end
= activeThreads
.end();
1019 unsigned high_thread
= *list_begin
;
1021 activeThreads
.erase(list_begin
);
1023 activeThreads
.push_back(high_thread
);
1028 InOrderCPU::tickThreadStats()
1030 /** Keep track of cycles that each thread is active */
1031 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
1032 while (thread_it
!= activeThreads
.end()) {
1033 threadCycles
[*thread_it
]++;
1037 // Keep track of cycles where SMT is active
1038 if (activeThreads
.size() > 1) {
1044 InOrderCPU::activateContext(ThreadID tid
, int delay
)
1046 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
1049 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1051 // Be sure to signal that there's some activity so the CPU doesn't
1052 // deschedule itself.
1053 activityRec
.activity();
1059 InOrderCPU::activateNextReadyContext(int delay
)
1061 DPRINTF(InOrderCPU
,"Activating next ready thread\n");
1063 // NOTE: Add 5 to the event priority so that we always activate
1064 // threads after we've finished deactivating, squashing,etc.
1066 scheduleCpuEvent(ActivateNextReadyThread
, NoFault
, 0/*tid*/, dummyInst
[0],
1069 // Be sure to signal that there's some activity so the CPU doesn't
1070 // deschedule itself.
1071 activityRec
.activity();
1077 InOrderCPU::haltContext(ThreadID tid
, int delay
)
1079 DPRINTF(InOrderCPU
, "[tid:%i]: Calling Halt Context...\n", tid
);
1081 scheduleCpuEvent(HaltThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1083 activityRec
.activity();
1087 InOrderCPU::haltThread(ThreadID tid
)
1089 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Halted Threads List...\n", tid
);
1090 deactivateThread(tid
);
1091 squashThreadInPipeline(tid
);
1092 haltedThreads
.push_back(tid
);
1094 tcBase(tid
)->setStatus(ThreadContext::Halted
);
1096 if (threadModel
== SwitchOnCacheMiss
) {
1097 activateNextReadyContext();
1102 InOrderCPU::suspendContext(ThreadID tid
, int delay
)
1104 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1108 InOrderCPU::suspendThread(ThreadID tid
)
1110 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Suspended Threads List...\n",
1112 deactivateThread(tid
);
1113 suspendedThreads
.push_back(tid
);
1114 thread
[tid
]->lastSuspend
= curTick();
1116 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1120 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
1122 //Squash all instructions in each stage
1123 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
1124 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
1129 InOrderCPU::getPipeStage(int stage_num
)
1131 return pipelineStage
[stage_num
];
1135 InOrderCPU::flattenRegIdx(RegIndex reg_idx
, RegType
®_type
, ThreadID tid
)
1137 if (reg_idx
< FP_Base_DepTag
) {
1139 return isa
[tid
].flattenIntIndex(reg_idx
);
1140 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1141 reg_type
= FloatType
;
1142 reg_idx
-= FP_Base_DepTag
;
1143 return isa
[tid
].flattenFloatIndex(reg_idx
);
1145 reg_type
= MiscType
;
1146 return reg_idx
- TheISA::Ctrl_Base_DepTag
;
1151 InOrderCPU::readIntReg(RegIndex reg_idx
, ThreadID tid
)
1153 DPRINTF(IntRegs
, "[tid:%i]: Reading Int. Reg %i as %x\n",
1154 tid
, reg_idx
, intRegs
[tid
][reg_idx
]);
1156 return intRegs
[tid
][reg_idx
];
1160 InOrderCPU::readFloatReg(RegIndex reg_idx
, ThreadID tid
)
1162 return floatRegs
.f
[tid
][reg_idx
];
1166 InOrderCPU::readFloatRegBits(RegIndex reg_idx
, ThreadID tid
)
1168 return floatRegs
.i
[tid
][reg_idx
];
1172 InOrderCPU::setIntReg(RegIndex reg_idx
, uint64_t val
, ThreadID tid
)
1174 if (reg_idx
== TheISA::ZeroReg
) {
1175 DPRINTF(IntRegs
, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1176 "(Int. Reg %i) to %x\n", tid
, reg_idx
, val
);
1179 DPRINTF(IntRegs
, "[tid:%i]: Setting Int. Reg %i to %x\n",
1182 intRegs
[tid
][reg_idx
] = val
;
1188 InOrderCPU::setFloatReg(RegIndex reg_idx
, FloatReg val
, ThreadID tid
)
1190 floatRegs
.f
[tid
][reg_idx
] = val
;
1195 InOrderCPU::setFloatRegBits(RegIndex reg_idx
, FloatRegBits val
, ThreadID tid
)
1197 floatRegs
.i
[tid
][reg_idx
] = val
;
1201 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
1203 // If Default value is set, then retrieve target thread
1204 if (tid
== InvalidThreadID
) {
1205 tid
= TheISA::getTargetThread(tcBase(tid
));
1208 if (reg_idx
< FP_Base_DepTag
) {
1209 // Integer Register File
1210 return readIntReg(reg_idx
, tid
);
1211 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1212 // Float Register File
1213 reg_idx
-= FP_Base_DepTag
;
1214 return readFloatRegBits(reg_idx
, tid
);
1216 reg_idx
-= Ctrl_Base_DepTag
;
1217 return readMiscReg(reg_idx
, tid
); // Misc. Register File
1221 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
1224 // If Default value is set, then retrieve target thread
1225 if (tid
== InvalidThreadID
) {
1226 tid
= TheISA::getTargetThread(tcBase(tid
));
1229 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
1230 setIntReg(reg_idx
, val
, tid
);
1231 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
1232 reg_idx
-= FP_Base_DepTag
;
1233 setFloatRegBits(reg_idx
, val
, tid
);
1235 reg_idx
-= Ctrl_Base_DepTag
;
1236 setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
1241 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1243 return isa
[tid
].readMiscRegNoEffect(misc_reg
);
1247 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
1249 return isa
[tid
].readMiscReg(misc_reg
, tcBase(tid
));
1253 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1255 isa
[tid
].setMiscRegNoEffect(misc_reg
, val
);
1259 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1261 isa
[tid
].setMiscReg(misc_reg
, val
, tcBase(tid
));
1266 InOrderCPU::addInst(DynInstPtr inst
)
1268 ThreadID tid
= inst
->readTid();
1270 instList
[tid
].push_back(inst
);
1272 return --(instList
[tid
].end());
1276 InOrderCPU::findInst(InstSeqNum seq_num
, ThreadID tid
)
1278 ListIt it
= instList
[tid
].begin();
1279 ListIt end
= instList
[tid
].end();
1282 if ((*it
)->seqNum
== seq_num
)
1284 else if ((*it
)->seqNum
> seq_num
)
1290 return instList
[tid
].end();
1294 InOrderCPU::updateContextSwitchStats()
1296 // Set Average Stat Here, then reset to 0
1297 instsPerCtxtSwitch
= instsPerSwitch
;
1303 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1305 // Set the nextPC to be fetched if this is the last instruction
1308 // This contributes to the precise state of the CPU
1309 // which can be used when restoring a thread to the CPU after after any
1310 // type of context switching activity (fork, exception, etc.)
1311 TheISA::PCState comm_pc
= inst
->pcState();
1312 lastCommittedPC
[tid
] = comm_pc
;
1313 TheISA::advancePC(comm_pc
, inst
->staticInst
);
1314 pcState(comm_pc
, tid
);
1316 //@todo: may be unnecessary with new-ISA-specific branch handling code
1317 if (inst
->isControl()) {
1318 thread
[tid
]->lastGradIsBranch
= true;
1319 thread
[tid
]->lastBranchPC
= inst
->pcState();
1320 TheISA::advancePC(thread
[tid
]->lastBranchPC
, inst
->staticInst
);
1322 thread
[tid
]->lastGradIsBranch
= false;
1326 // Finalize Trace Data For Instruction
1327 if (inst
->traceData
) {
1328 //inst->traceData->setCycle(curTick());
1329 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1330 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1331 inst
->traceData
->dump();
1332 delete inst
->traceData
;
1333 inst
->traceData
= NULL
;
1336 // Increment active thread's instruction count
1339 // Increment thread-state's instruction count
1340 thread
[tid
]->numInst
++;
1342 // Increment thread-state's instruction stats
1343 thread
[tid
]->numInsts
++;
1345 // Count committed insts per thread stats
1346 committedInsts
[tid
]++;
1348 // Count total insts committed stat
1349 totalCommittedInsts
++;
1351 // Count SMT-committed insts per thread stat
1352 if (numActiveThreads() > 1) {
1353 smtCommittedInsts
[tid
]++;
1356 // Instruction-Mix Stats
1357 if (inst
->isLoad()) {
1359 } else if (inst
->isStore()) {
1361 } else if (inst
->isControl()) {
1363 } else if (inst
->isNop()) {
1365 } else if (inst
->isNonSpeculative()) {
1367 } else if (inst
->isInteger()) {
1369 } else if (inst
->isFloating()) {
1373 // Check for instruction-count-based events.
1374 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numInst
);
1376 // Broadcast to other resources an instruction
1377 // has been completed
1378 resPool
->scheduleEvent((CPUEventType
)ResourcePool::InstGraduated
, inst
,
1381 // Finally, remove instruction from CPU
1385 // currently unused function, but substitute repetitive code w/this function
1388 InOrderCPU::addToRemoveList(DynInstPtr inst
)
1390 removeInstsThisCycle
= true;
1391 if (!inst
->isRemoveList()) {
1392 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1393 "[sn:%lli] to remove list\n",
1394 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1395 inst
->setRemoveList();
1396 removeList
.push(inst
->getInstListIt());
1398 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1399 "[sn:%lli], already remove list\n",
1400 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1406 InOrderCPU::removeInst(DynInstPtr inst
)
1408 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %s "
1410 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1412 removeInstsThisCycle
= true;
1414 // Remove the instruction.
1415 if (!inst
->isRemoveList()) {
1416 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1417 "[sn:%lli] to remove list\n",
1418 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1419 inst
->setRemoveList();
1420 removeList
.push(inst
->getInstListIt());
1422 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1423 "[sn:%lli], already on remove list\n",
1424 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1430 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1432 //assert(!instList[tid].empty());
1434 removeInstsThisCycle
= true;
1436 ListIt inst_iter
= instList
[tid
].end();
1440 DPRINTF(InOrderCPU
, "Squashing instructions from CPU instruction "
1441 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1442 tid
, seq_num
, (*inst_iter
)->seqNum
);
1444 while ((*inst_iter
)->seqNum
> seq_num
) {
1446 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1448 squashInstIt(inst_iter
, tid
);
1459 InOrderCPU::squashInstIt(const ListIt
&instIt
, ThreadID tid
)
1461 if ((*instIt
)->threadNumber
== tid
) {
1462 DPRINTF(InOrderCPU
, "Squashing instruction, "
1463 "[tid:%i] [sn:%lli] PC %s\n",
1464 (*instIt
)->threadNumber
,
1466 (*instIt
)->pcState());
1468 (*instIt
)->setSquashed();
1470 if (!(*instIt
)->isRemoveList()) {
1471 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1472 "[sn:%lli] to remove list\n",
1473 (*instIt
)->threadNumber
, (*instIt
)->pcState(),
1475 (*instIt
)->setRemoveList();
1476 removeList
.push(instIt
);
1478 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i]"
1479 " PC %s [sn:%lli], already on remove list\n",
1480 (*instIt
)->threadNumber
, (*instIt
)->pcState(),
1490 InOrderCPU::cleanUpRemovedInsts()
1492 while (!removeList
.empty()) {
1493 DPRINTF(InOrderCPU
, "Removing instruction, "
1494 "[tid:%i] [sn:%lli] PC %s\n",
1495 (*removeList
.front())->threadNumber
,
1496 (*removeList
.front())->seqNum
,
1497 (*removeList
.front())->pcState());
1499 DynInstPtr inst
= *removeList
.front();
1500 ThreadID tid
= inst
->threadNumber
;
1502 // Remove From Register Dependency Map, If Necessary
1503 archRegDepMap
[tid
].remove(inst
);
1505 // Clear if Non-Speculative
1506 if (inst
->staticInst
&&
1507 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1508 nonSpecInstActive
[tid
] == true) {
1509 nonSpecInstActive
[tid
] = false;
1512 inst
->onInstList
= false;
1514 instList
[tid
].erase(removeList
.front());
1519 removeInstsThisCycle
= false;
1523 InOrderCPU::cleanUpRemovedEvents()
1525 while (!cpuEventRemoveList
.empty()) {
1526 Event
*cpu_event
= cpuEventRemoveList
.front();
1527 cpuEventRemoveList
.pop();
1534 InOrderCPU::dumpInsts()
1538 ListIt inst_list_it
= instList
[0].begin();
1540 cprintf("Dumping Instruction List\n");
1542 while (inst_list_it
!= instList
[0].end()) {
1543 cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1545 num
, (*inst_list_it
)->pcState(),
1546 (*inst_list_it
)->threadNumber
,
1547 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1548 (*inst_list_it
)->isSquashed());
1555 InOrderCPU::wakeCPU()
1557 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1558 DPRINTF(Activity
, "CPU already running.\n");
1562 DPRINTF(Activity
, "Waking up CPU\n");
1564 Tick extra_cycles
= tickToCycles((curTick() - 1) - lastRunningCycle
);
1566 idleCycles
+= extra_cycles
;
1567 for (int stage_num
= 0; stage_num
< NumStages
; stage_num
++) {
1568 pipelineStage
[stage_num
]->idleCycles
+= extra_cycles
;
1571 numCycles
+= extra_cycles
;
1573 schedule(&tickEvent
, nextCycle(curTick()));
1579 InOrderCPU::wakeup()
1581 if (thread
[0]->status() != ThreadContext::Suspended
)
1586 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1587 threadContexts
[0]->activate();
1593 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1595 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1597 DPRINTF(Activity
,"Activity: syscall() called.\n");
1599 // Temporarily increase this by one to account for the syscall
1601 ++(this->thread
[tid
]->funcExeInst
);
1603 // Execute the actual syscall.
1604 this->thread
[tid
]->syscall(callnum
);
1606 // Decrease funcExeInst by one as the normal commit will handle
1608 --(this->thread
[tid
]->funcExeInst
);
1610 // Clear Non-Speculative Block Variable
1611 nonSpecInstActive
[tid
] = false;
1616 InOrderCPU::getITBPtr()
1618 CacheUnit
*itb_res
=
1619 dynamic_cast<CacheUnit
*>(resPool
->getResource(fetchPortIdx
));
1620 return itb_res
->tlb();
1625 InOrderCPU::getDTBPtr()
1627 CacheUnit
*dtb_res
=
1628 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1629 return dtb_res
->tlb();
1633 InOrderCPU::read(DynInstPtr inst
, Addr addr
,
1634 uint8_t *data
, unsigned size
, unsigned flags
)
1636 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1637 // you want to run w/out caches?
1638 CacheUnit
*cache_res
=
1639 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1641 return cache_res
->read(inst
, addr
, data
, size
, flags
);
1645 InOrderCPU::write(DynInstPtr inst
, uint8_t *data
, unsigned size
,
1646 Addr addr
, unsigned flags
, uint64_t *write_res
)
1648 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1649 // you want to run w/out caches?
1650 CacheUnit
*cache_res
=
1651 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1652 return cache_res
->write(inst
, data
, size
, addr
, flags
, write_res
);