2 * Copyright (c) 2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
15 * Copyright (c) 2007 MIPS Technologies, Inc.
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Korey Sewell
47 #include "arch/utility.hh"
48 #include "base/bigint.hh"
49 #include "config/the_isa.hh"
50 #include "cpu/inorder/resources/cache_unit.hh"
51 #include "cpu/inorder/resources/resource_list.hh"
52 #include "cpu/inorder/cpu.hh"
53 #include "cpu/inorder/first_stage.hh"
54 #include "cpu/inorder/inorder_dyn_inst.hh"
55 #include "cpu/inorder/pipeline_traits.hh"
56 #include "cpu/inorder/resource_pool.hh"
57 #include "cpu/inorder/thread_context.hh"
58 #include "cpu/inorder/thread_state.hh"
59 #include "cpu/activity.hh"
60 #include "cpu/base.hh"
61 #include "cpu/exetrace.hh"
62 #include "cpu/quiesce_event.hh"
63 #include "cpu/reg_class.hh"
64 #include "cpu/simple_thread.hh"
65 #include "cpu/thread_context.hh"
66 #include "debug/Activity.hh"
67 #include "debug/InOrderCPU.hh"
68 #include "debug/InOrderCachePort.hh"
69 #include "debug/Interrupt.hh"
70 #include "debug/Quiesce.hh"
71 #include "debug/RefCount.hh"
72 #include "debug/SkedCache.hh"
73 #include "params/InOrderCPU.hh"
74 #include "sim/full_system.hh"
75 #include "sim/process.hh"
76 #include "sim/stat_control.hh"
77 #include "sim/system.hh"
79 #if THE_ISA == ALPHA_ISA
80 #include "arch/alpha/osfpal.hh"
84 using namespace TheISA
;
85 using namespace ThePipeline
;
87 InOrderCPU::CachePort::CachePort(CacheUnit
*_cacheUnit
,
88 const std::string
& name
) :
89 MasterPort(_cacheUnit
->name() + name
, _cacheUnit
->cpu
),
94 InOrderCPU::CachePort::recvTimingResp(Packet
*pkt
)
97 DPRINTF(InOrderCachePort
, "Got error packet back for address: %x\n",
100 cacheUnit
->processCacheCompletion(pkt
);
106 InOrderCPU::CachePort::recvRetry()
108 cacheUnit
->recvRetry();
111 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
112 : Event(CPU_Tick_Pri
), cpu(c
)
117 InOrderCPU::TickEvent::process()
124 InOrderCPU::TickEvent::description() const
126 return "InOrderCPU tick event";
129 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
130 Fault fault
, ThreadID _tid
, DynInstPtr inst
,
131 CPUEventPri event_pri
)
132 : Event(event_pri
), cpu(_cpu
)
134 setEvent(e_type
, fault
, _tid
, inst
);
138 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
141 "ActivateNextReadyThread",
147 "SquashFromMemStall",
152 InOrderCPU::CPUEvent::process()
154 switch (cpuEventType
)
157 cpu
->activateThread(tid
);
158 cpu
->resPool
->activateThread(tid
);
161 case ActivateNextReadyThread
:
162 cpu
->activateNextReadyThread();
165 case DeactivateThread
:
166 cpu
->deactivateThread(tid
);
167 cpu
->resPool
->deactivateThread(tid
);
171 cpu
->haltThread(tid
);
172 cpu
->resPool
->deactivateThread(tid
);
176 cpu
->suspendThread(tid
);
177 cpu
->resPool
->suspendThread(tid
);
180 case SquashFromMemStall
:
181 cpu
->squashDueToMemStall(inst
->squashingStage
, inst
->seqNum
, tid
);
182 cpu
->resPool
->squashDueToMemStall(inst
, inst
->squashingStage
,
187 DPRINTF(InOrderCPU
, "Trapping CPU\n");
188 cpu
->trap(fault
, tid
, inst
);
189 cpu
->resPool
->trap(fault
, tid
, inst
);
190 cpu
->trapPending
[tid
] = false;
194 cpu
->syscall(inst
->syscallNum
, tid
);
195 cpu
->resPool
->trap(fault
, tid
, inst
);
199 fatal("Unrecognized Event Type %s", eventNames
[cpuEventType
]);
202 cpu
->cpuEventRemoveList
.push(this);
208 InOrderCPU::CPUEvent::description() const
210 return "InOrderCPU event";
214 InOrderCPU::CPUEvent::scheduleEvent(Cycles delay
)
216 assert(!scheduled() || squashed());
217 cpu
->reschedule(this, cpu
->clockEdge(delay
), true);
221 InOrderCPU::CPUEvent::unscheduleEvent()
227 InOrderCPU::InOrderCPU(Params
*params
)
229 cpu_id(params
->cpu_id
),
233 stageWidth(params
->stageWidth
),
234 resPool(new ResourcePool(this, params
)),
235 isa(numThreads
, NULL
),
237 dataPort(resPool
->getDataUnit(), ".dcache_port"),
238 instPort(resPool
->getInstUnit(), ".icache_port"),
239 removeInstsThisCycle(false),
240 activityRec(params
->name
, NumStages
, 10, params
->activity
),
241 system(params
->system
),
247 stageTracing(params
->stageTracing
),
253 // Resize for Multithreading CPUs
254 thread
.resize(numThreads
);
256 ThreadID active_threads
= params
->workload
.size();
260 active_threads
= params
->workload
.size();
262 if (active_threads
> MaxThreads
) {
263 panic("Workload Size too large. Increase the 'MaxThreads'"
264 "in your InOrder implementation or "
265 "edit your workload size.");
269 if (active_threads
> 1) {
270 threadModel
= (InOrderCPU::ThreadModel
) params
->threadModel
;
272 if (threadModel
== SMT
) {
273 DPRINTF(InOrderCPU
, "Setting Thread Model to SMT.\n");
274 } else if (threadModel
== SwitchOnCacheMiss
) {
275 DPRINTF(InOrderCPU
, "Setting Thread Model to "
276 "Switch On Cache Miss\n");
280 threadModel
= Single
;
284 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
285 isa
[tid
] = params
->isa
[tid
];
287 lastCommittedPC
[tid
].set(0);
290 // SMT is not supported in FS mode yet.
291 assert(numThreads
== 1);
292 thread
[tid
] = new Thread(this, 0, NULL
);
294 if (tid
< (ThreadID
)params
->workload
.size()) {
295 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
296 tid
, params
->workload
[tid
]->progName());
298 new Thread(this, tid
, params
->workload
[tid
]);
300 //Allocate Empty thread so M5 can use later
301 //when scheduling threads to CPU
302 Process
* dummy_proc
= params
->workload
[0];
303 thread
[tid
] = new Thread(this, tid
, dummy_proc
);
306 // Eventually set this with parameters...
310 // Setup the TC that will serve as the interface to the threads/CPU.
311 InOrderThreadContext
*tc
= new InOrderThreadContext
;
313 tc
->thread
= thread
[tid
];
315 // Setup quiesce event.
316 this->thread
[tid
]->quiesceEvent
= new EndQuiesceEvent(tc
);
318 // Give the thread the TC.
319 thread
[tid
]->tc
= tc
;
320 thread
[tid
]->setFuncExeInst(0);
321 globalSeqNum
[tid
] = 1;
323 // Add the TC to the CPU's list of TC's.
324 this->threadContexts
.push_back(tc
);
327 // Initialize TimeBuffer Stage Queues
328 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
329 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
330 stageQueue
[stNum
]->id(stNum
);
334 // Set Up Pipeline Stages
335 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
337 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
339 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
341 pipelineStage
[stNum
]->setCPU(this);
342 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
343 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
345 // Take Care of 1st/Nth stages
347 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
348 if (stNum
< NumStages
- 1)
349 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
352 // Initialize thread specific variables
353 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
354 archRegDepMap
[tid
].setCPU(this);
356 nonSpecInstActive
[tid
] = false;
357 nonSpecSeqNum
[tid
] = 0;
359 squashSeqNum
[tid
] = MaxAddr
;
360 lastSquashCycle
[tid
] = 0;
362 memset(intRegs
[tid
], 0, sizeof(intRegs
[tid
]));
363 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
366 // Define dummy instructions and resource requests to be used.
367 dummyInst
[tid
] = new InOrderDynInst(this,
373 dummyReq
[tid
] = new ResourceRequest(resPool
->getResource(0));
377 // Use this dummy inst to force squashing behind every instruction
379 dummyTrapInst
[tid
] = new InOrderDynInst(this, NULL
, 0, 0, 0);
380 dummyTrapInst
[tid
]->seqNum
= 0;
381 dummyTrapInst
[tid
]->squashSeqNum
= 0;
382 dummyTrapInst
[tid
]->setTid(tid
);
385 trapPending
[tid
] = false;
389 // InOrderCPU always requires an interrupt controller.
390 if (!params
->switched_out
&& !interrupts
) {
391 fatal("InOrderCPU %s has no interrupt controller.\n"
392 "Ensure createInterruptController() is called.\n", name());
395 dummyReqInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
396 dummyReqInst
->setSquashed();
397 dummyReqInst
->resetInstCount();
399 dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
400 dummyBufferInst
->setSquashed();
401 dummyBufferInst
->resetInstCount();
403 endOfSkedIt
= skedCache
.end();
404 frontEndSked
= createFrontEndSked();
405 faultSked
= createFaultSked();
407 lastRunningCycle
= curCycle();
412 // Schedule First Tick Event, CPU will reschedule itself from here on out.
413 scheduleTickEvent(Cycles(0));
416 InOrderCPU::~InOrderCPU()
420 SkedCacheIt sked_it
= skedCache
.begin();
421 SkedCacheIt sked_end
= skedCache
.end();
423 while (sked_it
!= sked_end
) {
424 delete (*sked_it
).second
;
430 m5::hash_map
<InOrderCPU::SkedID
, ThePipeline::RSkedPtr
> InOrderCPU::skedCache
;
433 InOrderCPU::createFrontEndSked()
435 RSkedPtr res_sked
= new ResourceSked();
437 StageScheduler
F(res_sked
, stage_num
++);
438 StageScheduler
D(res_sked
, stage_num
++);
441 F
.needs(FetchSeq
, FetchSeqUnit::AssignNextPC
);
442 F
.needs(ICache
, FetchUnit::InitiateFetch
);
445 D
.needs(ICache
, FetchUnit::CompleteFetch
);
446 D
.needs(Decode
, DecodeUnit::DecodeInst
);
447 D
.needs(BPred
, BranchPredictor::PredictBranch
);
448 D
.needs(FetchSeq
, FetchSeqUnit::UpdateTargetPC
);
451 DPRINTF(SkedCache
, "Resource Sked created for instruction Front End\n");
457 InOrderCPU::createFaultSked()
459 RSkedPtr res_sked
= new ResourceSked();
460 StageScheduler
W(res_sked
, NumStages
- 1);
461 W
.needs(Grad
, GraduationUnit::CheckFault
);
462 DPRINTF(SkedCache
, "Resource Sked created for instruction Faults\n");
467 InOrderCPU::createBackEndSked(DynInstPtr inst
)
469 RSkedPtr res_sked
= lookupSked(inst
);
470 if (res_sked
!= NULL
) {
471 DPRINTF(SkedCache
, "Found %s in sked cache.\n",
475 res_sked
= new ResourceSked();
478 int stage_num
= ThePipeline::BackEndStartStage
;
479 StageScheduler
X(res_sked
, stage_num
++);
480 StageScheduler
M(res_sked
, stage_num
++);
481 StageScheduler
W(res_sked
, stage_num
++);
483 if (!inst
->staticInst
) {
484 warn_once("Static Instruction Object Not Set. Can't Create"
485 " Back End Schedule");
490 X
.needs(RegManager
, UseDefUnit::MarkDestRegs
);
491 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
492 if (!idx
|| !inst
->isStore()) {
493 X
.needs(RegManager
, UseDefUnit::ReadSrcReg
, idx
);
497 //@todo: schedule non-spec insts to operate on this cycle
498 // as long as all previous insts are done
499 if ( inst
->isNonSpeculative() ) {
500 // skip execution of non speculative insts until later
501 } else if ( inst
->isMemRef() ) {
502 if ( inst
->isLoad() ) {
503 X
.needs(AGEN
, AGENUnit::GenerateAddr
);
505 } else if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
506 X
.needs(MDU
, MultDivUnit::StartMultDiv
);
508 X
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
512 if (!inst
->isNonSpeculative()) {
513 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
514 M
.needs(MDU
, MultDivUnit::EndMultDiv
);
517 if ( inst
->isLoad() ) {
518 M
.needs(DCache
, CacheUnit::InitiateReadData
);
520 M
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
521 } else if ( inst
->isStore() ) {
522 for (int i
= 1; i
< inst
->numSrcRegs(); i
++ ) {
523 M
.needs(RegManager
, UseDefUnit::ReadSrcReg
, i
);
525 M
.needs(AGEN
, AGENUnit::GenerateAddr
);
526 M
.needs(DCache
, CacheUnit::InitiateWriteData
);
528 M
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
533 if (!inst
->isNonSpeculative()) {
534 if ( inst
->isLoad() ) {
535 W
.needs(DCache
, CacheUnit::CompleteReadData
);
537 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
538 } else if ( inst
->isStore() ) {
539 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
541 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
544 // Finally, Execute Speculative Data
545 if (inst
->isMemRef()) {
546 if (inst
->isLoad()) {
547 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
548 W
.needs(DCache
, CacheUnit::InitiateReadData
);
550 W
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
551 W
.needs(DCache
, CacheUnit::CompleteReadData
);
553 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
554 } else if (inst
->isStore()) {
555 if ( inst
->numSrcRegs() >= 2 ) {
556 W
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
558 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
559 W
.needs(DCache
, CacheUnit::InitiateWriteData
);
561 W
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
562 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
564 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
567 W
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
571 W
.needs(Grad
, GraduationUnit::CheckFault
);
573 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
574 W
.needs(RegManager
, UseDefUnit::WriteDestReg
, idx
);
577 if (inst
->isControl())
578 W
.needs(BPred
, BranchPredictor::UpdatePredictor
);
580 W
.needs(Grad
, GraduationUnit::GraduateInst
);
582 // Insert Back Schedule into our cache of
583 // resource schedules
584 addToSkedCache(inst
, res_sked
);
586 DPRINTF(SkedCache
, "Back End Sked Created for instruction: %s (%08p)\n",
587 inst
->instName(), inst
->getMachInst());
594 InOrderCPU::regStats()
596 /* Register the Resource Pool's stats here.*/
599 /* Register for each Pipeline Stage */
600 for (int stage_num
=0; stage_num
< ThePipeline::NumStages
; stage_num
++) {
601 pipelineStage
[stage_num
]->regStats();
604 /* Register any of the InOrderCPU's stats here.*/
606 .name(name() + ".instsPerContextSwitch")
607 .desc("Instructions Committed Per Context Switch")
608 .prereq(instsPerCtxtSwitch
);
611 .name(name() + ".contextSwitches")
612 .desc("Number of context switches");
615 .name(name() + ".comLoads")
616 .desc("Number of Load instructions committed");
619 .name(name() + ".comStores")
620 .desc("Number of Store instructions committed");
623 .name(name() + ".comBranches")
624 .desc("Number of Branches instructions committed");
627 .name(name() + ".comNops")
628 .desc("Number of Nop instructions committed");
631 .name(name() + ".comNonSpec")
632 .desc("Number of Non-Speculative instructions committed");
635 .name(name() + ".comInts")
636 .desc("Number of Integer instructions committed");
639 .name(name() + ".comFloats")
640 .desc("Number of Floating Point instructions committed");
643 .name(name() + ".timesIdled")
644 .desc("Number of times that the entire CPU went into an idle state and"
645 " unscheduled itself")
649 .name(name() + ".idleCycles")
650 .desc("Number of cycles cpu's stages were not processed");
653 .name(name() + ".runCycles")
654 .desc("Number of cycles cpu stages are processed.");
657 .name(name() + ".activity")
658 .desc("Percentage of cycles cpu is active")
660 activity
= (runCycles
/ numCycles
) * 100;
664 .name(name() + ".threadCycles")
665 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
668 .name(name() + ".smtCycles")
669 .desc("Total number of cycles that the CPU was in SMT-mode");
673 .name(name() + ".committedInsts")
674 .desc("Number of Instructions committed (Per-Thread)");
678 .name(name() + ".committedOps")
679 .desc("Number of Ops committed (Per-Thread)");
683 .name(name() + ".smtCommittedInsts")
684 .desc("Number of SMT Instructions committed (Per-Thread)");
687 .name(name() + ".committedInsts_total")
688 .desc("Number of Instructions committed (Total)");
691 .name(name() + ".cpi")
692 .desc("CPI: Cycles Per Instruction (Per-Thread)")
694 cpi
= numCycles
/ committedInsts
;
697 .name(name() + ".smt_cpi")
698 .desc("CPI: Total SMT-CPI")
700 smtCpi
= smtCycles
/ smtCommittedInsts
;
703 .name(name() + ".cpi_total")
704 .desc("CPI: Total CPI of All Threads")
706 totalCpi
= numCycles
/ totalCommittedInsts
;
709 .name(name() + ".ipc")
710 .desc("IPC: Instructions Per Cycle (Per-Thread)")
712 ipc
= committedInsts
/ numCycles
;
715 .name(name() + ".smt_ipc")
716 .desc("IPC: Total SMT-IPC")
718 smtIpc
= smtCommittedInsts
/ smtCycles
;
721 .name(name() + ".ipc_total")
722 .desc("IPC: Total IPC of All Threads")
724 totalIpc
= totalCommittedInsts
/ numCycles
;
733 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
737 checkForInterrupts();
739 bool pipes_idle
= true;
740 //Tick each of the stages
741 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
742 pipelineStage
[stNum
]->tick();
744 pipes_idle
= pipes_idle
&& pipelineStage
[stNum
]->idle
;
752 // Now advance the time buffers one tick
753 timeBuffer
.advance();
754 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
755 stageQueue
[sqNum
]->advance();
757 activityRec
.advance();
759 // Any squashed events, or insts then remove them now
760 cleanUpRemovedEvents();
761 cleanUpRemovedInsts();
763 // Re-schedule CPU for this cycle
764 if (!tickEvent
.scheduled()) {
765 if (_status
== SwitchedOut
) {
767 lastRunningCycle
= curCycle();
768 } else if (!activityRec
.active()) {
769 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
770 lastRunningCycle
= curCycle();
773 //Tick next_tick = curTick() + cycles(1);
774 //tickEvent.schedule(next_tick);
775 schedule(&tickEvent
, clockEdge(Cycles(1)));
776 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n",
777 clockEdge(Cycles(1)));
782 updateThreadPriority();
791 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
792 // Set noSquashFromTC so that the CPU doesn't squash when initially
793 // setting up registers.
794 thread
[tid
]->noSquashFromTC
= true;
795 // Initialise the ThreadContext's memory proxies
796 thread
[tid
]->initMemProxies(thread
[tid
]->getTC());
799 if (FullSystem
&& !params()->switched_out
) {
800 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
801 ThreadContext
*src_tc
= threadContexts
[tid
];
802 TheISA::initCPU(src_tc
, src_tc
->contextId());
806 // Clear noSquashFromTC.
807 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
808 thread
[tid
]->noSquashFromTC
= false;
810 // Call Initializiation Routine for Resource Pool
815 InOrderCPU::verifyMemoryMode() const
817 if (!system
->isTimingMode()) {
818 fatal("The in-order CPU requires the memory system to be in "
824 InOrderCPU::hwrei(ThreadID tid
)
826 #if THE_ISA == ALPHA_ISA
827 // Need to clear the lock flag upon returning from an interrupt.
828 setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG
, false, tid
);
830 thread
[tid
]->kernelStats
->hwrei();
831 // FIXME: XXX check for interrupts? XXX
839 InOrderCPU::simPalCheck(int palFunc
, ThreadID tid
)
841 #if THE_ISA == ALPHA_ISA
842 if (this->thread
[tid
]->kernelStats
)
843 this->thread
[tid
]->kernelStats
->callpal(palFunc
,
844 this->threadContexts
[tid
]);
849 if (--System::numSystemsRunning
== 0)
850 exitSimLoop("all cpus halted");
855 if (this->system
->breakpoint())
864 InOrderCPU::checkForInterrupts()
866 for (int i
= 0; i
< threadContexts
.size(); i
++) {
867 ThreadContext
*tc
= threadContexts
[i
];
869 if (interrupts
->checkInterrupts(tc
)) {
870 Fault interrupt
= interrupts
->getInterrupt(tc
);
872 if (interrupt
!= NoFault
) {
873 DPRINTF(Interrupt
, "Processing Intterupt for [tid:%i].\n",
876 ThreadID tid
= tc
->threadId();
877 interrupts
->updateIntrInfo(tc
);
879 // Squash from Last Stage in Pipeline
880 unsigned last_stage
= NumStages
- 1;
881 dummyTrapInst
[tid
]->squashingStage
= last_stage
;
882 pipelineStage
[last_stage
]->setupSquash(dummyTrapInst
[tid
],
885 // By default, setupSquash will always squash from stage + 1
886 pipelineStage
[BackEndStartStage
- 1]->setupSquash(dummyTrapInst
[tid
],
889 // Schedule Squash Through-out Resource Pool
890 resPool
->scheduleEvent(
891 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
,
892 dummyTrapInst
[tid
], Cycles(0));
894 // Finally, Setup Trap to happen at end of cycle
895 trapContext(interrupt
, tid
, dummyTrapInst
[tid
]);
902 InOrderCPU::getInterrupts()
904 // Check if there are any outstanding interrupts
905 return interrupts
->getInterrupt(threadContexts
[0]);
909 InOrderCPU::processInterrupts(Fault interrupt
)
911 // Check for interrupts here. For now can copy the code that
912 // exists within isa_fullsys_traits.hh. Also assume that thread 0
913 // is the one that handles the interrupts.
914 // @todo: Possibly consolidate the interrupt checking code.
915 // @todo: Allow other threads to handle interrupts.
917 assert(interrupt
!= NoFault
);
918 interrupts
->updateIntrInfo(threadContexts
[0]);
920 DPRINTF(InOrderCPU
, "Interrupt %s being handled\n", interrupt
->name());
922 // Note: Context ID ok here? Impl. of FS mode needs to revisit this
923 trap(interrupt
, threadContexts
[0]->contextId(), dummyBufferInst
);
927 InOrderCPU::trapContext(Fault fault
, ThreadID tid
, DynInstPtr inst
,
930 scheduleCpuEvent(Trap
, fault
, tid
, inst
, delay
);
931 trapPending
[tid
] = true;
935 InOrderCPU::trap(Fault fault
, ThreadID tid
, DynInstPtr inst
)
937 fault
->invoke(tcBase(tid
), inst
->staticInst
);
938 removePipelineStalls(tid
);
942 InOrderCPU::squashFromMemStall(DynInstPtr inst
, ThreadID tid
,
945 scheduleCpuEvent(SquashFromMemStall
, NoFault
, tid
, inst
, delay
);
950 InOrderCPU::squashDueToMemStall(int stage_num
, InstSeqNum seq_num
,
953 DPRINTF(InOrderCPU
, "Squashing Pipeline Stages Due to Memory Stall...\n");
955 // Squash all instructions in each stage including
956 // instruction that caused the squash (seq_num - 1)
957 // NOTE: The stage bandwidth needs to be cleared so thats why
958 // the stalling instruction is squashed as well. The stalled
959 // instruction is previously placed in another intermediate buffer
960 // while it's stall is being handled.
961 InstSeqNum squash_seq_num
= seq_num
- 1;
963 for (int stNum
=stage_num
; stNum
>= 0 ; stNum
--) {
964 pipelineStage
[stNum
]->squashDueToMemStall(squash_seq_num
, tid
);
969 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
970 ThreadID tid
, DynInstPtr inst
,
971 Cycles delay
, CPUEventPri event_pri
)
973 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, inst
,
976 Tick sked_tick
= clockEdge(delay
);
977 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
978 eventNames
[c_event
], curTick() + delay
, tid
);
979 schedule(cpu_event
, sked_tick
);
981 // Broadcast event to the Resource Pool
982 // Need to reset tid just in case this is a dummy instruction
984 // @todo: Is this really right? Should the delay not be passed on?
985 resPool
->scheduleEvent(c_event
, inst
, Cycles(0), 0, tid
);
989 InOrderCPU::isThreadActive(ThreadID tid
)
991 list
<ThreadID
>::iterator isActive
=
992 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
994 return (isActive
!= activeThreads
.end());
998 InOrderCPU::isThreadReady(ThreadID tid
)
1000 list
<ThreadID
>::iterator isReady
=
1001 std::find(readyThreads
.begin(), readyThreads
.end(), tid
);
1003 return (isReady
!= readyThreads
.end());
1007 InOrderCPU::isThreadSuspended(ThreadID tid
)
1009 list
<ThreadID
>::iterator isSuspended
=
1010 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
1012 return (isSuspended
!= suspendedThreads
.end());
1016 InOrderCPU::activateNextReadyThread()
1018 if (readyThreads
.size() >= 1) {
1019 ThreadID ready_tid
= readyThreads
.front();
1021 // Activate in Pipeline
1022 activateThread(ready_tid
);
1024 // Activate in Resource Pool
1025 resPool
->activateThread(ready_tid
);
1027 list
<ThreadID
>::iterator ready_it
=
1028 std::find(readyThreads
.begin(), readyThreads
.end(), ready_tid
);
1029 readyThreads
.erase(ready_it
);
1032 "Attempting to activate new thread, but No Ready Threads to"
1035 "Unable to switch to next active thread.\n");
1040 InOrderCPU::activateThread(ThreadID tid
)
1042 if (isThreadSuspended(tid
)) {
1044 "Removing [tid:%i] from suspended threads list.\n", tid
);
1046 list
<ThreadID
>::iterator susp_it
=
1047 std::find(suspendedThreads
.begin(), suspendedThreads
.end(),
1049 suspendedThreads
.erase(susp_it
);
1052 if (threadModel
== SwitchOnCacheMiss
&&
1053 numActiveThreads() == 1) {
1055 "Ignoring activation of [tid:%i], since [tid:%i] is "
1056 "already running.\n", tid
, activeThreadId());
1058 DPRINTF(InOrderCPU
,"Placing [tid:%i] on ready threads list\n",
1061 readyThreads
.push_back(tid
);
1063 } else if (!isThreadActive(tid
)) {
1065 "Adding [tid:%i] to active threads list.\n", tid
);
1066 activeThreads
.push_back(tid
);
1068 activateThreadInPipeline(tid
);
1070 thread
[tid
]->lastActivate
= curTick();
1072 tcBase(tid
)->setStatus(ThreadContext::Active
);
1081 InOrderCPU::activateThreadInPipeline(ThreadID tid
)
1083 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
1084 pipelineStage
[stNum
]->activateThread(tid
);
1089 InOrderCPU::deactivateContext(ThreadID tid
, Cycles delay
)
1091 DPRINTF(InOrderCPU
,"[tid:%i]: Deactivating ...\n", tid
);
1093 scheduleCpuEvent(DeactivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1095 // Be sure to signal that there's some activity so the CPU doesn't
1096 // deschedule itself.
1097 activityRec
.activity();
1103 InOrderCPU::deactivateThread(ThreadID tid
)
1105 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
1107 if (isThreadActive(tid
)) {
1108 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
1110 list
<ThreadID
>::iterator thread_it
=
1111 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
1113 removePipelineStalls(*thread_it
);
1115 activeThreads
.erase(thread_it
);
1117 // Ideally, this should be triggered from the
1118 // suspendContext/Thread functions
1119 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1122 assert(!isThreadActive(tid
));
1126 InOrderCPU::removePipelineStalls(ThreadID tid
)
1128 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
1131 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
1132 pipelineStage
[stNum
]->removeStalls(tid
);
1138 InOrderCPU::updateThreadPriority()
1140 if (activeThreads
.size() > 1)
1142 //DEFAULT TO ROUND ROBIN SCHEME
1143 //e.g. Move highest priority to end of thread list
1144 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
1146 unsigned high_thread
= *list_begin
;
1148 activeThreads
.erase(list_begin
);
1150 activeThreads
.push_back(high_thread
);
1155 InOrderCPU::tickThreadStats()
1157 /** Keep track of cycles that each thread is active */
1158 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
1159 while (thread_it
!= activeThreads
.end()) {
1160 threadCycles
[*thread_it
]++;
1164 // Keep track of cycles where SMT is active
1165 if (activeThreads
.size() > 1) {
1171 InOrderCPU::activateContext(ThreadID tid
, Cycles delay
)
1173 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
1176 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1178 // Be sure to signal that there's some activity so the CPU doesn't
1179 // deschedule itself.
1180 activityRec
.activity();
1186 InOrderCPU::activateNextReadyContext(Cycles delay
)
1188 DPRINTF(InOrderCPU
,"Activating next ready thread\n");
1190 scheduleCpuEvent(ActivateNextReadyThread
, NoFault
, 0/*tid*/, dummyInst
[0],
1191 delay
, ActivateNextReadyThread_Pri
);
1193 // Be sure to signal that there's some activity so the CPU doesn't
1194 // deschedule itself.
1195 activityRec
.activity();
1201 InOrderCPU::haltContext(ThreadID tid
)
1203 DPRINTF(InOrderCPU
, "[tid:%i]: Calling Halt Context...\n", tid
);
1205 scheduleCpuEvent(HaltThread
, NoFault
, tid
, dummyInst
[tid
]);
1207 activityRec
.activity();
1211 InOrderCPU::haltThread(ThreadID tid
)
1213 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Halted Threads List...\n", tid
);
1214 deactivateThread(tid
);
1215 squashThreadInPipeline(tid
);
1216 haltedThreads
.push_back(tid
);
1218 tcBase(tid
)->setStatus(ThreadContext::Halted
);
1220 if (threadModel
== SwitchOnCacheMiss
) {
1221 activateNextReadyContext();
1226 InOrderCPU::suspendContext(ThreadID tid
)
1228 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, dummyInst
[tid
]);
1232 InOrderCPU::suspendThread(ThreadID tid
)
1234 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Suspended Threads List...\n",
1236 deactivateThread(tid
);
1237 suspendedThreads
.push_back(tid
);
1238 thread
[tid
]->lastSuspend
= curTick();
1240 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1244 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
1246 //Squash all instructions in each stage
1247 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
1248 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
1253 InOrderCPU::getPipeStage(int stage_num
)
1255 return pipelineStage
[stage_num
];
1260 InOrderCPU::flattenRegIdx(RegIndex reg_idx
, RegClass
®_type
, ThreadID tid
)
1264 reg_type
= regIdxToClass(reg_idx
, &rel_idx
);
1268 return isa
[tid
]->flattenIntIndex(rel_idx
);
1271 return isa
[tid
]->flattenFloatIndex(rel_idx
);
1277 panic("register %d out of range\n", reg_idx
);
1282 InOrderCPU::readIntReg(RegIndex reg_idx
, ThreadID tid
)
1284 DPRINTF(IntRegs
, "[tid:%i]: Reading Int. Reg %i as %x\n",
1285 tid
, reg_idx
, intRegs
[tid
][reg_idx
]);
1287 return intRegs
[tid
][reg_idx
];
1291 InOrderCPU::readFloatReg(RegIndex reg_idx
, ThreadID tid
)
1293 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1294 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1296 return floatRegs
.f
[tid
][reg_idx
];
1300 InOrderCPU::readFloatRegBits(RegIndex reg_idx
, ThreadID tid
)
1302 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1303 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1305 return floatRegs
.i
[tid
][reg_idx
];
1309 InOrderCPU::setIntReg(RegIndex reg_idx
, uint64_t val
, ThreadID tid
)
1311 if (reg_idx
== TheISA::ZeroReg
) {
1312 DPRINTF(IntRegs
, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1313 "(Int. Reg %i) to %x\n", tid
, reg_idx
, val
);
1316 DPRINTF(IntRegs
, "[tid:%i]: Setting Int. Reg %i to %x\n",
1319 intRegs
[tid
][reg_idx
] = val
;
1325 InOrderCPU::setFloatReg(RegIndex reg_idx
, FloatReg val
, ThreadID tid
)
1327 floatRegs
.f
[tid
][reg_idx
] = val
;
1328 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1331 floatRegs
.i
[tid
][reg_idx
],
1332 floatRegs
.f
[tid
][reg_idx
]);
1337 InOrderCPU::setFloatRegBits(RegIndex reg_idx
, FloatRegBits val
, ThreadID tid
)
1339 floatRegs
.i
[tid
][reg_idx
] = val
;
1340 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1343 floatRegs
.i
[tid
][reg_idx
],
1344 floatRegs
.f
[tid
][reg_idx
]);
1348 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
1350 // If Default value is set, then retrieve target thread
1351 if (tid
== InvalidThreadID
) {
1352 tid
= TheISA::getTargetThread(tcBase(tid
));
1357 switch (regIdxToClass(reg_idx
, &rel_idx
)) {
1359 // Integer Register File
1360 return readIntReg(rel_idx
, tid
);
1363 // Float Register File
1364 return readFloatRegBits(rel_idx
, tid
);
1367 return readMiscReg(rel_idx
, tid
); // Misc. Register File
1370 panic("register %d out of range\n", reg_idx
);
1375 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
1378 // If Default value is set, then retrieve target thread
1379 if (tid
== InvalidThreadID
) {
1380 tid
= TheISA::getTargetThread(tcBase(tid
));
1385 switch (regIdxToClass(reg_idx
, &rel_idx
)) {
1387 setIntReg(rel_idx
, val
, tid
);
1391 setFloatRegBits(rel_idx
, val
, tid
);
1395 setMiscReg(rel_idx
, val
, tid
); // Misc. Register File
1401 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1403 return isa
[tid
]->readMiscRegNoEffect(misc_reg
);
1407 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
1409 return isa
[tid
]->readMiscReg(misc_reg
, tcBase(tid
));
1413 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1415 isa
[tid
]->setMiscRegNoEffect(misc_reg
, val
);
1419 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1421 isa
[tid
]->setMiscReg(misc_reg
, val
, tcBase(tid
));
1426 InOrderCPU::addInst(DynInstPtr inst
)
1428 ThreadID tid
= inst
->readTid();
1430 instList
[tid
].push_back(inst
);
1432 return --(instList
[tid
].end());
1436 InOrderCPU::findInst(InstSeqNum seq_num
, ThreadID tid
)
1438 ListIt it
= instList
[tid
].begin();
1439 ListIt end
= instList
[tid
].end();
1442 if ((*it
)->seqNum
== seq_num
)
1444 else if ((*it
)->seqNum
> seq_num
)
1450 return instList
[tid
].end();
1454 InOrderCPU::updateContextSwitchStats()
1456 // Set Average Stat Here, then reset to 0
1457 instsPerCtxtSwitch
= instsPerSwitch
;
1463 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1465 // Set the nextPC to be fetched if this is the last instruction
1468 // This contributes to the precise state of the CPU
1469 // which can be used when restoring a thread to the CPU after after any
1470 // type of context switching activity (fork, exception, etc.)
1471 TheISA::PCState comm_pc
= inst
->pcState();
1472 lastCommittedPC
[tid
] = comm_pc
;
1473 TheISA::advancePC(comm_pc
, inst
->staticInst
);
1474 pcState(comm_pc
, tid
);
1476 //@todo: may be unnecessary with new-ISA-specific branch handling code
1477 if (inst
->isControl()) {
1478 thread
[tid
]->lastGradIsBranch
= true;
1479 thread
[tid
]->lastBranchPC
= inst
->pcState();
1480 TheISA::advancePC(thread
[tid
]->lastBranchPC
, inst
->staticInst
);
1482 thread
[tid
]->lastGradIsBranch
= false;
1486 // Finalize Trace Data For Instruction
1487 if (inst
->traceData
) {
1488 //inst->traceData->setCycle(curTick());
1489 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1490 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1491 inst
->traceData
->dump();
1492 delete inst
->traceData
;
1493 inst
->traceData
= NULL
;
1496 // Increment active thread's instruction count
1499 // Increment thread-state's instruction count
1500 thread
[tid
]->numInst
++;
1501 thread
[tid
]->numOp
++;
1503 // Increment thread-state's instruction stats
1504 thread
[tid
]->numInsts
++;
1505 thread
[tid
]->numOps
++;
1507 // Count committed insts per thread stats
1508 if (!inst
->isMicroop() || inst
->isLastMicroop()) {
1509 committedInsts
[tid
]++;
1511 // Count total insts committed stat
1512 totalCommittedInsts
++;
1515 committedOps
[tid
]++;
1517 // Count SMT-committed insts per thread stat
1518 if (numActiveThreads() > 1) {
1519 if (!inst
->isMicroop() || inst
->isLastMicroop())
1520 smtCommittedInsts
[tid
]++;
1523 // Instruction-Mix Stats
1524 if (inst
->isLoad()) {
1526 } else if (inst
->isStore()) {
1528 } else if (inst
->isControl()) {
1530 } else if (inst
->isNop()) {
1532 } else if (inst
->isNonSpeculative()) {
1534 } else if (inst
->isInteger()) {
1536 } else if (inst
->isFloating()) {
1540 // Check for instruction-count-based events.
1541 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numOp
);
1543 // Finally, remove instruction from CPU
1547 // currently unused function, but substitute repetitive code w/this function
1550 InOrderCPU::addToRemoveList(DynInstPtr inst
)
1552 removeInstsThisCycle
= true;
1553 if (!inst
->isRemoveList()) {
1554 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1555 "[sn:%lli] to remove list\n",
1556 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1557 inst
->setRemoveList();
1558 removeList
.push(inst
->getInstListIt());
1560 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1561 "[sn:%lli], already remove list\n",
1562 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1568 InOrderCPU::removeInst(DynInstPtr inst
)
1570 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %s "
1572 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1574 removeInstsThisCycle
= true;
1576 // Remove the instruction.
1577 if (!inst
->isRemoveList()) {
1578 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1579 "[sn:%lli] to remove list\n",
1580 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1581 inst
->setRemoveList();
1582 removeList
.push(inst
->getInstListIt());
1584 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1585 "[sn:%lli], already on remove list\n",
1586 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1592 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1594 //assert(!instList[tid].empty());
1596 removeInstsThisCycle
= true;
1598 ListIt inst_iter
= instList
[tid
].end();
1602 DPRINTF(InOrderCPU
, "Squashing instructions from CPU instruction "
1603 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1604 tid
, seq_num
, (*inst_iter
)->seqNum
);
1606 while ((*inst_iter
)->seqNum
> seq_num
) {
1608 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1610 squashInstIt(inst_iter
, tid
);
1621 InOrderCPU::squashInstIt(const ListIt inst_it
, ThreadID tid
)
1623 DynInstPtr inst
= (*inst_it
);
1624 if (inst
->threadNumber
== tid
) {
1625 DPRINTF(InOrderCPU
, "Squashing instruction, "
1626 "[tid:%i] [sn:%lli] PC %s\n",
1631 inst
->setSquashed();
1632 archRegDepMap
[tid
].remove(inst
);
1634 if (!inst
->isRemoveList()) {
1635 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1636 "[sn:%lli] to remove list\n",
1637 inst
->threadNumber
, inst
->pcState(),
1639 inst
->setRemoveList();
1640 removeList
.push(inst_it
);
1642 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i]"
1643 " PC %s [sn:%lli], already on remove list\n",
1644 inst
->threadNumber
, inst
->pcState(),
1654 InOrderCPU::cleanUpRemovedInsts()
1656 while (!removeList
.empty()) {
1657 DPRINTF(InOrderCPU
, "Removing instruction, "
1658 "[tid:%i] [sn:%lli] PC %s\n",
1659 (*removeList
.front())->threadNumber
,
1660 (*removeList
.front())->seqNum
,
1661 (*removeList
.front())->pcState());
1663 DynInstPtr inst
= *removeList
.front();
1664 ThreadID tid
= inst
->threadNumber
;
1666 // Remove From Register Dependency Map, If Necessary
1667 // archRegDepMap[tid].remove(inst);
1669 // Clear if Non-Speculative
1670 if (inst
->staticInst
&&
1671 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1672 nonSpecInstActive
[tid
] == true) {
1673 nonSpecInstActive
[tid
] = false;
1676 inst
->onInstList
= false;
1678 instList
[tid
].erase(removeList
.front());
1683 removeInstsThisCycle
= false;
1687 InOrderCPU::cleanUpRemovedEvents()
1689 while (!cpuEventRemoveList
.empty()) {
1690 Event
*cpu_event
= cpuEventRemoveList
.front();
1691 cpuEventRemoveList
.pop();
1698 InOrderCPU::dumpInsts()
1702 ListIt inst_list_it
= instList
[0].begin();
1704 cprintf("Dumping Instruction List\n");
1706 while (inst_list_it
!= instList
[0].end()) {
1707 cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1709 num
, (*inst_list_it
)->pcState(),
1710 (*inst_list_it
)->threadNumber
,
1711 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1712 (*inst_list_it
)->isSquashed());
1719 InOrderCPU::wakeCPU()
1721 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1722 DPRINTF(Activity
, "CPU already running.\n");
1726 DPRINTF(Activity
, "Waking up CPU\n");
1728 Tick extra_cycles
= curCycle() - lastRunningCycle
;
1729 if (extra_cycles
!= 0)
1732 idleCycles
+= extra_cycles
;
1733 for (int stage_num
= 0; stage_num
< NumStages
; stage_num
++) {
1734 pipelineStage
[stage_num
]->idleCycles
+= extra_cycles
;
1737 numCycles
+= extra_cycles
;
1739 schedule(&tickEvent
, clockEdge());
1742 // Lots of copied full system code...place into BaseCPU class?
1744 InOrderCPU::wakeup()
1746 if (thread
[0]->status() != ThreadContext::Suspended
)
1751 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1752 threadContexts
[0]->activate();
1756 InOrderCPU::syscallContext(Fault fault
, ThreadID tid
, DynInstPtr inst
,
1759 // Syscall must be non-speculative, so squash from last stage
1760 unsigned squash_stage
= NumStages
- 1;
1761 inst
->setSquashInfo(squash_stage
);
1763 // Squash In Pipeline Stage
1764 pipelineStage
[squash_stage
]->setupSquash(inst
, tid
);
1766 // Schedule Squash Through-out Resource Pool
1767 resPool
->scheduleEvent(
1768 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
, inst
,
1770 scheduleCpuEvent(Syscall
, fault
, tid
, inst
, delay
, Syscall_Pri
);
1774 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1776 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1778 DPRINTF(Activity
,"Activity: syscall() called.\n");
1780 // Temporarily increase this by one to account for the syscall
1782 ++(this->thread
[tid
]->funcExeInst
);
1784 // Execute the actual syscall.
1785 this->thread
[tid
]->syscall(callnum
);
1787 // Decrease funcExeInst by one as the normal commit will handle
1789 --(this->thread
[tid
]->funcExeInst
);
1791 // Clear Non-Speculative Block Variable
1792 nonSpecInstActive
[tid
] = false;
1796 InOrderCPU::getITBPtr()
1798 CacheUnit
*itb_res
= resPool
->getInstUnit();
1799 return itb_res
->tlb();
1804 InOrderCPU::getDTBPtr()
1806 return resPool
->getDataUnit()->tlb();
1810 InOrderCPU::getDecoderPtr(unsigned tid
)
1812 return resPool
->getInstUnit()->decoder
[tid
];
1816 InOrderCPU::read(DynInstPtr inst
, Addr addr
,
1817 uint8_t *data
, unsigned size
, unsigned flags
)
1819 return resPool
->getDataUnit()->read(inst
, addr
, data
, size
, flags
);
1823 InOrderCPU::write(DynInstPtr inst
, uint8_t *data
, unsigned size
,
1824 Addr addr
, unsigned flags
, uint64_t *write_res
)
1826 return resPool
->getDataUnit()->write(inst
, data
, size
, addr
, flags
,