src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <algorithm>
  33
  34 #include "arch/utility.hh"
  35 #include "base/bigint.hh"
  36 #include "config/full_system.hh"
  37 #include "config/the_isa.hh"
  38 #include "cpu/inorder/resources/resource_list.hh"
  39 #include "cpu/inorder/cpu.hh"
  40 #include "cpu/inorder/first_stage.hh"
  41 #include "cpu/inorder/inorder_dyn_inst.hh"
  42 #include "cpu/inorder/pipeline_traits.hh"
  43 #include "cpu/inorder/resource_pool.hh"
  44 #include "cpu/inorder/thread_context.hh"
  45 #include "cpu/inorder/thread_state.hh"
  46 #include "cpu/activity.hh"
  47 #include "cpu/base.hh"
  48 #include "cpu/exetrace.hh"
  49 #include "cpu/simple_thread.hh"
  50 #include "cpu/thread_context.hh"
  51 #include "debug/Activity.hh"
  52 #include "debug/InOrderCPU.hh"
  53 #include "debug/RefCount.hh"
  54 #include "debug/SkedCache.hh"
  55 #include "mem/translating_port.hh"
  56 #include "params/InOrderCPU.hh"
  57 #include "sim/process.hh"
  58 #include "sim/stat_control.hh"
  59
  60 #if FULL_SYSTEM
  61 #include "cpu/quiesce_event.hh"
  62 #include "sim/system.hh"
  63 #endif
  64
  65 #if THE_ISA == ALPHA_ISA
  66 #include "arch/alpha/osfpal.hh"
  67 #endif
  68
  69 using namespace std;
  70 using namespace TheISA;
  71 using namespace ThePipeline;
  72
  73 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
  74   : Event(CPU_Tick_Pri), cpu(c)
  75 { }
  76
  77
  78 void
  79 InOrderCPU::TickEvent::process()
  80 {
  81     cpu->tick();
  82 }
  83
  84
  85 const char *
  86 InOrderCPU::TickEvent::description()
  87 {
  88     return "InOrderCPU tick event";
  89 }
  90
  91 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
  92                                Fault fault, ThreadID _tid, DynInstPtr inst,
  93                                CPUEventPri event_pri)
  94     : Event(event_pri), cpu(_cpu)
  95 {
  96     setEvent(e_type, fault, _tid, inst);
  97 }
  98
  99
 100 std::string InOrderCPU::eventNames[NumCPUEvents] =
 101 {
 102     "ActivateThread",
 103     "ActivateNextReadyThread",
 104     "DeactivateThread",
 105     "HaltThread",
 106     "SuspendThread",
 107     "Trap",
 108     "Syscall",
 109     "SquashFromMemStall",
 110     "UpdatePCs"
 111 };
 112
 113 void
 114 InOrderCPU::CPUEvent::process()
 115 {
 116     switch (cpuEventType)
 117     {
 118       case ActivateThread:
 119         cpu->activateThread(tid);
 120         cpu->resPool->activateThread(tid);
 121         break;
 122
 123       case ActivateNextReadyThread:
 124         cpu->activateNextReadyThread();
 125         break;
 126
 127       case DeactivateThread:
 128         cpu->deactivateThread(tid);
 129         cpu->resPool->deactivateThread(tid);
 130         break;
 131
 132       case HaltThread:
 133         cpu->haltThread(tid);
 134         cpu->resPool->deactivateThread(tid);
 135         break;
 136
 137       case SuspendThread:
 138         cpu->suspendThread(tid);
 139         cpu->resPool->suspendThread(tid);
 140         break;
 141
 142       case SquashFromMemStall:
 143         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 144         cpu->resPool->squashDueToMemStall(inst, inst->squashingStage,
 145                                           inst->seqNum, tid);
 146         break;
 147
 148       case Trap:
 149         DPRINTF(InOrderCPU, "Trapping CPU\n");
 150         cpu->trap(fault, tid, inst);
 151         cpu->resPool->trap(fault, tid, inst);
 152         break;
 153
 154 #if !FULL_SYSTEM
 155       case Syscall:
 156         cpu->syscall(inst->syscallNum, tid);
 157         cpu->resPool->trap(fault, tid, inst);
 158         break;
 159 #endif
 160       default:
 161         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 162     }
 163
 164     cpu->cpuEventRemoveList.push(this);
 165 }
 166
 167
 168
 169 const char *
 170 InOrderCPU::CPUEvent::description()
 171 {
 172     return "InOrderCPU event";
 173 }
 174
 175 void
 176 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 177 {
 178     assert(!scheduled() || squashed());
 179     cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
 180 }
 181
 182 void
 183 InOrderCPU::CPUEvent::unscheduleEvent()
 184 {
 185     if (scheduled())
 186         squash();
 187 }
 188
 189 InOrderCPU::InOrderCPU(Params *params)
 190     : BaseCPU(params),
 191       cpu_id(params->cpu_id),
 192       coreType("default"),
 193       _status(Idle),
 194       tickEvent(this),
 195       stageWidth(params->stageWidth),
 196       timeBuffer(2 , 2),
 197       removeInstsThisCycle(false),
 198       activityRec(params->name, NumStages, 10, params->activity),
 199       stCondFails(0),
 200 #if FULL_SYSTEM
 201       system(params->system),
 202 #endif // FULL_SYSTEM
 203 #ifdef DEBUG
 204       cpuEventNum(0),
 205       resReqCount(0),
 206 #endif // DEBUG
 207       drainCount(0),
 208       deferRegistration(false/*params->deferRegistration*/),
 209       stageTracing(params->stageTracing),
 210       lastRunningCycle(0),
 211       instsPerSwitch(0)
 212 {
 213     ThreadID active_threads;
 214     cpu_params = params;
 215
 216     resPool = new ResourcePool(this, params);
 217
 218     // Resize for Multithreading CPUs
 219     thread.resize(numThreads);
 220
 221 #if FULL_SYSTEM
 222     active_threads = 1;
 223 #else
 224     active_threads = params->workload.size();
 225
 226     if (active_threads > MaxThreads) {
 227         panic("Workload Size too large. Increase the 'MaxThreads'"
 228               "in your InOrder implementation or "
 229               "edit your workload size.");
 230     }
 231
 232
 233     if (active_threads > 1) {
 234         threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 235
 236         if (threadModel == SMT) {
 237             DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 238         } else if (threadModel == SwitchOnCacheMiss) {
 239             DPRINTF(InOrderCPU, "Setting Thread Model to "
 240                     "Switch On Cache Miss\n");
 241         }
 242
 243     } else {
 244         threadModel = Single;
 245     }
 246
 247
 248
 249 #endif
 250
 251     // Bind the fetch & data ports from the resource pool.
 252     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
 253     if (fetchPortIdx == 0) {
 254         fatal("Unable to find port to fetch instructions from.\n");
 255     }
 256
 257     dataPortIdx = resPool->getPortIdx(params->dataMemPort);
 258     if (dataPortIdx == 0) {
 259         fatal("Unable to find port for data.\n");
 260     }
 261
 262     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 263         pc[tid].set(0);
 264         lastCommittedPC[tid].set(0);
 265
 266 #if FULL_SYSTEM
 267         // SMT is not supported in FS mode yet.
 268         assert(numThreads == 1);
 269         thread[tid] = new Thread(this, 0);
 270 #else
 271         if (tid < (ThreadID)params->workload.size()) {
 272             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 273                     tid, params->workload[tid]->prog_fname);
 274             thread[tid] =
 275                 new Thread(this, tid, params->workload[tid]);
 276         } else {
 277             //Allocate Empty thread so M5 can use later
 278             //when scheduling threads to CPU
 279             Process* dummy_proc = params->workload[0];
 280             thread[tid] = new Thread(this, tid, dummy_proc);
 281         }
 282
 283         // Eventually set this with parameters...
 284         asid[tid] = tid;
 285 #endif
 286
 287         // Setup the TC that will serve as the interface to the threads/CPU.
 288         InOrderThreadContext *tc = new InOrderThreadContext;
 289         tc->cpu = this;
 290         tc->thread = thread[tid];
 291
 292 #if FULL_SYSTEM
 293         // Setup quiesce event.
 294         this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
 295 #endif
 296
 297         // Give the thread the TC.
 298         thread[tid]->tc = tc;
 299         thread[tid]->setFuncExeInst(0);
 300         globalSeqNum[tid] = 1;
 301
 302         // Add the TC to the CPU's list of TC's.
 303         this->threadContexts.push_back(tc);
 304     }
 305
 306     // Initialize TimeBuffer Stage Queues
 307     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 308         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 309         stageQueue[stNum]->id(stNum);
 310     }
 311
 312
 313     // Set Up Pipeline Stages
 314     for (int stNum=0; stNum < NumStages; stNum++) {
 315         if (stNum == 0)
 316             pipelineStage[stNum] = new FirstStage(params, stNum);
 317         else
 318             pipelineStage[stNum] = new PipelineStage(params, stNum);
 319
 320         pipelineStage[stNum]->setCPU(this);
 321         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 322         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 323
 324         // Take Care of 1st/Nth stages
 325         if (stNum > 0)
 326             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 327         if (stNum < NumStages - 1)
 328             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 329     }
 330
 331     // Initialize thread specific variables
 332     for (ThreadID tid = 0; tid < numThreads; tid++) {
 333         archRegDepMap[tid].setCPU(this);
 334
 335         nonSpecInstActive[tid] = false;
 336         nonSpecSeqNum[tid] = 0;
 337
 338         squashSeqNum[tid] = MaxAddr;
 339         lastSquashCycle[tid] = 0;
 340
 341         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 342         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 343         isa[tid].clear();
 344
 345         // Define dummy instructions and resource requests to be used.
 346         dummyInst[tid] = new InOrderDynInst(this,
 347                                             thread[tid],
 348                                             0,
 349                                             tid,
 350                                             asid[tid]);
 351
 352         dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
 353     }
 354
 355     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 356     dummyReqInst->setSquashed();
 357     dummyReqInst->resetInstCount();
 358
 359     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 360     dummyBufferInst->setSquashed();
 361     dummyBufferInst->resetInstCount();
 362
 363     endOfSkedIt = skedCache.end();
 364     frontEndSked = createFrontEndSked();
 365
 366     lastRunningCycle = curTick();
 367
 368     lockAddr = 0;
 369     lockFlag = false;
 370
 371     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 372     scheduleTickEvent(0);
 373 }
 374
 375 InOrderCPU::~InOrderCPU()
 376 {
 377     delete resPool;
 378
 379     SkedCacheIt sked_it = skedCache.begin();
 380     SkedCacheIt sked_end = skedCache.end();
 381
 382     while (sked_it != sked_end) {
 383         delete (*sked_it).second;
 384         sked_it++;
 385     }
 386     skedCache.clear();
 387 }
 388
 389 m5::hash_map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
 390
 391 RSkedPtr
 392 InOrderCPU::createFrontEndSked()
 393 {
 394     RSkedPtr res_sked = new ResourceSked();
 395     int stage_num = 0;
 396     StageScheduler F(res_sked, stage_num++);
 397     StageScheduler D(res_sked, stage_num++);
 398
 399     // FETCH
 400     F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
 401     F.needs(ICache, FetchUnit::InitiateFetch);
 402
 403     // DECODE
 404     D.needs(ICache, FetchUnit::CompleteFetch);
 405     D.needs(Decode, DecodeUnit::DecodeInst);
 406     D.needs(BPred, BranchPredictor::PredictBranch);
 407     D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
 408
 409
 410     DPRINTF(SkedCache, "Resource Sked created for instruction \"front_end\"\n");
 411
 412     return res_sked;
 413 }
 414
 415 RSkedPtr
 416 InOrderCPU::createBackEndSked(DynInstPtr inst)
 417 {
 418     RSkedPtr res_sked = lookupSked(inst);
 419     if (res_sked != NULL) {
 420         DPRINTF(SkedCache, "Found %s in sked cache.\n",
 421                 inst->instName());
 422         return res_sked;
 423     } else {
 424         res_sked = new ResourceSked();
 425     }
 426
 427     int stage_num = ThePipeline::BackEndStartStage;
 428     StageScheduler X(res_sked, stage_num++);
 429     StageScheduler M(res_sked, stage_num++);
 430     StageScheduler W(res_sked, stage_num++);
 431
 432     if (!inst->staticInst) {
 433         warn_once("Static Instruction Object Not Set. Can't Create"
 434                   " Back End Schedule");
 435         return NULL;
 436     }
 437
 438     // EXECUTE
 439     X.needs(RegManager, UseDefUnit::MarkDestRegs);
 440     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 441         if (!idx || !inst->isStore()) {
 442             X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
 443         }
 444     }
 445
 446     //@todo: schedule non-spec insts to operate on this cycle
 447     // as long as all previous insts are done
 448     if ( inst->isNonSpeculative() ) {
 449         // skip execution of non speculative insts until later
 450     } else if ( inst->isMemRef() ) {
 451         if ( inst->isLoad() ) {
 452             X.needs(AGEN, AGENUnit::GenerateAddr);
 453         }
 454     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 455         X.needs(MDU, MultDivUnit::StartMultDiv);
 456     } else {
 457         X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 458     }
 459
 460     // MEMORY
 461     if (!inst->isNonSpeculative()) {
 462         if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 463             M.needs(MDU, MultDivUnit::EndMultDiv);
 464         }
 465
 466         if ( inst->isLoad() ) {
 467             M.needs(DCache, CacheUnit::InitiateReadData);
 468             if (inst->splitInst)
 469                 M.needs(DCache, CacheUnit::InitSecondSplitRead);
 470         } else if ( inst->isStore() ) {
 471             for (int i = 1; i < inst->numSrcRegs(); i++ ) {
 472                 M.needs(RegManager, UseDefUnit::ReadSrcReg, i);
 473             }
 474             M.needs(AGEN, AGENUnit::GenerateAddr);
 475             M.needs(DCache, CacheUnit::InitiateWriteData);
 476             if (inst->splitInst)
 477                 M.needs(DCache, CacheUnit::InitSecondSplitWrite);
 478         }
 479     }
 480
 481     // WRITEBACK
 482     if (!inst->isNonSpeculative()) {
 483         if ( inst->isLoad() ) {
 484             W.needs(DCache, CacheUnit::CompleteReadData);
 485             if (inst->splitInst)
 486                 W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
 487         } else if ( inst->isStore() ) {
 488             W.needs(DCache, CacheUnit::CompleteWriteData);
 489             if (inst->splitInst)
 490                 W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
 491         }
 492     } else {
 493         // Finally, Execute Speculative Data
 494         if (inst->isMemRef()) {
 495             if (inst->isLoad()) {
 496                 W.needs(AGEN, AGENUnit::GenerateAddr);
 497                 W.needs(DCache, CacheUnit::InitiateReadData);
 498                 if (inst->splitInst)
 499                     W.needs(DCache, CacheUnit::InitSecondSplitRead);
 500                 W.needs(DCache, CacheUnit::CompleteReadData);
 501                 if (inst->splitInst)
 502                     W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
 503             } else if (inst->isStore()) {
 504                 if ( inst->numSrcRegs() >= 2 ) {
 505                     W.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 506                 }
 507                 W.needs(AGEN, AGENUnit::GenerateAddr);
 508                 W.needs(DCache, CacheUnit::InitiateWriteData);
 509                 if (inst->splitInst)
 510                     W.needs(DCache, CacheUnit::InitSecondSplitWrite);
 511                 W.needs(DCache, CacheUnit::CompleteWriteData);
 512                 if (inst->splitInst)
 513                     W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
 514             }
 515         } else {
 516             W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 517         }
 518     }
 519
 520     W.needs(Grad, GraduationUnit::CheckFault);
 521
 522     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 523         W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
 524     }
 525
 526     if (inst->isControl())
 527         W.needs(BPred, BranchPredictor::UpdatePredictor);
 528
 529     W.needs(Grad, GraduationUnit::GraduateInst);
 530
 531     // Insert Back Schedule into our cache of
 532     // resource schedules
 533     addToSkedCache(inst, res_sked);
 534
 535     DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
 536             inst->instName(), inst->getMachInst());
 537     res_sked->print();
 538
 539     return res_sked;
 540 }
 541
 542 void
 543 InOrderCPU::regStats()
 544 {
 545     /* Register the Resource Pool's stats here.*/
 546     resPool->regStats();
 547
 548     /* Register for each Pipeline Stage */
 549     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 550         pipelineStage[stage_num]->regStats();
 551     }
 552
 553     /* Register any of the InOrderCPU's stats here.*/
 554     instsPerCtxtSwitch
 555         .name(name() + ".instsPerContextSwitch")
 556         .desc("Instructions Committed Per Context Switch")
 557         .prereq(instsPerCtxtSwitch);
 558
 559     numCtxtSwitches
 560         .name(name() + ".contextSwitches")
 561         .desc("Number of context switches");
 562
 563     comLoads
 564         .name(name() + ".comLoads")
 565         .desc("Number of Load instructions committed");
 566
 567     comStores
 568         .name(name() + ".comStores")
 569         .desc("Number of Store instructions committed");
 570
 571     comBranches
 572         .name(name() + ".comBranches")
 573         .desc("Number of Branches instructions committed");
 574
 575     comNops
 576         .name(name() + ".comNops")
 577         .desc("Number of Nop instructions committed");
 578
 579     comNonSpec
 580         .name(name() + ".comNonSpec")
 581         .desc("Number of Non-Speculative instructions committed");
 582
 583     comInts
 584         .name(name() + ".comInts")
 585         .desc("Number of Integer instructions committed");
 586
 587     comFloats
 588         .name(name() + ".comFloats")
 589         .desc("Number of Floating Point instructions committed");
 590
 591     timesIdled
 592         .name(name() + ".timesIdled")
 593         .desc("Number of times that the entire CPU went into an idle state and"
 594               " unscheduled itself")
 595         .prereq(timesIdled);
 596
 597     idleCycles
 598         .name(name() + ".idleCycles")
 599         .desc("Number of cycles cpu's stages were not processed");
 600
 601     runCycles
 602         .name(name() + ".runCycles")
 603         .desc("Number of cycles cpu stages are processed.");
 604
 605     activity
 606         .name(name() + ".activity")
 607         .desc("Percentage of cycles cpu is active")
 608         .precision(6);
 609     activity = (runCycles / numCycles) * 100;
 610
 611     threadCycles
 612         .init(numThreads)
 613         .name(name() + ".threadCycles")
 614         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 615
 616     smtCycles
 617         .name(name() + ".smtCycles")
 618         .desc("Total number of cycles that the CPU was in SMT-mode");
 619
 620     committedInsts
 621         .init(numThreads)
 622         .name(name() + ".committedInsts")
 623         .desc("Number of Instructions Simulated (Per-Thread)");
 624
 625     smtCommittedInsts
 626         .init(numThreads)
 627         .name(name() + ".smtCommittedInsts")
 628         .desc("Number of SMT Instructions Simulated (Per-Thread)");
 629
 630     totalCommittedInsts
 631         .name(name() + ".committedInsts_total")
 632         .desc("Number of Instructions Simulated (Total)");
 633
 634     cpi
 635         .name(name() + ".cpi")
 636         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 637         .precision(6);
 638     cpi = numCycles / committedInsts;
 639
 640     smtCpi
 641         .name(name() + ".smt_cpi")
 642         .desc("CPI: Total SMT-CPI")
 643         .precision(6);
 644     smtCpi = smtCycles / smtCommittedInsts;
 645
 646     totalCpi
 647         .name(name() + ".cpi_total")
 648         .desc("CPI: Total CPI of All Threads")
 649         .precision(6);
 650     totalCpi = numCycles / totalCommittedInsts;
 651
 652     ipc
 653         .name(name() + ".ipc")
 654         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 655         .precision(6);
 656     ipc =  committedInsts / numCycles;
 657
 658     smtIpc
 659         .name(name() + ".smt_ipc")
 660         .desc("IPC: Total SMT-IPC")
 661         .precision(6);
 662     smtIpc = smtCommittedInsts / smtCycles;
 663
 664     totalIpc
 665         .name(name() + ".ipc_total")
 666         .desc("IPC: Total IPC of All Threads")
 667         .precision(6);
 668         totalIpc =  totalCommittedInsts / numCycles;
 669
 670     BaseCPU::regStats();
 671 }
 672
 673
 674 void
 675 InOrderCPU::tick()
 676 {
 677     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 678
 679     ++numCycles;
 680
 681     bool pipes_idle = true;
 682
 683     //Tick each of the stages
 684     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 685         pipelineStage[stNum]->tick();
 686
 687         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 688     }
 689
 690     if (pipes_idle)
 691         idleCycles++;
 692     else
 693         runCycles++;
 694
 695     // Now advance the time buffers one tick
 696     timeBuffer.advance();
 697     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 698         stageQueue[sqNum]->advance();
 699     }
 700     activityRec.advance();
 701
 702     // Any squashed events, or insts then remove them now
 703     cleanUpRemovedEvents();
 704     cleanUpRemovedInsts();
 705
 706     // Re-schedule CPU for this cycle
 707     if (!tickEvent.scheduled()) {
 708         if (_status == SwitchedOut) {
 709             // increment stat
 710             lastRunningCycle = curTick();
 711         } else if (!activityRec.active()) {
 712             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 713             lastRunningCycle = curTick();
 714             timesIdled++;
 715         } else {
 716             //Tick next_tick = curTick() + cycles(1);
 717             //tickEvent.schedule(next_tick);
 718             schedule(&tickEvent, nextCycle(curTick() + 1));
 719             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 720                     nextCycle(curTick() + 1));
 721         }
 722     }
 723
 724     tickThreadStats();
 725     updateThreadPriority();
 726 }
 727
 728
 729 void
 730 InOrderCPU::init()
 731 {
 732     if (!deferRegistration) {
 733         registerThreadContexts();
 734     }
 735
 736     // Set inSyscall so that the CPU doesn't squash when initially
 737     // setting up registers.
 738     for (ThreadID tid = 0; tid < numThreads; ++tid)
 739         thread[tid]->inSyscall = true;
 740
 741 #if FULL_SYSTEM
 742     for (ThreadID tid = 0; tid < numThreads; tid++) {
 743         ThreadContext *src_tc = threadContexts[tid];
 744         TheISA::initCPU(src_tc, src_tc->contextId());
 745     }
 746 #endif
 747
 748     // Clear inSyscall.
 749     for (ThreadID tid = 0; tid < numThreads; ++tid)
 750         thread[tid]->inSyscall = false;
 751
 752     // Call Initializiation Routine for Resource Pool
 753     resPool->init();
 754 }
 755
 756 Port*
 757 InOrderCPU::getPort(const std::string &if_name, int idx)
 758 {
 759     return resPool->getPort(if_name, idx);
 760 }
 761
 762 #if FULL_SYSTEM
 763 Fault
 764 InOrderCPU::hwrei(ThreadID tid)
 765 {
 766 #if THE_ISA == ALPHA_ISA
 767     // Need to clear the lock flag upon returning from an interrupt.
 768     setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
 769
 770     thread[tid]->kernelStats->hwrei();
 771     // FIXME: XXX check for interrupts? XXX
 772 #endif
 773
 774     return NoFault;
 775 }
 776
 777
 778 bool
 779 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 780 {
 781 #if THE_ISA == ALPHA_ISA
 782     if (this->thread[tid]->kernelStats)
 783         this->thread[tid]->kernelStats->callpal(palFunc,
 784                                                 this->threadContexts[tid]);
 785
 786     switch (palFunc) {
 787       case PAL::halt:
 788         halt();
 789         if (--System::numSystemsRunning == 0)
 790             exitSimLoop("all cpus halted");
 791         break;
 792
 793       case PAL::bpt:
 794       case PAL::bugchk:
 795         if (this->system->breakpoint())
 796             return false;
 797         break;
 798     }
 799 #endif
 800     return true;
 801 }
 802
 803
 804 Fault
 805 InOrderCPU::getInterrupts()
 806 {
 807     // Check if there are any outstanding interrupts
 808     return interrupts->getInterrupt(threadContexts[0]);
 809 }
 810
 811
 812 void
 813 InOrderCPU::processInterrupts(Fault interrupt)
 814 {
 815     // Check for interrupts here.  For now can copy the code that
 816     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 817     // is the one that handles the interrupts.
 818     // @todo: Possibly consolidate the interrupt checking code.
 819     // @todo: Allow other threads to handle interrupts.
 820
 821     assert(interrupt != NoFault);
 822     interrupts->updateIntrInfo(threadContexts[0]);
 823
 824     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 825
 826     // Note: Context ID ok here? Impl. of FS mode needs to revisit this
 827     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 828 }
 829
 830
 831 void
 832 InOrderCPU::updateMemPorts()
 833 {
 834     // Update all ThreadContext's memory ports (Functional/Virtual
 835     // Ports)
 836     ThreadID size = thread.size();
 837     for (ThreadID i = 0; i < size; ++i)
 838         thread[i]->connectMemPorts(thread[i]->getTC());
 839 }
 840 #endif
 841
 842 void
 843 InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 844 {
 845     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 846 }
 847
 848 void
 849 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 850 {
 851     fault->invoke(tcBase(tid), inst->staticInst);
 852     removePipelineStalls(tid);
 853 }
 854
 855 void
 856 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 857 {
 858     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 859 }
 860
 861
 862 void
 863 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 864                                 ThreadID tid)
 865 {
 866     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 867
 868     // Squash all instructions in each stage including
 869     // instruction that caused the squash (seq_num - 1)
 870     // NOTE: The stage bandwidth needs to be cleared so thats why
 871     //       the stalling instruction is squashed as well. The stalled
 872     //       instruction is previously placed in another intermediate buffer
 873     //       while it's stall is being handled.
 874     InstSeqNum squash_seq_num = seq_num - 1;
 875
 876     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 877         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 878     }
 879 }
 880
 881 void
 882 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 883                              ThreadID tid, DynInstPtr inst,
 884                              unsigned delay, CPUEventPri event_pri)
 885 {
 886     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 887                                        event_pri);
 888
 889     Tick sked_tick = nextCycle(curTick() + ticks(delay));
 890     if (delay >= 0) {
 891         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 892                 eventNames[c_event], curTick() + delay, tid);
 893         schedule(cpu_event, sked_tick);
 894     } else {
 895         cpu_event->process();
 896         cpuEventRemoveList.push(cpu_event);
 897     }
 898
 899     // Broadcast event to the Resource Pool
 900     // Need to reset tid just in case this is a dummy instruction
 901     inst->setTid(tid);
 902     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 903 }
 904
 905 bool
 906 InOrderCPU::isThreadActive(ThreadID tid)
 907 {
 908   list<ThreadID>::iterator isActive =
 909       std::find(activeThreads.begin(), activeThreads.end(), tid);
 910
 911     return (isActive != activeThreads.end());
 912 }
 913
 914 bool
 915 InOrderCPU::isThreadReady(ThreadID tid)
 916 {
 917   list<ThreadID>::iterator isReady =
 918       std::find(readyThreads.begin(), readyThreads.end(), tid);
 919
 920     return (isReady != readyThreads.end());
 921 }
 922
 923 bool
 924 InOrderCPU::isThreadSuspended(ThreadID tid)
 925 {
 926   list<ThreadID>::iterator isSuspended =
 927       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
 928
 929     return (isSuspended != suspendedThreads.end());
 930 }
 931
 932 void
 933 InOrderCPU::activateNextReadyThread()
 934 {
 935     if (readyThreads.size() >= 1) {
 936         ThreadID ready_tid = readyThreads.front();
 937
 938         // Activate in Pipeline
 939         activateThread(ready_tid);
 940
 941         // Activate in Resource Pool
 942         resPool->activateThread(ready_tid);
 943
 944         list<ThreadID>::iterator ready_it =
 945             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
 946         readyThreads.erase(ready_it);
 947     } else {
 948         DPRINTF(InOrderCPU,
 949                 "Attempting to activate new thread, but No Ready Threads to"
 950                 "activate.\n");
 951         DPRINTF(InOrderCPU,
 952                 "Unable to switch to next active thread.\n");
 953     }
 954 }
 955
 956 void
 957 InOrderCPU::activateThread(ThreadID tid)
 958 {
 959     if (isThreadSuspended(tid)) {
 960         DPRINTF(InOrderCPU,
 961                 "Removing [tid:%i] from suspended threads list.\n", tid);
 962
 963         list<ThreadID>::iterator susp_it =
 964             std::find(suspendedThreads.begin(), suspendedThreads.end(),
 965                       tid);
 966         suspendedThreads.erase(susp_it);
 967     }
 968
 969     if (threadModel == SwitchOnCacheMiss &&
 970         numActiveThreads() == 1) {
 971         DPRINTF(InOrderCPU,
 972                 "Ignoring activation of [tid:%i], since [tid:%i] is "
 973                 "already running.\n", tid, activeThreadId());
 974
 975         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
 976                 tid);
 977
 978         readyThreads.push_back(tid);
 979
 980     } else if (!isThreadActive(tid)) {
 981         DPRINTF(InOrderCPU,
 982                 "Adding [tid:%i] to active threads list.\n", tid);
 983         activeThreads.push_back(tid);
 984
 985         activateThreadInPipeline(tid);
 986
 987         thread[tid]->lastActivate = curTick();
 988
 989         tcBase(tid)->setStatus(ThreadContext::Active);
 990
 991         wakeCPU();
 992
 993         numCtxtSwitches++;
 994     }
 995 }
 996
 997 void
 998 InOrderCPU::activateThreadInPipeline(ThreadID tid)
 999 {
1000     for (int stNum=0; stNum < NumStages; stNum++) {
1001         pipelineStage[stNum]->activateThread(tid);
1002     }
1003 }
1004
1005 void
1006 InOrderCPU::deactivateContext(ThreadID tid, int delay)
1007 {
1008     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
1009
1010     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
1011
1012     // Be sure to signal that there's some activity so the CPU doesn't
1013     // deschedule itself.
1014     activityRec.activity();
1015
1016     _status = Running;
1017 }
1018
1019 void
1020 InOrderCPU::deactivateThread(ThreadID tid)
1021 {
1022     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
1023
1024     if (isThreadActive(tid)) {
1025         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
1026                 tid);
1027         list<ThreadID>::iterator thread_it =
1028             std::find(activeThreads.begin(), activeThreads.end(), tid);
1029
1030         removePipelineStalls(*thread_it);
1031
1032         activeThreads.erase(thread_it);
1033
1034         // Ideally, this should be triggered from the
1035         // suspendContext/Thread functions
1036         tcBase(tid)->setStatus(ThreadContext::Suspended);
1037     }
1038
1039     assert(!isThreadActive(tid));
1040 }
1041
1042 void
1043 InOrderCPU::removePipelineStalls(ThreadID tid)
1044 {
1045     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
1046             tid);
1047
1048     for (int stNum = 0; stNum < NumStages ; stNum++) {
1049         pipelineStage[stNum]->removeStalls(tid);
1050     }
1051
1052 }
1053
1054 void
1055 InOrderCPU::updateThreadPriority()
1056 {
1057     if (activeThreads.size() > 1)
1058     {
1059         //DEFAULT TO ROUND ROBIN SCHEME
1060         //e.g. Move highest priority to end of thread list
1061         list<ThreadID>::iterator list_begin = activeThreads.begin();
1062         list<ThreadID>::iterator list_end   = activeThreads.end();
1063
1064         unsigned high_thread = *list_begin;
1065
1066         activeThreads.erase(list_begin);
1067
1068         activeThreads.push_back(high_thread);
1069     }
1070 }
1071
1072 inline void
1073 InOrderCPU::tickThreadStats()
1074 {
1075     /** Keep track of cycles that each thread is active */
1076     list<ThreadID>::iterator thread_it = activeThreads.begin();
1077     while (thread_it != activeThreads.end()) {
1078         threadCycles[*thread_it]++;
1079         thread_it++;
1080     }
1081
1082     // Keep track of cycles where SMT is active
1083     if (activeThreads.size() > 1) {
1084         smtCycles++;
1085     }
1086 }
1087
1088 void
1089 InOrderCPU::activateContext(ThreadID tid, int delay)
1090 {
1091     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
1092
1093
1094     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
1095
1096     // Be sure to signal that there's some activity so the CPU doesn't
1097     // deschedule itself.
1098     activityRec.activity();
1099
1100     _status = Running;
1101 }
1102
1103 void
1104 InOrderCPU::activateNextReadyContext(int delay)
1105 {
1106     DPRINTF(InOrderCPU,"Activating next ready thread\n");
1107
1108     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
1109                      delay, ActivateNextReadyThread_Pri);
1110
1111     // Be sure to signal that there's some activity so the CPU doesn't
1112     // deschedule itself.
1113     activityRec.activity();
1114
1115     _status = Running;
1116 }
1117
1118 void
1119 InOrderCPU::haltContext(ThreadID tid, int delay)
1120 {
1121     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
1122
1123     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
1124
1125     activityRec.activity();
1126 }
1127
1128 void
1129 InOrderCPU::haltThread(ThreadID tid)
1130 {
1131     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
1132     deactivateThread(tid);
1133     squashThreadInPipeline(tid);
1134     haltedThreads.push_back(tid);
1135
1136     tcBase(tid)->setStatus(ThreadContext::Halted);
1137
1138     if (threadModel == SwitchOnCacheMiss) {
1139         activateNextReadyContext();
1140     }
1141 }
1142
1143 void
1144 InOrderCPU::suspendContext(ThreadID tid, int delay)
1145 {
1146     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
1147 }
1148
1149 void
1150 InOrderCPU::suspendThread(ThreadID tid)
1151 {
1152     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
1153             tid);
1154     deactivateThread(tid);
1155     suspendedThreads.push_back(tid);
1156     thread[tid]->lastSuspend = curTick();
1157
1158     tcBase(tid)->setStatus(ThreadContext::Suspended);
1159 }
1160
1161 void
1162 InOrderCPU::squashThreadInPipeline(ThreadID tid)
1163 {
1164     //Squash all instructions in each stage
1165     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
1166         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
1167     }
1168 }
1169
1170 PipelineStage*
1171 InOrderCPU::getPipeStage(int stage_num)
1172 {
1173     return pipelineStage[stage_num];
1174 }
1175
1176
1177 RegIndex
1178 InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
1179 {
1180     if (reg_idx < FP_Base_DepTag) {
1181         reg_type = IntType;
1182         return isa[tid].flattenIntIndex(reg_idx);
1183     } else if (reg_idx < Ctrl_Base_DepTag) {
1184         reg_type = FloatType;
1185         reg_idx -= FP_Base_DepTag;
1186         return isa[tid].flattenFloatIndex(reg_idx);
1187     } else {
1188         reg_type = MiscType;
1189         return reg_idx - TheISA::Ctrl_Base_DepTag;
1190     }
1191 }
1192
1193 uint64_t
1194 InOrderCPU::readIntReg(RegIndex reg_idx, ThreadID tid)
1195 {
1196     DPRINTF(IntRegs, "[tid:%i]: Reading Int. Reg %i as %x\n",
1197             tid, reg_idx, intRegs[tid][reg_idx]);
1198
1199     return intRegs[tid][reg_idx];
1200 }
1201
1202 FloatReg
1203 InOrderCPU::readFloatReg(RegIndex reg_idx, ThreadID tid)
1204 {
1205     DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1206             tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
1207
1208     return floatRegs.f[tid][reg_idx];
1209 }
1210
1211 FloatRegBits
1212 InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
1213 {
1214     DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1215             tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
1216
1217     return floatRegs.i[tid][reg_idx];
1218 }
1219
1220 void
1221 InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid)
1222 {
1223     if (reg_idx == TheISA::ZeroReg) {
1224         DPRINTF(IntRegs, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1225                 "(Int. Reg %i) to %x\n", tid, reg_idx, val);
1226         return;
1227     } else {
1228         DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
1229                 tid, reg_idx, val);
1230
1231         intRegs[tid][reg_idx] = val;
1232     }
1233 }
1234
1235
1236 void
1237 InOrderCPU::setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid)
1238 {
1239     floatRegs.f[tid][reg_idx] = val;
1240     DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
1241             "%x, %08f\n",
1242             tid, reg_idx,
1243             floatRegs.i[tid][reg_idx],
1244             floatRegs.f[tid][reg_idx]);
1245 }
1246
1247
1248 void
1249 InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid)
1250 {
1251     floatRegs.i[tid][reg_idx] = val;
1252     DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
1253             "%x, %08f\n",
1254             tid, reg_idx,
1255             floatRegs.i[tid][reg_idx],
1256             floatRegs.f[tid][reg_idx]);
1257 }
1258
1259 uint64_t
1260 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1261 {
1262     // If Default value is set, then retrieve target thread
1263     if (tid == InvalidThreadID) {
1264         tid = TheISA::getTargetThread(tcBase(tid));
1265     }
1266
1267     if (reg_idx < FP_Base_DepTag) {
1268         // Integer Register File
1269         return readIntReg(reg_idx, tid);
1270     } else if (reg_idx < Ctrl_Base_DepTag) {
1271         // Float Register File
1272         reg_idx -= FP_Base_DepTag;
1273         return readFloatRegBits(reg_idx, tid);
1274     } else {
1275         reg_idx -= Ctrl_Base_DepTag;
1276         return readMiscReg(reg_idx, tid);  // Misc. Register File
1277     }
1278 }
1279 void
1280 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1281                               ThreadID tid)
1282 {
1283     // If Default value is set, then retrieve target thread
1284     if (tid == InvalidThreadID) {
1285         tid = TheISA::getTargetThread(tcBase(tid));
1286     }
1287
1288     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1289         setIntReg(reg_idx, val, tid);
1290     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1291         reg_idx -= FP_Base_DepTag;
1292         setFloatRegBits(reg_idx, val, tid);
1293     } else {
1294         reg_idx -= Ctrl_Base_DepTag;
1295         setMiscReg(reg_idx, val, tid); // Misc. Register File
1296     }
1297 }
1298
1299 MiscReg
1300 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1301 {
1302     return isa[tid].readMiscRegNoEffect(misc_reg);
1303 }
1304
1305 MiscReg
1306 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1307 {
1308     DPRINTF(InOrderCPU, "MiscReg: %i\n", misc_reg);
1309     DPRINTF(InOrderCPU, "tid: %i\n", tid);
1310     DPRINTF(InOrderCPU, "tcBase: %x\n", tcBase(tid));
1311     DPRINTF(InOrderCPU, "isa-tid: %x\n", &isa[tid]);
1312
1313     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1314 }
1315
1316 void
1317 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1318 {
1319     isa[tid].setMiscRegNoEffect(misc_reg, val);
1320 }
1321
1322 void
1323 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1324 {
1325     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1326 }
1327
1328
1329 InOrderCPU::ListIt
1330 InOrderCPU::addInst(DynInstPtr inst)
1331 {
1332     ThreadID tid = inst->readTid();
1333
1334     instList[tid].push_back(inst);
1335
1336     return --(instList[tid].end());
1337 }
1338
1339 InOrderCPU::ListIt
1340 InOrderCPU::findInst(InstSeqNum seq_num, ThreadID tid)
1341 {
1342     ListIt it = instList[tid].begin();
1343     ListIt end = instList[tid].end();
1344
1345     while (it != end) {
1346         if ((*it)->seqNum == seq_num)
1347             return it;
1348         else if ((*it)->seqNum > seq_num)
1349             break;
1350
1351         it++;
1352     }
1353
1354     return instList[tid].end();
1355 }
1356
1357 void
1358 InOrderCPU::updateContextSwitchStats()
1359 {
1360     // Set Average Stat Here, then reset to 0
1361     instsPerCtxtSwitch = instsPerSwitch;
1362     instsPerSwitch = 0;
1363 }
1364
1365
1366 void
1367 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1368 {
1369     // Set the nextPC to be fetched if this is the last instruction
1370     // committed
1371     // ========
1372     // This contributes to the precise state of the CPU
1373     // which can be used when restoring a thread to the CPU after after any
1374     // type of context switching activity (fork, exception, etc.)
1375     TheISA::PCState comm_pc = inst->pcState();
1376     lastCommittedPC[tid] = comm_pc;
1377     TheISA::advancePC(comm_pc, inst->staticInst);
1378     pcState(comm_pc, tid);
1379
1380     //@todo: may be unnecessary with new-ISA-specific branch handling code
1381     if (inst->isControl()) {
1382         thread[tid]->lastGradIsBranch = true;
1383         thread[tid]->lastBranchPC = inst->pcState();
1384         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1385     } else {
1386         thread[tid]->lastGradIsBranch = false;
1387     }
1388
1389
1390     // Finalize Trace Data For Instruction
1391     if (inst->traceData) {
1392         //inst->traceData->setCycle(curTick());
1393         inst->traceData->setFetchSeq(inst->seqNum);
1394         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1395         inst->traceData->dump();
1396         delete inst->traceData;
1397         inst->traceData = NULL;
1398     }
1399
1400     // Increment active thread's instruction count
1401     instsPerSwitch++;
1402
1403     // Increment thread-state's instruction count
1404     thread[tid]->numInst++;
1405
1406     // Increment thread-state's instruction stats
1407     thread[tid]->numInsts++;
1408
1409     // Count committed insts per thread stats
1410     committedInsts[tid]++;
1411
1412     // Count total insts committed stat
1413     totalCommittedInsts++;
1414
1415     // Count SMT-committed insts per thread stat
1416     if (numActiveThreads() > 1) {
1417         smtCommittedInsts[tid]++;
1418     }
1419
1420     // Instruction-Mix Stats
1421     if (inst->isLoad()) {
1422         comLoads++;
1423     } else if (inst->isStore()) {
1424         comStores++;
1425     } else if (inst->isControl()) {
1426         comBranches++;
1427     } else if (inst->isNop()) {
1428         comNops++;
1429     } else if (inst->isNonSpeculative()) {
1430         comNonSpec++;
1431     } else if (inst->isInteger()) {
1432         comInts++;
1433     } else if (inst->isFloating()) {
1434         comFloats++;
1435     }
1436
1437     // Check for instruction-count-based events.
1438     comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1439
1440     // Finally, remove instruction from CPU
1441     removeInst(inst);
1442 }
1443
1444 // currently unused function, but substitute repetitive code w/this function
1445 // call
1446 void
1447 InOrderCPU::addToRemoveList(DynInstPtr inst)
1448 {
1449     removeInstsThisCycle = true;
1450     if (!inst->isRemoveList()) {
1451         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1452                 "[sn:%lli] to remove list\n",
1453                 inst->threadNumber, inst->pcState(), inst->seqNum);
1454         inst->setRemoveList();
1455         removeList.push(inst->getInstListIt());
1456     }  else {
1457         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1458                 "[sn:%lli], already remove list\n",
1459                 inst->threadNumber, inst->pcState(), inst->seqNum);
1460     }
1461
1462 }
1463
1464 void
1465 InOrderCPU::removeInst(DynInstPtr inst)
1466 {
1467     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1468             "[sn:%lli]\n",
1469             inst->threadNumber, inst->pcState(), inst->seqNum);
1470
1471     removeInstsThisCycle = true;
1472
1473     // Remove the instruction.
1474     if (!inst->isRemoveList()) {
1475         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1476                 "[sn:%lli] to remove list\n",
1477                 inst->threadNumber, inst->pcState(), inst->seqNum);
1478         inst->setRemoveList();
1479         removeList.push(inst->getInstListIt());
1480     } else {
1481         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1482                 "[sn:%lli], already on remove list\n",
1483                 inst->threadNumber, inst->pcState(), inst->seqNum);
1484     }
1485
1486 }
1487
1488 void
1489 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1490 {
1491     //assert(!instList[tid].empty());
1492
1493     removeInstsThisCycle = true;
1494
1495     ListIt inst_iter = instList[tid].end();
1496
1497     inst_iter--;
1498
1499     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1500             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1501             tid, seq_num, (*inst_iter)->seqNum);
1502
1503     while ((*inst_iter)->seqNum > seq_num) {
1504
1505         bool break_loop = (inst_iter == instList[tid].begin());
1506
1507         squashInstIt(inst_iter, tid);
1508
1509         inst_iter--;
1510
1511         if (break_loop)
1512             break;
1513     }
1514 }
1515
1516
1517 inline void
1518 InOrderCPU::squashInstIt(const ListIt inst_it, ThreadID tid)
1519 {
1520     DynInstPtr inst = (*inst_it);
1521     if (inst->threadNumber == tid) {
1522         DPRINTF(InOrderCPU, "Squashing instruction, "
1523                 "[tid:%i] [sn:%lli] PC %s\n",
1524                 inst->threadNumber,
1525                 inst->seqNum,
1526                 inst->pcState());
1527
1528         inst->setSquashed();
1529         archRegDepMap[tid].remove(inst);
1530
1531         if (!inst->isRemoveList()) {
1532             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1533                     "[sn:%lli] to remove list\n",
1534                     inst->threadNumber, inst->pcState(),
1535                     inst->seqNum);
1536             inst->setRemoveList();
1537             removeList.push(inst_it);
1538         } else {
1539             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1540                     " PC %s [sn:%lli], already on remove list\n",
1541                     inst->threadNumber, inst->pcState(),
1542                     inst->seqNum);
1543         }
1544
1545     }
1546
1547 }
1548
1549
1550 void
1551 InOrderCPU::cleanUpRemovedInsts()
1552 {
1553     while (!removeList.empty()) {
1554         DPRINTF(InOrderCPU, "Removing instruction, "
1555                 "[tid:%i] [sn:%lli] PC %s\n",
1556                 (*removeList.front())->threadNumber,
1557                 (*removeList.front())->seqNum,
1558                (*removeList.front())->pcState());
1559
1560         DynInstPtr inst = *removeList.front();
1561         ThreadID tid = inst->threadNumber;
1562
1563         // Remove From Register Dependency Map, If Necessary
1564         // archRegDepMap[tid].remove(inst);
1565
1566         // Clear if Non-Speculative
1567         if (inst->staticInst &&
1568             inst->seqNum == nonSpecSeqNum[tid] &&
1569             nonSpecInstActive[tid] == true) {
1570             nonSpecInstActive[tid] = false;
1571         }
1572
1573         inst->onInstList = false;
1574
1575         instList[tid].erase(removeList.front());
1576
1577         removeList.pop();
1578     }
1579
1580     removeInstsThisCycle = false;
1581 }
1582
1583 void
1584 InOrderCPU::cleanUpRemovedEvents()
1585 {
1586     while (!cpuEventRemoveList.empty()) {
1587         Event *cpu_event = cpuEventRemoveList.front();
1588         cpuEventRemoveList.pop();
1589         delete cpu_event;
1590     }
1591 }
1592
1593
1594 void
1595 InOrderCPU::dumpInsts()
1596 {
1597     int num = 0;
1598
1599     ListIt inst_list_it = instList[0].begin();
1600
1601     cprintf("Dumping Instruction List\n");
1602
1603     while (inst_list_it != instList[0].end()) {
1604         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1605                 "Squashed:%i\n\n",
1606                 num, (*inst_list_it)->pcState(),
1607                 (*inst_list_it)->threadNumber,
1608                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1609                 (*inst_list_it)->isSquashed());
1610         inst_list_it++;
1611         ++num;
1612     }
1613 }
1614
1615 void
1616 InOrderCPU::wakeCPU()
1617 {
1618     if (/*activityRec.active() || */tickEvent.scheduled()) {
1619         DPRINTF(Activity, "CPU already running.\n");
1620         return;
1621     }
1622
1623     DPRINTF(Activity, "Waking up CPU\n");
1624
1625     Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
1626
1627     idleCycles += extra_cycles;
1628     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1629         pipelineStage[stage_num]->idleCycles += extra_cycles;
1630     }
1631
1632     numCycles += extra_cycles;
1633
1634     schedule(&tickEvent, nextCycle(curTick()));
1635 }
1636
1637 #if FULL_SYSTEM
1638 // Lots of copied full system code...place into BaseCPU class?
1639 void
1640 InOrderCPU::wakeup()
1641 {
1642     if (thread[0]->status() != ThreadContext::Suspended)
1643         return;
1644
1645     wakeCPU();
1646
1647     DPRINTF(Quiesce, "Suspended Processor woken\n");
1648     threadContexts[0]->activate();
1649 }
1650 #endif
1651
1652 #if !FULL_SYSTEM
1653 void
1654 InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
1655 {
1656     //@todo: squash behind syscall
1657     scheduleCpuEvent(Syscall, fault, tid, inst, delay, Syscall_Pri);
1658 }
1659
1660 void
1661 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1662 {
1663     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1664
1665     DPRINTF(Activity,"Activity: syscall() called.\n");
1666
1667     // Temporarily increase this by one to account for the syscall
1668     // instruction.
1669     ++(this->thread[tid]->funcExeInst);
1670
1671     // Execute the actual syscall.
1672     this->thread[tid]->syscall(callnum);
1673
1674     // Decrease funcExeInst by one as the normal commit will handle
1675     // incrementing it.
1676     --(this->thread[tid]->funcExeInst);
1677
1678     // Clear Non-Speculative Block Variable
1679     nonSpecInstActive[tid] = false;
1680 }
1681 #endif
1682
1683 TheISA::TLB*
1684 InOrderCPU::getITBPtr()
1685 {
1686     CacheUnit *itb_res =
1687         dynamic_cast<CacheUnit*>(resPool->getResource(fetchPortIdx));
1688     return itb_res->tlb();
1689 }
1690
1691
1692 TheISA::TLB*
1693 InOrderCPU::getDTBPtr()
1694 {
1695     CacheUnit *dtb_res =
1696         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1697     return dtb_res->tlb();
1698 }
1699
1700 Fault
1701 InOrderCPU::read(DynInstPtr inst, Addr addr,
1702                  uint8_t *data, unsigned size, unsigned flags)
1703 {
1704     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1705     //       you want to run w/out caches?
1706     CacheUnit *cache_res =
1707         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1708
1709     return cache_res->read(inst, addr, data, size, flags);
1710 }
1711
1712 Fault
1713 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1714                   Addr addr, unsigned flags, uint64_t *write_res)
1715 {
1716     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1717     //       you want to run w/out caches?
1718     CacheUnit *cache_res =
1719         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1720     return cache_res->write(inst, data, size, addr, flags, write_res);
1721 }