2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "arch/utility.hh"
35 #include "config/full_system.hh"
36 #include "cpu/exetrace.hh"
37 #include "cpu/activity.hh"
38 #include "cpu/simple_thread.hh"
39 #include "cpu/thread_context.hh"
40 #include "cpu/base.hh"
41 #include "cpu/inorder/inorder_dyn_inst.hh"
42 #include "cpu/inorder/thread_context.hh"
43 #include "cpu/inorder/thread_state.hh"
44 #include "cpu/inorder/cpu.hh"
45 #include "params/InOrderCPU.hh"
46 #include "cpu/inorder/pipeline_traits.hh"
47 #include "cpu/inorder/first_stage.hh"
48 #include "cpu/inorder/resources/resource_list.hh"
49 #include "cpu/inorder/resource_pool.hh"
50 #include "mem/translating_port.hh"
51 #include "sim/process.hh"
52 #include "sim/stat_control.hh"
55 using namespace TheISA
;
56 using namespace ThePipeline
;
58 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
59 : Event(CPU_Tick_Pri
), cpu(c
)
64 InOrderCPU::TickEvent::process()
71 InOrderCPU::TickEvent::description()
73 return "InOrderCPU tick event";
76 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
77 Fault fault
, ThreadID _tid
, unsigned _vpe
)
78 : Event(CPU_Tick_Pri
), cpu(_cpu
)
80 setEvent(e_type
, fault
, _tid
, _vpe
);
84 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
100 InOrderCPU::CPUEvent::process()
102 switch (cpuEventType
)
105 cpu
->activateThread(tid
);
108 //@TODO: Consider Implementing "Suspend Thread" as Separate from Deallocate
109 case SuspendThread
: // Suspend & Deallocate are same for now.
110 //cpu->suspendThread(tid);
112 case DeallocateThread
:
113 cpu
->deallocateThread(tid
);
117 cpu
->enableVPEs(vpe
);
121 cpu
->disableVPEs(tid
, vpe
);
125 cpu
->enableThreads(vpe
);
129 cpu
->disableThreads(tid
, vpe
);
133 cpu
->trapCPU(fault
, tid
);
137 fatal("Unrecognized Event Type %d", cpuEventType
);
140 cpu
->cpuEventRemoveList
.push(this);
144 InOrderCPU::CPUEvent::description()
146 return "InOrderCPU event";
150 InOrderCPU::CPUEvent::scheduleEvent(int delay
)
153 mainEventQueue
.reschedule(this,curTick
+ cpu
->ticks(delay
));
154 else if (!scheduled())
155 mainEventQueue
.schedule(this,curTick
+ cpu
->ticks(delay
));
159 InOrderCPU::CPUEvent::unscheduleEvent()
165 InOrderCPU::InOrderCPU(Params
*params
)
167 cpu_id(params
->cpu_id
),
172 removeInstsThisCycle(false),
173 activityRec(params
->name
, NumStages
, 10, params
->activity
),
175 deferRegistration(false/*params->deferRegistration*/),
176 stageTracing(params
->stageTracing
),
181 resPool
= new ResourcePool(this, params
);
183 // Resize for Multithreading CPUs
184 thread
.resize(numThreads
);
186 ThreadID active_threads
= params
->workload
.size();
188 if (active_threads
> MaxThreads
) {
189 panic("Workload Size too large. Increase the 'MaxThreads'"
190 "in your InOrder implementation or "
191 "edit your workload size.");
194 // Bind the fetch & data ports from the resource pool.
195 fetchPortIdx
= resPool
->getPortIdx(params
->fetchMemPort
);
196 if (fetchPortIdx
== 0) {
197 fatal("Unable to find port to fetch instructions from.\n");
200 dataPortIdx
= resPool
->getPortIdx(params
->dataMemPort
);
201 if (dataPortIdx
== 0) {
202 fatal("Unable to find port for data.\n");
205 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
206 if (tid
< (ThreadID
)params
->workload
.size()) {
207 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
208 tid
, this->thread
[tid
]);
210 new Thread(this, tid
, params
->workload
[tid
], tid
);
212 //Allocate Empty thread so M5 can use later
213 //when scheduling threads to CPU
214 Process
* dummy_proc
= params
->workload
[0];
215 this->thread
[tid
] = new Thread(this, tid
, dummy_proc
, tid
);
218 // Setup the TC that will serve as the interface to the threads/CPU.
219 InOrderThreadContext
*tc
= new InOrderThreadContext
;
221 tc
->thread
= thread
[tid
];
223 // Give the thread the TC.
224 thread
[tid
]->tc
= tc
;
225 thread
[tid
]->setFuncExeInst(0);
226 globalSeqNum
[tid
] = 1;
228 // Add the TC to the CPU's list of TC's.
229 this->threadContexts
.push_back(tc
);
232 // Initialize TimeBuffer Stage Queues
233 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
234 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
235 stageQueue
[stNum
]->id(stNum
);
239 // Set Up Pipeline Stages
240 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
242 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
244 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
246 pipelineStage
[stNum
]->setCPU(this);
247 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
248 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
250 // Take Care of 1st/Nth stages
252 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
253 if (stNum
< NumStages
- 1)
254 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
257 // Initialize thread specific variables
258 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
259 archRegDepMap
[tid
].setCPU(this);
261 nonSpecInstActive
[tid
] = false;
262 nonSpecSeqNum
[tid
] = 0;
264 squashSeqNum
[tid
] = MaxAddr
;
265 lastSquashCycle
[tid
] = 0;
267 intRegFile
[tid
].clear();
268 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
271 isa
[tid
].expandForMultithreading(numThreads
, numVirtProcs
);
274 lastRunningCycle
= curTick
;
275 contextSwitch
= false;
277 // Define dummy instructions and resource requests to be used.
278 DynInstPtr dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0);
279 dummyReq
= new ResourceRequest(NULL
, NULL
, 0, 0, 0, 0);
281 // Reset CPU to reset state.
283 Fault resetFault
= new ResetFault();
284 resetFault
->invoke(tcBase());
289 // Schedule First Tick Event, CPU will reschedule itself from here on out.
290 scheduleTickEvent(0);
295 InOrderCPU::regStats()
297 /* Register the Resource Pool's stats here.*/
300 /* Register any of the InOrderCPU's stats here.*/
302 .name(name() + ".timesIdled")
303 .desc("Number of times that the entire CPU went into an idle state and"
304 " unscheduled itself")
308 .name(name() + ".idleCycles")
309 .desc("Total number of cycles that the CPU has spent unscheduled due "
315 .name(name() + ".threadCycles")
316 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
319 .name(name() + ".smtCycles")
320 .desc("Total number of cycles that the CPU was simultaneous multithreading.(SMT)");
324 .name(name() + ".committedInsts")
325 .desc("Number of Instructions Simulated (Per-Thread)");
329 .name(name() + ".smtCommittedInsts")
330 .desc("Number of SMT Instructions Simulated (Per-Thread)");
333 .name(name() + ".committedInsts_total")
334 .desc("Number of Instructions Simulated (Total)");
337 .name(name() + ".cpi")
338 .desc("CPI: Cycles Per Instruction (Per-Thread)")
340 cpi
= threadCycles
/ committedInsts
;
343 .name(name() + ".smt_cpi")
344 .desc("CPI: Total SMT-CPI")
346 smtCpi
= smtCycles
/ smtCommittedInsts
;
349 .name(name() + ".cpi_total")
350 .desc("CPI: Total CPI of All Threads")
352 totalCpi
= numCycles
/ totalCommittedInsts
;
355 .name(name() + ".ipc")
356 .desc("IPC: Instructions Per Cycle (Per-Thread)")
358 ipc
= committedInsts
/ threadCycles
;
361 .name(name() + ".smt_ipc")
362 .desc("IPC: Total SMT-IPC")
364 smtIpc
= smtCommittedInsts
/ smtCycles
;
367 .name(name() + ".ipc_total")
368 .desc("IPC: Total IPC of All Threads")
370 totalIpc
= totalCommittedInsts
/ numCycles
;
379 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
383 //Tick each of the stages
384 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
385 pipelineStage
[stNum
]->tick();
388 // Now advance the time buffers one tick
389 timeBuffer
.advance();
390 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
391 stageQueue
[sqNum
]->advance();
393 activityRec
.advance();
395 // Any squashed requests, events, or insts then remove them now
396 cleanUpRemovedReqs();
397 cleanUpRemovedEvents();
398 cleanUpRemovedInsts();
400 // Re-schedule CPU for this cycle
401 if (!tickEvent
.scheduled()) {
402 if (_status
== SwitchedOut
) {
404 lastRunningCycle
= curTick
;
405 } else if (!activityRec
.active()) {
406 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
407 lastRunningCycle
= curTick
;
410 //Tick next_tick = curTick + cycles(1);
411 //tickEvent.schedule(next_tick);
412 mainEventQueue
.schedule(&tickEvent
, nextCycle(curTick
+ 1));
413 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n", nextCycle() + curTick
);
418 updateThreadPriority();
425 if (!deferRegistration
) {
426 registerThreadContexts();
429 // Set inSyscall so that the CPU doesn't squash when initially
430 // setting up registers.
431 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
432 thread
[tid
]->inSyscall
= true;
435 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
436 ThreadContext
*src_tc
= threadContexts
[tid
];
437 TheISA::initCPU(src_tc
, src_tc
->contextId());
442 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
443 thread
[tid
]->inSyscall
= false;
445 // Call Initializiation Routine for Resource Pool
450 InOrderCPU::readFunctional(Addr addr
, uint32_t &buffer
)
452 tcBase()->getMemPort()->readBlob(addr
, (uint8_t*)&buffer
, sizeof(uint32_t));
453 buffer
= gtoh(buffer
);
459 for (int i
= 0; i
< numThreads
; i
++) {
460 isa
[i
].reset(coreType
, numThreads
,
461 numVirtProcs
, dynamic_cast<BaseCPU
*>(this));
466 InOrderCPU::getPort(const std::string
&if_name
, int idx
)
468 return resPool
->getPort(if_name
, idx
);
472 InOrderCPU::trap(Fault fault
, ThreadID tid
, int delay
)
474 //@ Squash Pipeline during TRAP
475 scheduleCpuEvent(Trap
, fault
, tid
, 0/*vpe*/, delay
);
479 InOrderCPU::trapCPU(Fault fault
, ThreadID tid
)
481 fault
->invoke(tcBase(tid
));
485 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
486 ThreadID tid
, unsigned vpe
, unsigned delay
)
488 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, vpe
);
491 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i.\n",
492 eventNames
[c_event
], curTick
+ delay
);
493 mainEventQueue
.schedule(cpu_event
,curTick
+ delay
);
495 cpu_event
->process();
496 cpuEventRemoveList
.push(cpu_event
);
499 // Broadcast event to the Resource Pool
500 DynInstPtr dummy_inst
=
501 new InOrderDynInst(this, NULL
, getNextEventNum(), tid
);
502 resPool
->scheduleEvent(c_event
, dummy_inst
, 0, 0, tid
);
506 InOrderCPU::isThreadActive(ThreadID tid
)
508 list
<ThreadID
>::iterator isActive
=
509 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
511 return (isActive
!= activeThreads
.end());
516 InOrderCPU::activateThread(ThreadID tid
)
518 if (!isThreadActive(tid
)) {
520 "Adding Thread %i to active threads list in CPU.\n", tid
);
521 activeThreads
.push_back(tid
);
528 InOrderCPU::deactivateThread(ThreadID tid
)
530 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
532 if (isThreadActive(tid
)) {
533 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
535 list
<ThreadID
>::iterator thread_it
=
536 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
538 removePipelineStalls(*thread_it
);
540 //@TODO: change stage status' to Idle?
542 activeThreads
.erase(thread_it
);
547 InOrderCPU::removePipelineStalls(ThreadID tid
)
549 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
552 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
553 pipelineStage
[stNum
]->removeStalls(tid
);
558 InOrderCPU::isThreadInCPU(ThreadID tid
)
560 list
<ThreadID
>::iterator isCurrent
=
561 std::find(currentThreads
.begin(), currentThreads
.end(), tid
);
563 return (isCurrent
!= currentThreads
.end());
567 InOrderCPU::addToCurrentThreads(ThreadID tid
)
569 if (!isThreadInCPU(tid
)) {
570 DPRINTF(InOrderCPU
, "Adding Thread %i to current threads list in CPU.\n",
572 currentThreads
.push_back(tid
);
577 InOrderCPU::removeFromCurrentThreads(ThreadID tid
)
579 if (isThreadInCPU(tid
)) {
581 "Adding Thread %i to current threads list in CPU.\n", tid
);
582 list
<ThreadID
>::iterator isCurrent
=
583 std::find(currentThreads
.begin(), currentThreads
.end(), tid
);
584 currentThreads
.erase(isCurrent
);
589 InOrderCPU::isThreadSuspended(ThreadID tid
)
591 list
<ThreadID
>::iterator isSuspended
=
592 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
594 return (isSuspended
!= suspendedThreads
.end());
598 InOrderCPU::enableVirtProcElement(unsigned vpe
)
600 DPRINTF(InOrderCPU
, "[vpe:%i]: Scheduling "
601 "Enabling of concurrent virtual processor execution",
604 scheduleCpuEvent(EnableVPEs
, NoFault
, 0/*tid*/, vpe
);
608 InOrderCPU::enableVPEs(unsigned vpe
)
610 DPRINTF(InOrderCPU
, "[vpe:%i]: Enabling Concurrent Execution "
611 "virtual processors %i", vpe
);
613 list
<ThreadID
>::iterator thread_it
= currentThreads
.begin();
615 while (thread_it
!= currentThreads
.end()) {
616 if (!isThreadSuspended(*thread_it
)) {
617 activateThread(*thread_it
);
624 InOrderCPU::disableVirtProcElement(ThreadID tid
, unsigned vpe
)
626 DPRINTF(InOrderCPU
, "[vpe:%i]: Scheduling "
627 "Disabling of concurrent virtual processor execution",
630 scheduleCpuEvent(DisableVPEs
, NoFault
, 0/*tid*/, vpe
);
634 InOrderCPU::disableVPEs(ThreadID tid
, unsigned vpe
)
636 DPRINTF(InOrderCPU
, "[vpe:%i]: Disabling Concurrent Execution of "
637 "virtual processors %i", vpe
);
639 unsigned base_vpe
= TheISA::getVirtProcNum(tcBase(tid
));
641 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
643 vector
<list
<ThreadID
>::iterator
> removeList
;
645 while (thread_it
!= activeThreads
.end()) {
646 if (base_vpe
!= vpe
) {
647 removeList
.push_back(thread_it
);
652 for (int i
= 0; i
< removeList
.size(); i
++) {
653 activeThreads
.erase(removeList
[i
]);
658 InOrderCPU::enableMultiThreading(unsigned vpe
)
660 // Schedule event to take place at end of cycle
661 DPRINTF(InOrderCPU
, "[vpe:%i]: Scheduling Enable Multithreading on "
662 "virtual processor %i", vpe
);
664 scheduleCpuEvent(EnableThreads
, NoFault
, 0/*tid*/, vpe
);
668 InOrderCPU::enableThreads(unsigned vpe
)
670 DPRINTF(InOrderCPU
, "[vpe:%i]: Enabling Multithreading on "
671 "virtual processor %i", vpe
);
673 list
<ThreadID
>::iterator thread_it
= currentThreads
.begin();
675 while (thread_it
!= currentThreads
.end()) {
676 if (TheISA::getVirtProcNum(tcBase(*thread_it
)) == vpe
) {
677 if (!isThreadSuspended(*thread_it
)) {
678 activateThread(*thread_it
);
685 InOrderCPU::disableMultiThreading(ThreadID tid
, unsigned vpe
)
687 // Schedule event to take place at end of cycle
688 DPRINTF(InOrderCPU
, "[tid:%i]: Scheduling Disable Multithreading on "
689 "virtual processor %i", tid
, vpe
);
691 scheduleCpuEvent(DisableThreads
, NoFault
, tid
, vpe
);
695 InOrderCPU::disableThreads(ThreadID tid
, unsigned vpe
)
697 DPRINTF(InOrderCPU
, "[tid:%i]: Disabling Multithreading on "
698 "virtual processor %i", tid
, vpe
);
700 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
702 vector
<list
<ThreadID
>::iterator
> removeList
;
704 while (thread_it
!= activeThreads
.end()) {
705 if (TheISA::getVirtProcNum(tcBase(*thread_it
)) == vpe
) {
706 removeList
.push_back(thread_it
);
711 for (int i
= 0; i
< removeList
.size(); i
++) {
712 activeThreads
.erase(removeList
[i
]);
717 InOrderCPU::updateThreadPriority()
719 if (activeThreads
.size() > 1)
721 //DEFAULT TO ROUND ROBIN SCHEME
722 //e.g. Move highest priority to end of thread list
723 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
724 list
<ThreadID
>::iterator list_end
= activeThreads
.end();
726 unsigned high_thread
= *list_begin
;
728 activeThreads
.erase(list_begin
);
730 activeThreads
.push_back(high_thread
);
735 InOrderCPU::tickThreadStats()
737 /** Keep track of cycles that each thread is active */
738 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
739 while (thread_it
!= activeThreads
.end()) {
740 threadCycles
[*thread_it
]++;
744 // Keep track of cycles where SMT is active
745 if (activeThreads
.size() > 1) {
751 InOrderCPU::activateContext(ThreadID tid
, int delay
)
753 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
755 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, 0/*vpe*/, delay
);
757 // Be sure to signal that there's some activity so the CPU doesn't
758 // deschedule itself.
759 activityRec
.activity();
766 InOrderCPU::suspendContext(ThreadID tid
, int delay
)
768 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, 0/*vpe*/, delay
);
773 InOrderCPU::suspendThread(ThreadID tid
)
775 DPRINTF(InOrderCPU
,"[tid: %i]: Suspended ...\n", tid
);
776 deactivateThread(tid
);
780 InOrderCPU::deallocateContext(ThreadID tid
, int delay
)
782 scheduleCpuEvent(DeallocateThread
, NoFault
, tid
, 0/*vpe*/, delay
);
786 InOrderCPU::deallocateThread(ThreadID tid
)
788 DPRINTF(InOrderCPU
,"[tid:%i]: Deallocating ...", tid
);
790 removeFromCurrentThreads(tid
);
792 deactivateThread(tid
);
794 squashThreadInPipeline(tid
);
798 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
800 //Squash all instructions in each stage
801 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
802 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
807 InOrderCPU::haltContext(ThreadID tid
, int delay
)
809 DPRINTF(InOrderCPU
, "[tid:%i]: Halt context called.\n", tid
);
811 // Halt is same thing as deallocate for now
812 // @TODO: Differentiate between halt & deallocate in the CPU
814 deallocateContext(tid
, delay
);
818 InOrderCPU::insertThread(ThreadID tid
)
820 panic("Unimplemented Function\n.");
824 InOrderCPU::removeThread(ThreadID tid
)
826 DPRINTF(InOrderCPU
, "Removing Thread %i from CPU.\n", tid
);
828 /** Broadcast to CPU resources*/
832 InOrderCPU::getPipeStage(int stage_num
)
834 return pipelineStage
[stage_num
];
839 InOrderCPU::activateWhenReady(ThreadID tid
)
841 panic("Unimplemented Function\n.");
846 InOrderCPU::readPC(ThreadID tid
)
853 InOrderCPU::setPC(Addr new_PC
, ThreadID tid
)
860 InOrderCPU::readNextPC(ThreadID tid
)
867 InOrderCPU::setNextPC(uint64_t new_NPC
, ThreadID tid
)
869 nextPC
[tid
] = new_NPC
;
874 InOrderCPU::readNextNPC(ThreadID tid
)
881 InOrderCPU::setNextNPC(uint64_t new_NNPC
, ThreadID tid
)
883 nextNPC
[tid
] = new_NNPC
;
887 InOrderCPU::readIntReg(int reg_idx
, ThreadID tid
)
889 return intRegFile
[tid
].readReg(reg_idx
);
893 InOrderCPU::readFloatReg(int reg_idx
, ThreadID tid
)
895 return floatRegs
.f
[tid
][reg_idx
];
899 InOrderCPU::readFloatRegBits(int reg_idx
, ThreadID tid
)
901 return floatRegs
.i
[tid
][reg_idx
];
905 InOrderCPU::setIntReg(int reg_idx
, uint64_t val
, ThreadID tid
)
907 intRegFile
[tid
].setReg(reg_idx
, val
);
912 InOrderCPU::setFloatReg(int reg_idx
, FloatReg val
, ThreadID tid
)
914 floatRegs
.f
[tid
][reg_idx
] = val
;
919 InOrderCPU::setFloatRegBits(int reg_idx
, FloatRegBits val
, ThreadID tid
)
921 floatRegs
.i
[tid
][reg_idx
] = val
;
925 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
927 // If Default value is set, then retrieve target thread
928 if (tid
== InvalidThreadID
) {
929 tid
= TheISA::getTargetThread(tcBase(tid
));
932 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
933 return readIntReg(reg_idx
, tid
);
934 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
935 reg_idx
-= FP_Base_DepTag
;
936 return readFloatRegBits(reg_idx
, tid
);
938 reg_idx
-= Ctrl_Base_DepTag
;
939 return readMiscReg(reg_idx
, tid
); // Misc. Register File
943 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
946 // If Default value is set, then retrieve target thread
947 if (tid
== InvalidThreadID
) {
948 tid
= TheISA::getTargetThread(tcBase(tid
));
951 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
952 setIntReg(reg_idx
, val
, tid
);
953 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
954 reg_idx
-= FP_Base_DepTag
;
955 setFloatRegBits(reg_idx
, val
, tid
);
957 reg_idx
-= Ctrl_Base_DepTag
;
958 setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
963 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
965 return isa
[tid
].readMiscRegNoEffect(misc_reg
);
969 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
971 return isa
[tid
].readMiscReg(misc_reg
, tcBase(tid
));
975 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
977 isa
[tid
].setMiscRegNoEffect(misc_reg
, val
);
981 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
983 isa
[tid
].setMiscReg(misc_reg
, val
, tcBase(tid
));
988 InOrderCPU::addInst(DynInstPtr
&inst
)
990 ThreadID tid
= inst
->readTid();
992 instList
[tid
].push_back(inst
);
994 return --(instList
[tid
].end());
998 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1000 // Set the CPU's PCs - This contributes to the precise state of the CPU which can be used
1001 // when restoring a thread to the CPU after a fork or after an exception
1002 // @TODO: Set-Up Grad-Info/Committed-Info to let ThreadState know if it's a branch or not
1003 setPC(inst
->readPC(), tid
);
1004 setNextPC(inst
->readNextPC(), tid
);
1005 setNextNPC(inst
->readNextNPC(), tid
);
1007 // Finalize Trace Data For Instruction
1008 if (inst
->traceData
) {
1009 //inst->traceData->setCycle(curTick);
1010 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1011 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1012 inst
->traceData
->dump();
1013 delete inst
->traceData
;
1014 inst
->traceData
= NULL
;
1017 // Set Last Graduated Instruction In Thread State
1018 //thread[tid]->lastGradInst = inst;
1020 // Increment thread-state's instruction count
1021 thread
[tid
]->numInst
++;
1023 // Increment thread-state's instruction stats
1024 thread
[tid
]->numInsts
++;
1026 // Count committed insts per thread stats
1027 committedInsts
[tid
]++;
1029 // Count total insts committed stat
1030 totalCommittedInsts
++;
1032 // Count SMT-committed insts per thread stat
1033 if (numActiveThreads() > 1) {
1034 smtCommittedInsts
[tid
]++;
1037 // Check for instruction-count-based events.
1038 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numInst
);
1040 // Broadcast to other resources an instruction
1041 // has been completed
1042 resPool
->scheduleEvent((CPUEventType
)ResourcePool::InstGraduated
, inst
, tid
);
1044 // Finally, remove instruction from CPU
1049 InOrderCPU::addToRemoveList(DynInstPtr
&inst
)
1051 removeInstsThisCycle
= true;
1053 removeList
.push(inst
->getInstListIt());
1057 InOrderCPU::removeInst(DynInstPtr
&inst
)
1059 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %#x "
1061 inst
->threadNumber
, inst
->readPC(), inst
->seqNum
);
1063 removeInstsThisCycle
= true;
1065 // Remove the instruction.
1066 removeList
.push(inst
->getInstListIt());
1070 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1072 //assert(!instList[tid].empty());
1074 removeInstsThisCycle
= true;
1076 ListIt inst_iter
= instList
[tid
].end();
1080 DPRINTF(InOrderCPU
, "Deleting instructions from CPU instruction "
1081 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1082 tid
, seq_num
, (*inst_iter
)->seqNum
);
1084 while ((*inst_iter
)->seqNum
> seq_num
) {
1086 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1088 squashInstIt(inst_iter
, tid
);
1099 InOrderCPU::squashInstIt(const ListIt
&instIt
, ThreadID tid
)
1101 if ((*instIt
)->threadNumber
== tid
) {
1102 DPRINTF(InOrderCPU
, "Squashing instruction, "
1103 "[tid:%i] [sn:%lli] PC %#x\n",
1104 (*instIt
)->threadNumber
,
1106 (*instIt
)->readPC());
1108 (*instIt
)->setSquashed();
1110 removeList
.push(instIt
);
1116 InOrderCPU::cleanUpRemovedInsts()
1118 while (!removeList
.empty()) {
1119 DPRINTF(InOrderCPU
, "Removing instruction, "
1120 "[tid:%i] [sn:%lli] PC %#x\n",
1121 (*removeList
.front())->threadNumber
,
1122 (*removeList
.front())->seqNum
,
1123 (*removeList
.front())->readPC());
1125 DynInstPtr inst
= *removeList
.front();
1126 ThreadID tid
= inst
->threadNumber
;
1128 // Make Sure Resource Schedule Is Emptied Out
1129 ThePipeline::ResSchedule
*inst_sched
= &inst
->resSched
;
1130 while (!inst_sched
->empty()) {
1131 ThePipeline::ScheduleEntry
* sch_entry
= inst_sched
->top();
1136 // Remove From Register Dependency Map, If Necessary
1137 archRegDepMap
[(*removeList
.front())->threadNumber
].
1138 remove((*removeList
.front()));
1141 // Clear if Non-Speculative
1142 if (inst
->staticInst
&&
1143 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1144 nonSpecInstActive
[tid
] == true) {
1145 nonSpecInstActive
[tid
] = false;
1148 instList
[tid
].erase(removeList
.front());
1152 DPRINTF(RefCount
, "pop from remove list: [sn:%i]: Refcount = %i.\n",
1154 0/*inst->curCount()*/);
1158 removeInstsThisCycle
= false;
1162 InOrderCPU::cleanUpRemovedReqs()
1164 while (!reqRemoveList
.empty()) {
1165 ResourceRequest
*res_req
= reqRemoveList
.front();
1167 DPRINTF(RefCount
, "[tid:%i]: Removing Request, "
1168 "[sn:%lli] [slot:%i] [stage_num:%i] [res:%s] [refcount:%i].\n",
1169 res_req
->inst
->threadNumber
,
1170 res_req
->inst
->seqNum
,
1172 res_req
->getStageNum(),
1173 res_req
->res
->name(),
1174 0/*res_req->inst->curCount()*/);
1176 reqRemoveList
.pop();
1180 DPRINTF(RefCount
, "after remove request: [sn:%i]: Refcount = %i.\n",
1181 res_req
->inst
->seqNum
,
1182 0/*res_req->inst->curCount()*/);
1187 InOrderCPU::cleanUpRemovedEvents()
1189 while (!cpuEventRemoveList
.empty()) {
1190 Event
*cpu_event
= cpuEventRemoveList
.front();
1191 cpuEventRemoveList
.pop();
1198 InOrderCPU::dumpInsts()
1202 ListIt inst_list_it
= instList
[0].begin();
1204 cprintf("Dumping Instruction List\n");
1206 while (inst_list_it
!= instList
[0].end()) {
1207 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1209 num
, (*inst_list_it
)->readPC(), (*inst_list_it
)->threadNumber
,
1210 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1211 (*inst_list_it
)->isSquashed());
1218 InOrderCPU::wakeCPU()
1220 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1221 DPRINTF(Activity
, "CPU already running.\n");
1225 DPRINTF(Activity
, "Waking up CPU\n");
1227 //@todo: figure out how to count idleCycles correctly
1228 //idleCycles += (curTick - 1) - lastRunningCycle;
1230 mainEventQueue
.schedule(&tickEvent
, curTick
);
1234 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1236 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1238 DPRINTF(Activity
,"Activity: syscall() called.\n");
1240 // Temporarily increase this by one to account for the syscall
1242 ++(this->thread
[tid
]->funcExeInst
);
1244 // Execute the actual syscall.
1245 this->thread
[tid
]->syscall(callnum
);
1247 // Decrease funcExeInst by one as the normal commit will handle
1249 --(this->thread
[tid
]->funcExeInst
);
1251 // Clear Non-Speculative Block Variable
1252 nonSpecInstActive
[tid
] = false;
1256 InOrderCPU::prefetch(DynInstPtr inst
)
1258 Resource
*mem_res
= resPool
->getResource(dataPortIdx
);
1259 return mem_res
->prefetch(inst
);
1263 InOrderCPU::writeHint(DynInstPtr inst
)
1265 Resource
*mem_res
= resPool
->getResource(dataPortIdx
);
1266 return mem_res
->writeHint(inst
);
1271 InOrderCPU::getITBPtr()
1273 CacheUnit
*itb_res
=
1274 dynamic_cast<CacheUnit
*>(resPool
->getResource(fetchPortIdx
));
1275 return itb_res
->tlb();
1280 InOrderCPU::getDTBPtr()
1282 CacheUnit
*dtb_res
=
1283 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1284 return dtb_res
->tlb();
1289 InOrderCPU::read(DynInstPtr inst
, Addr addr
, T
&data
, unsigned flags
)
1291 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1292 // you want to run w/out caches?
1293 CacheUnit
*cache_res
= dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1295 return cache_res
->read(inst
, addr
, data
, flags
);
1298 #ifndef DOXYGEN_SHOULD_SKIP_THIS
1302 InOrderCPU::read(DynInstPtr inst
, Addr addr
, Twin32_t
&data
, unsigned flags
);
1306 InOrderCPU::read(DynInstPtr inst
, Addr addr
, Twin64_t
&data
, unsigned flags
);
1310 InOrderCPU::read(DynInstPtr inst
, Addr addr
, uint64_t &data
, unsigned flags
);
1314 InOrderCPU::read(DynInstPtr inst
, Addr addr
, uint32_t &data
, unsigned flags
);
1318 InOrderCPU::read(DynInstPtr inst
, Addr addr
, uint16_t &data
, unsigned flags
);
1322 InOrderCPU::read(DynInstPtr inst
, Addr addr
, uint8_t &data
, unsigned flags
);
1324 #endif //DOXYGEN_SHOULD_SKIP_THIS
1328 InOrderCPU::read(DynInstPtr inst
, Addr addr
, double &data
, unsigned flags
)
1330 return read(inst
, addr
, *(uint64_t*)&data
, flags
);
1335 InOrderCPU::read(DynInstPtr inst
, Addr addr
, float &data
, unsigned flags
)
1337 return read(inst
, addr
, *(uint32_t*)&data
, flags
);
1343 InOrderCPU::read(DynInstPtr inst
, Addr addr
, int32_t &data
, unsigned flags
)
1345 return read(inst
, addr
, (uint32_t&)data
, flags
);
1350 InOrderCPU::write(DynInstPtr inst
, T data
, Addr addr
, unsigned flags
,
1351 uint64_t *write_res
)
1353 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1354 // you want to run w/out caches?
1355 CacheUnit
*cache_res
=
1356 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1357 return cache_res
->write(inst
, data
, addr
, flags
, write_res
);
1360 #ifndef DOXYGEN_SHOULD_SKIP_THIS
1364 InOrderCPU::write(DynInstPtr inst
, Twin32_t data
, Addr addr
,
1365 unsigned flags
, uint64_t *res
);
1369 InOrderCPU::write(DynInstPtr inst
, Twin64_t data
, Addr addr
,
1370 unsigned flags
, uint64_t *res
);
1374 InOrderCPU::write(DynInstPtr inst
, uint64_t data
, Addr addr
,
1375 unsigned flags
, uint64_t *res
);
1379 InOrderCPU::write(DynInstPtr inst
, uint32_t data
, Addr addr
,
1380 unsigned flags
, uint64_t *res
);
1384 InOrderCPU::write(DynInstPtr inst
, uint16_t data
, Addr addr
,
1385 unsigned flags
, uint64_t *res
);
1389 InOrderCPU::write(DynInstPtr inst
, uint8_t data
, Addr addr
,
1390 unsigned flags
, uint64_t *res
);
1392 #endif //DOXYGEN_SHOULD_SKIP_THIS
1396 InOrderCPU::write(DynInstPtr inst
, double data
, Addr addr
, unsigned flags
, uint64_t *res
)
1398 return write(inst
, *(uint64_t*)&data
, addr
, flags
, res
);
1403 InOrderCPU::write(DynInstPtr inst
, float data
, Addr addr
, unsigned flags
, uint64_t *res
)
1405 return write(inst
, *(uint32_t*)&data
, addr
, flags
, res
);
1411 InOrderCPU::write(DynInstPtr inst
, int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
1413 return write(inst
, (uint32_t)data
, addr
, flags
, res
);