src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <algorithm>
  33
  34 #include "arch/utility.hh"
  35 #include "base/bigint.hh"
  36 #include "config/full_system.hh"
  37 #include "config/the_isa.hh"
  38 #include "cpu/inorder/resources/resource_list.hh"
  39 #include "cpu/inorder/cpu.hh"
  40 #include "cpu/inorder/first_stage.hh"
  41 #include "cpu/inorder/inorder_dyn_inst.hh"
  42 #include "cpu/inorder/pipeline_traits.hh"
  43 #include "cpu/inorder/resource_pool.hh"
  44 #include "cpu/inorder/thread_context.hh"
  45 #include "cpu/inorder/thread_state.hh"
  46 #include "cpu/activity.hh"
  47 #include "cpu/base.hh"
  48 #include "cpu/exetrace.hh"
  49 #include "cpu/simple_thread.hh"
  50 #include "cpu/thread_context.hh"
  51 #include "debug/Activity.hh"
  52 #include "debug/InOrderCPU.hh"
  53 #include "debug/RefCount.hh"
  54 #include "debug/SkedCache.hh"
  55 #include "mem/translating_port.hh"
  56 #include "params/InOrderCPU.hh"
  57 #include "sim/process.hh"
  58 #include "sim/stat_control.hh"
  59
  60 #if FULL_SYSTEM
  61 #include "cpu/quiesce_event.hh"
  62 #include "sim/system.hh"
  63 #endif
  64
  65 #if THE_ISA == ALPHA_ISA
  66 #include "arch/alpha/osfpal.hh"
  67 #endif
  68
  69 using namespace std;
  70 using namespace TheISA;
  71 using namespace ThePipeline;
  72
  73 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
  74   : Event(CPU_Tick_Pri), cpu(c)
  75 { }
  76
  77
  78 void
  79 InOrderCPU::TickEvent::process()
  80 {
  81     cpu->tick();
  82 }
  83
  84
  85 const char *
  86 InOrderCPU::TickEvent::description()
  87 {
  88     return "InOrderCPU tick event";
  89 }
  90
  91 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
  92                                Fault fault, ThreadID _tid, DynInstPtr inst,
  93                                unsigned event_pri_offset)
  94     : Event(Event::Priority((unsigned int)CPU_Tick_Pri + event_pri_offset)),
  95       cpu(_cpu)
  96 {
  97     setEvent(e_type, fault, _tid, inst);
  98 }
  99
 100
 101 std::string InOrderCPU::eventNames[NumCPUEvents] =
 102 {
 103     "ActivateThread",
 104     "ActivateNextReadyThread",
 105     "DeactivateThread",
 106     "HaltThread",
 107     "SuspendThread",
 108     "Trap",
 109     "InstGraduated",
 110     "SquashFromMemStall",
 111     "UpdatePCs"
 112 };
 113
 114 void
 115 InOrderCPU::CPUEvent::process()
 116 {
 117     switch (cpuEventType)
 118     {
 119       case ActivateThread:
 120         cpu->activateThread(tid);
 121         break;
 122
 123       case ActivateNextReadyThread:
 124         cpu->activateNextReadyThread();
 125         break;
 126
 127       case DeactivateThread:
 128         cpu->deactivateThread(tid);
 129         break;
 130
 131       case HaltThread:
 132         cpu->haltThread(tid);
 133         break;
 134
 135       case SuspendThread:
 136         cpu->suspendThread(tid);
 137         break;
 138
 139       case SquashFromMemStall:
 140         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 141         break;
 142
 143       case Trap:
 144         cpu->trapCPU(fault, tid, inst);
 145         break;
 146
 147       default:
 148         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 149     }
 150
 151     cpu->cpuEventRemoveList.push(this);
 152 }
 153
 154
 155
 156 const char *
 157 InOrderCPU::CPUEvent::description()
 158 {
 159     return "InOrderCPU event";
 160 }
 161
 162 void
 163 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 164 {
 165     assert(!scheduled() || squashed());
 166     cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
 167 }
 168
 169 void
 170 InOrderCPU::CPUEvent::unscheduleEvent()
 171 {
 172     if (scheduled())
 173         squash();
 174 }
 175
 176 InOrderCPU::InOrderCPU(Params *params)
 177     : BaseCPU(params),
 178       cpu_id(params->cpu_id),
 179       coreType("default"),
 180       _status(Idle),
 181       tickEvent(this),
 182       stageWidth(params->stageWidth),
 183       timeBuffer(2 , 2),
 184       removeInstsThisCycle(false),
 185       activityRec(params->name, NumStages, 10, params->activity),
 186 #if FULL_SYSTEM
 187       system(params->system),
 188       physmem(system->physmem),
 189 #endif // FULL_SYSTEM
 190 #ifdef DEBUG
 191       cpuEventNum(0),
 192       resReqCount(0),
 193 #endif // DEBUG
 194       switchCount(0),
 195       deferRegistration(false/*params->deferRegistration*/),
 196       stageTracing(params->stageTracing),
 197       instsPerSwitch(0)
 198 {
 199     ThreadID active_threads;
 200     cpu_params = params;
 201
 202     resPool = new ResourcePool(this, params);
 203
 204     // Resize for Multithreading CPUs
 205     thread.resize(numThreads);
 206
 207 #if FULL_SYSTEM
 208     active_threads = 1;
 209 #else
 210     active_threads = params->workload.size();
 211
 212     if (active_threads > MaxThreads) {
 213         panic("Workload Size too large. Increase the 'MaxThreads'"
 214               "in your InOrder implementation or "
 215               "edit your workload size.");
 216     }
 217
 218
 219     if (active_threads > 1) {
 220         threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 221
 222         if (threadModel == SMT) {
 223             DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 224         } else if (threadModel == SwitchOnCacheMiss) {
 225             DPRINTF(InOrderCPU, "Setting Thread Model to "
 226                     "Switch On Cache Miss\n");
 227         }
 228
 229     } else {
 230         threadModel = Single;
 231     }
 232
 233
 234
 235 #endif
 236
 237     // Bind the fetch & data ports from the resource pool.
 238     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
 239     if (fetchPortIdx == 0) {
 240         fatal("Unable to find port to fetch instructions from.\n");
 241     }
 242
 243     dataPortIdx = resPool->getPortIdx(params->dataMemPort);
 244     if (dataPortIdx == 0) {
 245         fatal("Unable to find port for data.\n");
 246     }
 247
 248     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 249 #if FULL_SYSTEM
 250         // SMT is not supported in FS mode yet.
 251         assert(numThreads == 1);
 252         thread[tid] = new Thread(this, 0);
 253 #else
 254         if (tid < (ThreadID)params->workload.size()) {
 255             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 256                     tid, params->workload[tid]->prog_fname);
 257             thread[tid] =
 258                 new Thread(this, tid, params->workload[tid]);
 259         } else {
 260             //Allocate Empty thread so M5 can use later
 261             //when scheduling threads to CPU
 262             Process* dummy_proc = params->workload[0];
 263             thread[tid] = new Thread(this, tid, dummy_proc);
 264         }
 265
 266         // Eventually set this with parameters...
 267         asid[tid] = tid;
 268 #endif
 269
 270         // Setup the TC that will serve as the interface to the threads/CPU.
 271         InOrderThreadContext *tc = new InOrderThreadContext;
 272         tc->cpu = this;
 273         tc->thread = thread[tid];
 274
 275         // Give the thread the TC.
 276         thread[tid]->tc = tc;
 277         thread[tid]->setFuncExeInst(0);
 278         globalSeqNum[tid] = 1;
 279
 280         // Add the TC to the CPU's list of TC's.
 281         this->threadContexts.push_back(tc);
 282     }
 283
 284     // Initialize TimeBuffer Stage Queues
 285     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 286         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 287         stageQueue[stNum]->id(stNum);
 288     }
 289
 290
 291     // Set Up Pipeline Stages
 292     for (int stNum=0; stNum < NumStages; stNum++) {
 293         if (stNum == 0)
 294             pipelineStage[stNum] = new FirstStage(params, stNum);
 295         else
 296             pipelineStage[stNum] = new PipelineStage(params, stNum);
 297
 298         pipelineStage[stNum]->setCPU(this);
 299         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 300         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 301
 302         // Take Care of 1st/Nth stages
 303         if (stNum > 0)
 304             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 305         if (stNum < NumStages - 1)
 306             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 307     }
 308
 309     // Initialize thread specific variables
 310     for (ThreadID tid = 0; tid < numThreads; tid++) {
 311         archRegDepMap[tid].setCPU(this);
 312
 313         nonSpecInstActive[tid] = false;
 314         nonSpecSeqNum[tid] = 0;
 315
 316         squashSeqNum[tid] = MaxAddr;
 317         lastSquashCycle[tid] = 0;
 318
 319         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 320         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 321         isa[tid].clear();
 322
 323         // Define dummy instructions and resource requests to be used.
 324         dummyInst[tid] = new InOrderDynInst(this,
 325                                             thread[tid],
 326                                             0,
 327                                             tid,
 328                                             asid[tid]);
 329
 330         dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
 331     }
 332
 333     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 334     dummyReqInst->setSquashed();
 335     dummyReqInst->resetInstCount();
 336
 337     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 338     dummyBufferInst->setSquashed();
 339     dummyBufferInst->resetInstCount();
 340
 341     endOfSkedIt = skedCache.end();
 342     frontEndSked = createFrontEndSked();
 343
 344     lastRunningCycle = curTick();
 345
 346     // Reset CPU to reset state.
 347 #if FULL_SYSTEM
 348     Fault resetFault = new ResetFault();
 349     resetFault->invoke(tcBase());
 350 #endif
 351
 352
 353     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 354     scheduleTickEvent(0);
 355 }
 356
 357 InOrderCPU::~InOrderCPU()
 358 {
 359     delete resPool;
 360
 361     SkedCacheIt sked_it = skedCache.begin();
 362     SkedCacheIt sked_end = skedCache.end();
 363
 364     while (sked_it != sked_end) {
 365         delete (*sked_it).second;
 366         sked_it++;
 367     }
 368     skedCache.clear();
 369 }
 370
 371 m5::hash_map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
 372
 373 RSkedPtr
 374 InOrderCPU::createFrontEndSked()
 375 {
 376     RSkedPtr res_sked = new ResourceSked();
 377     int stage_num = 0;
 378     StageScheduler F(res_sked, stage_num++);
 379     StageScheduler D(res_sked, stage_num++);
 380
 381     // FETCH
 382     F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
 383     F.needs(ICache, FetchUnit::InitiateFetch);
 384
 385     // DECODE
 386     D.needs(ICache, FetchUnit::CompleteFetch);
 387     D.needs(Decode, DecodeUnit::DecodeInst);
 388     D.needs(BPred, BranchPredictor::PredictBranch);
 389     D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
 390
 391
 392     DPRINTF(SkedCache, "Resource Sked created for instruction \"front_end\"\n");
 393
 394     return res_sked;
 395 }
 396
 397 RSkedPtr
 398 InOrderCPU::createBackEndSked(DynInstPtr inst)
 399 {
 400     RSkedPtr res_sked = lookupSked(inst);
 401     if (res_sked != NULL) {
 402         DPRINTF(SkedCache, "Found %s in sked cache.\n",
 403                 inst->instName());
 404         return res_sked;
 405     } else {
 406         res_sked = new ResourceSked();
 407     }
 408
 409     int stage_num = ThePipeline::BackEndStartStage;
 410     StageScheduler X(res_sked, stage_num++);
 411     StageScheduler M(res_sked, stage_num++);
 412     StageScheduler W(res_sked, stage_num++);
 413
 414     if (!inst->staticInst) {
 415         warn_once("Static Instruction Object Not Set. Can't Create"
 416                   " Back End Schedule");
 417         return NULL;
 418     }
 419
 420     // EXECUTE
 421     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 422         if (!idx || !inst->isStore()) {
 423             X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
 424         }
 425     }
 426
 427     if ( inst->isNonSpeculative() ) {
 428         // skip execution of non speculative insts until later
 429     } else if ( inst->isMemRef() ) {
 430         if ( inst->isLoad() ) {
 431             X.needs(AGEN, AGENUnit::GenerateAddr);
 432         }
 433     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 434         X.needs(MDU, MultDivUnit::StartMultDiv);
 435     } else {
 436         X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 437     }
 438
 439     if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 440         X.needs(MDU, MultDivUnit::EndMultDiv);
 441     }
 442
 443     // MEMORY
 444     if ( inst->isLoad() ) {
 445         M.needs(DCache, CacheUnit::InitiateReadData);
 446     } else if ( inst->isStore() ) {
 447         if ( inst->numSrcRegs() >= 2 ) {
 448             M.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 449         }
 450         M.needs(AGEN, AGENUnit::GenerateAddr);
 451         M.needs(DCache, CacheUnit::InitiateWriteData);
 452     }
 453
 454
 455     // WRITEBACK
 456     if ( inst->isLoad() ) {
 457         W.needs(DCache, CacheUnit::CompleteReadData);
 458     } else if ( inst->isStore() ) {
 459         W.needs(DCache, CacheUnit::CompleteWriteData);
 460     }
 461
 462     if ( inst->isNonSpeculative() ) {
 463         if ( inst->isMemRef() ) fatal("Non-Speculative Memory Instruction");
 464         W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 465     }
 466
 467     W.needs(Grad, GraduationUnit::GraduateInst);
 468
 469     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 470         W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
 471     }
 472
 473     // Insert Back Schedule into our cache of
 474     // resource schedules
 475     addToSkedCache(inst, res_sked);
 476
 477     DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
 478             inst->instName(), inst->getMachInst());
 479     res_sked->print();
 480
 481     return res_sked;
 482 }
 483
 484 void
 485 InOrderCPU::regStats()
 486 {
 487     /* Register the Resource Pool's stats here.*/
 488     resPool->regStats();
 489
 490     /* Register for each Pipeline Stage */
 491     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 492         pipelineStage[stage_num]->regStats();
 493     }
 494
 495     /* Register any of the InOrderCPU's stats here.*/
 496     instsPerCtxtSwitch
 497         .name(name() + ".instsPerContextSwitch")
 498         .desc("Instructions Committed Per Context Switch")
 499         .prereq(instsPerCtxtSwitch);
 500
 501     numCtxtSwitches
 502         .name(name() + ".contextSwitches")
 503         .desc("Number of context switches");
 504
 505     comLoads
 506         .name(name() + ".comLoads")
 507         .desc("Number of Load instructions committed");
 508
 509     comStores
 510         .name(name() + ".comStores")
 511         .desc("Number of Store instructions committed");
 512
 513     comBranches
 514         .name(name() + ".comBranches")
 515         .desc("Number of Branches instructions committed");
 516
 517     comNops
 518         .name(name() + ".comNops")
 519         .desc("Number of Nop instructions committed");
 520
 521     comNonSpec
 522         .name(name() + ".comNonSpec")
 523         .desc("Number of Non-Speculative instructions committed");
 524
 525     comInts
 526         .name(name() + ".comInts")
 527         .desc("Number of Integer instructions committed");
 528
 529     comFloats
 530         .name(name() + ".comFloats")
 531         .desc("Number of Floating Point instructions committed");
 532
 533     timesIdled
 534         .name(name() + ".timesIdled")
 535         .desc("Number of times that the entire CPU went into an idle state and"
 536               " unscheduled itself")
 537         .prereq(timesIdled);
 538
 539     idleCycles
 540         .name(name() + ".idleCycles")
 541         .desc("Number of cycles cpu's stages were not processed");
 542
 543     runCycles
 544         .name(name() + ".runCycles")
 545         .desc("Number of cycles cpu stages are processed.");
 546
 547     activity
 548         .name(name() + ".activity")
 549         .desc("Percentage of cycles cpu is active")
 550         .precision(6);
 551     activity = (runCycles / numCycles) * 100;
 552
 553     threadCycles
 554         .init(numThreads)
 555         .name(name() + ".threadCycles")
 556         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 557
 558     smtCycles
 559         .name(name() + ".smtCycles")
 560         .desc("Total number of cycles that the CPU was in SMT-mode");
 561
 562     committedInsts
 563         .init(numThreads)
 564         .name(name() + ".committedInsts")
 565         .desc("Number of Instructions Simulated (Per-Thread)");
 566
 567     smtCommittedInsts
 568         .init(numThreads)
 569         .name(name() + ".smtCommittedInsts")
 570         .desc("Number of SMT Instructions Simulated (Per-Thread)");
 571
 572     totalCommittedInsts
 573         .name(name() + ".committedInsts_total")
 574         .desc("Number of Instructions Simulated (Total)");
 575
 576     cpi
 577         .name(name() + ".cpi")
 578         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 579         .precision(6);
 580     cpi = numCycles / committedInsts;
 581
 582     smtCpi
 583         .name(name() + ".smt_cpi")
 584         .desc("CPI: Total SMT-CPI")
 585         .precision(6);
 586     smtCpi = smtCycles / smtCommittedInsts;
 587
 588     totalCpi
 589         .name(name() + ".cpi_total")
 590         .desc("CPI: Total CPI of All Threads")
 591         .precision(6);
 592     totalCpi = numCycles / totalCommittedInsts;
 593
 594     ipc
 595         .name(name() + ".ipc")
 596         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 597         .precision(6);
 598     ipc =  committedInsts / numCycles;
 599
 600     smtIpc
 601         .name(name() + ".smt_ipc")
 602         .desc("IPC: Total SMT-IPC")
 603         .precision(6);
 604     smtIpc = smtCommittedInsts / smtCycles;
 605
 606     totalIpc
 607         .name(name() + ".ipc_total")
 608         .desc("IPC: Total IPC of All Threads")
 609         .precision(6);
 610         totalIpc =  totalCommittedInsts / numCycles;
 611
 612     BaseCPU::regStats();
 613 }
 614
 615
 616 void
 617 InOrderCPU::tick()
 618 {
 619     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 620
 621     ++numCycles;
 622
 623     bool pipes_idle = true;
 624
 625     //Tick each of the stages
 626     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 627         pipelineStage[stNum]->tick();
 628
 629         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 630     }
 631
 632     if (pipes_idle)
 633         idleCycles++;
 634     else
 635         runCycles++;
 636
 637     // Now advance the time buffers one tick
 638     timeBuffer.advance();
 639     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 640         stageQueue[sqNum]->advance();
 641     }
 642     activityRec.advance();
 643
 644     // Any squashed events, or insts then remove them now
 645     cleanUpRemovedEvents();
 646     cleanUpRemovedInsts();
 647
 648     // Re-schedule CPU for this cycle
 649     if (!tickEvent.scheduled()) {
 650         if (_status == SwitchedOut) {
 651             // increment stat
 652             lastRunningCycle = curTick();
 653         } else if (!activityRec.active()) {
 654             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 655             lastRunningCycle = curTick();
 656             timesIdled++;
 657         } else {
 658             //Tick next_tick = curTick() + cycles(1);
 659             //tickEvent.schedule(next_tick);
 660             schedule(&tickEvent, nextCycle(curTick() + 1));
 661             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 662                     nextCycle(curTick() + 1));
 663         }
 664     }
 665
 666     tickThreadStats();
 667     updateThreadPriority();
 668 }
 669
 670
 671 void
 672 InOrderCPU::init()
 673 {
 674     if (!deferRegistration) {
 675         registerThreadContexts();
 676     }
 677
 678     // Set inSyscall so that the CPU doesn't squash when initially
 679     // setting up registers.
 680     for (ThreadID tid = 0; tid < numThreads; ++tid)
 681         thread[tid]->inSyscall = true;
 682
 683 #if FULL_SYSTEM
 684     for (ThreadID tid = 0; tid < numThreads; tid++) {
 685         ThreadContext *src_tc = threadContexts[tid];
 686         TheISA::initCPU(src_tc, src_tc->contextId());
 687     }
 688 #endif
 689
 690     // Clear inSyscall.
 691     for (ThreadID tid = 0; tid < numThreads; ++tid)
 692         thread[tid]->inSyscall = false;
 693
 694     // Call Initializiation Routine for Resource Pool
 695     resPool->init();
 696 }
 697
 698 Port*
 699 InOrderCPU::getPort(const std::string &if_name, int idx)
 700 {
 701     return resPool->getPort(if_name, idx);
 702 }
 703
 704 #if FULL_SYSTEM
 705 Fault
 706 InOrderCPU::hwrei(ThreadID tid)
 707 {
 708     panic("hwrei: Unimplemented");
 709
 710     return NoFault;
 711 }
 712
 713
 714 bool
 715 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 716 {
 717     panic("simPalCheck: Unimplemented");
 718
 719     return true;
 720 }
 721
 722
 723 Fault
 724 InOrderCPU::getInterrupts()
 725 {
 726     // Check if there are any outstanding interrupts
 727     return interrupts->getInterrupt(threadContexts[0]);
 728 }
 729
 730
 731 void
 732 InOrderCPU::processInterrupts(Fault interrupt)
 733 {
 734     // Check for interrupts here.  For now can copy the code that
 735     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 736     // is the one that handles the interrupts.
 737     // @todo: Possibly consolidate the interrupt checking code.
 738     // @todo: Allow other threads to handle interrupts.
 739
 740     assert(interrupt != NoFault);
 741     interrupts->updateIntrInfo(threadContexts[0]);
 742
 743     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 744
 745     // Note: Context ID ok here? Impl. of FS mode needs to revisit this
 746     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 747 }
 748
 749
 750 void
 751 InOrderCPU::updateMemPorts()
 752 {
 753     // Update all ThreadContext's memory ports (Functional/Virtual
 754     // Ports)
 755     ThreadID size = thread.size();
 756     for (ThreadID i = 0; i < size; ++i)
 757         thread[i]->connectMemPorts(thread[i]->getTC());
 758 }
 759 #endif
 760
 761 void
 762 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 763 {
 764     //@ Squash Pipeline during TRAP
 765     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 766 }
 767
 768 void
 769 InOrderCPU::trapCPU(Fault fault, ThreadID tid, DynInstPtr inst)
 770 {
 771     fault->invoke(tcBase(tid), inst->staticInst);
 772 }
 773
 774 void
 775 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 776 {
 777     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 778 }
 779
 780
 781 void
 782 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 783                                 ThreadID tid)
 784 {
 785     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 786
 787     // Squash all instructions in each stage including
 788     // instruction that caused the squash (seq_num - 1)
 789     // NOTE: The stage bandwidth needs to be cleared so thats why
 790     //       the stalling instruction is squashed as well. The stalled
 791     //       instruction is previously placed in another intermediate buffer
 792     //       while it's stall is being handled.
 793     InstSeqNum squash_seq_num = seq_num - 1;
 794
 795     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 796         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 797     }
 798 }
 799
 800 void
 801 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 802                              ThreadID tid, DynInstPtr inst,
 803                              unsigned delay, unsigned event_pri_offset)
 804 {
 805     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 806                                        event_pri_offset);
 807
 808     Tick sked_tick = nextCycle(curTick() + ticks(delay));
 809     if (delay >= 0) {
 810         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 811                 eventNames[c_event], curTick() + delay, tid);
 812         schedule(cpu_event, sked_tick);
 813     } else {
 814         cpu_event->process();
 815         cpuEventRemoveList.push(cpu_event);
 816     }
 817
 818     // Broadcast event to the Resource Pool
 819     // Need to reset tid just in case this is a dummy instruction
 820     inst->setTid(tid);
 821     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 822 }
 823
 824 bool
 825 InOrderCPU::isThreadActive(ThreadID tid)
 826 {
 827   list<ThreadID>::iterator isActive =
 828       std::find(activeThreads.begin(), activeThreads.end(), tid);
 829
 830     return (isActive != activeThreads.end());
 831 }
 832
 833 bool
 834 InOrderCPU::isThreadReady(ThreadID tid)
 835 {
 836   list<ThreadID>::iterator isReady =
 837       std::find(readyThreads.begin(), readyThreads.end(), tid);
 838
 839     return (isReady != readyThreads.end());
 840 }
 841
 842 bool
 843 InOrderCPU::isThreadSuspended(ThreadID tid)
 844 {
 845   list<ThreadID>::iterator isSuspended =
 846       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
 847
 848     return (isSuspended != suspendedThreads.end());
 849 }
 850
 851 void
 852 InOrderCPU::activateNextReadyThread()
 853 {
 854     if (readyThreads.size() >= 1) {
 855         ThreadID ready_tid = readyThreads.front();
 856
 857         // Activate in Pipeline
 858         activateThread(ready_tid);
 859
 860         // Activate in Resource Pool
 861         resPool->activateAll(ready_tid);
 862
 863         list<ThreadID>::iterator ready_it =
 864             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
 865         readyThreads.erase(ready_it);
 866     } else {
 867         DPRINTF(InOrderCPU,
 868                 "Attempting to activate new thread, but No Ready Threads to"
 869                 "activate.\n");
 870         DPRINTF(InOrderCPU,
 871                 "Unable to switch to next active thread.\n");
 872     }
 873 }
 874
 875 void
 876 InOrderCPU::activateThread(ThreadID tid)
 877 {
 878     if (isThreadSuspended(tid)) {
 879         DPRINTF(InOrderCPU,
 880                 "Removing [tid:%i] from suspended threads list.\n", tid);
 881
 882         list<ThreadID>::iterator susp_it =
 883             std::find(suspendedThreads.begin(), suspendedThreads.end(),
 884                       tid);
 885         suspendedThreads.erase(susp_it);
 886     }
 887
 888     if (threadModel == SwitchOnCacheMiss &&
 889         numActiveThreads() == 1) {
 890         DPRINTF(InOrderCPU,
 891                 "Ignoring activation of [tid:%i], since [tid:%i] is "
 892                 "already running.\n", tid, activeThreadId());
 893
 894         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
 895                 tid);
 896
 897         readyThreads.push_back(tid);
 898
 899     } else if (!isThreadActive(tid)) {
 900         DPRINTF(InOrderCPU,
 901                 "Adding [tid:%i] to active threads list.\n", tid);
 902         activeThreads.push_back(tid);
 903
 904         activateThreadInPipeline(tid);
 905
 906         thread[tid]->lastActivate = curTick();
 907
 908         tcBase(tid)->setStatus(ThreadContext::Active);
 909
 910         wakeCPU();
 911
 912         numCtxtSwitches++;
 913     }
 914 }
 915
 916 void
 917 InOrderCPU::activateThreadInPipeline(ThreadID tid)
 918 {
 919     for (int stNum=0; stNum < NumStages; stNum++) {
 920         pipelineStage[stNum]->activateThread(tid);
 921     }
 922 }
 923
 924 void
 925 InOrderCPU::deactivateContext(ThreadID tid, int delay)
 926 {
 927     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
 928
 929     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
 930
 931     // Be sure to signal that there's some activity so the CPU doesn't
 932     // deschedule itself.
 933     activityRec.activity();
 934
 935     _status = Running;
 936 }
 937
 938 void
 939 InOrderCPU::deactivateThread(ThreadID tid)
 940 {
 941     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
 942
 943     if (isThreadActive(tid)) {
 944         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
 945                 tid);
 946         list<ThreadID>::iterator thread_it =
 947             std::find(activeThreads.begin(), activeThreads.end(), tid);
 948
 949         removePipelineStalls(*thread_it);
 950
 951         activeThreads.erase(thread_it);
 952
 953         // Ideally, this should be triggered from the
 954         // suspendContext/Thread functions
 955         tcBase(tid)->setStatus(ThreadContext::Suspended);
 956     }
 957
 958     assert(!isThreadActive(tid));
 959 }
 960
 961 void
 962 InOrderCPU::removePipelineStalls(ThreadID tid)
 963 {
 964     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
 965             tid);
 966
 967     for (int stNum = 0; stNum < NumStages ; stNum++) {
 968         pipelineStage[stNum]->removeStalls(tid);
 969     }
 970
 971 }
 972
 973 void
 974 InOrderCPU::updateThreadPriority()
 975 {
 976     if (activeThreads.size() > 1)
 977     {
 978         //DEFAULT TO ROUND ROBIN SCHEME
 979         //e.g. Move highest priority to end of thread list
 980         list<ThreadID>::iterator list_begin = activeThreads.begin();
 981         list<ThreadID>::iterator list_end   = activeThreads.end();
 982
 983         unsigned high_thread = *list_begin;
 984
 985         activeThreads.erase(list_begin);
 986
 987         activeThreads.push_back(high_thread);
 988     }
 989 }
 990
 991 inline void
 992 InOrderCPU::tickThreadStats()
 993 {
 994     /** Keep track of cycles that each thread is active */
 995     list<ThreadID>::iterator thread_it = activeThreads.begin();
 996     while (thread_it != activeThreads.end()) {
 997         threadCycles[*thread_it]++;
 998         thread_it++;
 999     }
1000
1001     // Keep track of cycles where SMT is active
1002     if (activeThreads.size() > 1) {
1003         smtCycles++;
1004     }
1005 }
1006
1007 void
1008 InOrderCPU::activateContext(ThreadID tid, int delay)
1009 {
1010     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
1011
1012
1013     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
1014
1015     // Be sure to signal that there's some activity so the CPU doesn't
1016     // deschedule itself.
1017     activityRec.activity();
1018
1019     _status = Running;
1020 }
1021
1022 void
1023 InOrderCPU::activateNextReadyContext(int delay)
1024 {
1025     DPRINTF(InOrderCPU,"Activating next ready thread\n");
1026
1027     // NOTE: Add 5 to the event priority so that we always activate
1028     // threads after we've finished deactivating, squashing,etc.
1029     // other threads
1030     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
1031                      delay, 5);
1032
1033     // Be sure to signal that there's some activity so the CPU doesn't
1034     // deschedule itself.
1035     activityRec.activity();
1036
1037     _status = Running;
1038 }
1039
1040 void
1041 InOrderCPU::haltContext(ThreadID tid, int delay)
1042 {
1043     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
1044
1045     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
1046
1047     activityRec.activity();
1048 }
1049
1050 void
1051 InOrderCPU::haltThread(ThreadID tid)
1052 {
1053     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
1054     deactivateThread(tid);
1055     squashThreadInPipeline(tid);
1056     haltedThreads.push_back(tid);
1057
1058     tcBase(tid)->setStatus(ThreadContext::Halted);
1059
1060     if (threadModel == SwitchOnCacheMiss) {
1061         activateNextReadyContext();
1062     }
1063 }
1064
1065 void
1066 InOrderCPU::suspendContext(ThreadID tid, int delay)
1067 {
1068     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
1069 }
1070
1071 void
1072 InOrderCPU::suspendThread(ThreadID tid)
1073 {
1074     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
1075             tid);
1076     deactivateThread(tid);
1077     suspendedThreads.push_back(tid);
1078     thread[tid]->lastSuspend = curTick();
1079
1080     tcBase(tid)->setStatus(ThreadContext::Suspended);
1081 }
1082
1083 void
1084 InOrderCPU::squashThreadInPipeline(ThreadID tid)
1085 {
1086     //Squash all instructions in each stage
1087     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
1088         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
1089     }
1090 }
1091
1092 PipelineStage*
1093 InOrderCPU::getPipeStage(int stage_num)
1094 {
1095     return pipelineStage[stage_num];
1096 }
1097
1098 RegIndex
1099 InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
1100 {
1101     if (reg_idx < FP_Base_DepTag) {
1102         reg_type = IntType;
1103         return isa[tid].flattenIntIndex(reg_idx);
1104     } else if (reg_idx < Ctrl_Base_DepTag) {
1105         reg_type = FloatType;
1106         reg_idx -= FP_Base_DepTag;
1107         return isa[tid].flattenFloatIndex(reg_idx);
1108     } else {
1109         reg_type = MiscType;
1110         return reg_idx - TheISA::Ctrl_Base_DepTag;
1111     }
1112 }
1113
1114 uint64_t
1115 InOrderCPU::readIntReg(RegIndex reg_idx, ThreadID tid)
1116 {
1117     DPRINTF(IntRegs, "[tid:%i]: Reading Int. Reg %i as %x\n",
1118             tid, reg_idx, intRegs[tid][reg_idx]);
1119
1120     return intRegs[tid][reg_idx];
1121 }
1122
1123 FloatReg
1124 InOrderCPU::readFloatReg(RegIndex reg_idx, ThreadID tid)
1125 {
1126     return floatRegs.f[tid][reg_idx];
1127 }
1128
1129 FloatRegBits
1130 InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
1131 {;
1132     return floatRegs.i[tid][reg_idx];
1133 }
1134
1135 void
1136 InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid)
1137 {
1138     if (reg_idx == TheISA::ZeroReg) {
1139         DPRINTF(IntRegs, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1140                 "(Int. Reg %i) to %x\n", tid, reg_idx, val);
1141         return;
1142     } else {
1143         DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
1144                 tid, reg_idx, val);
1145
1146         intRegs[tid][reg_idx] = val;
1147     }
1148 }
1149
1150
1151 void
1152 InOrderCPU::setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid)
1153 {
1154     floatRegs.f[tid][reg_idx] = val;
1155 }
1156
1157
1158 void
1159 InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid)
1160 {
1161     floatRegs.i[tid][reg_idx] = val;
1162 }
1163
1164 uint64_t
1165 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1166 {
1167     // If Default value is set, then retrieve target thread
1168     if (tid == InvalidThreadID) {
1169         tid = TheISA::getTargetThread(tcBase(tid));
1170     }
1171
1172     if (reg_idx < FP_Base_DepTag) {
1173         // Integer Register File
1174         return readIntReg(reg_idx, tid);
1175     } else if (reg_idx < Ctrl_Base_DepTag) {
1176         // Float Register File
1177         reg_idx -= FP_Base_DepTag;
1178         return readFloatRegBits(reg_idx, tid);
1179     } else {
1180         reg_idx -= Ctrl_Base_DepTag;
1181         return readMiscReg(reg_idx, tid);  // Misc. Register File
1182     }
1183 }
1184 void
1185 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1186                               ThreadID tid)
1187 {
1188     // If Default value is set, then retrieve target thread
1189     if (tid == InvalidThreadID) {
1190         tid = TheISA::getTargetThread(tcBase(tid));
1191     }
1192
1193     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1194         setIntReg(reg_idx, val, tid);
1195     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1196         reg_idx -= FP_Base_DepTag;
1197         setFloatRegBits(reg_idx, val, tid);
1198     } else {
1199         reg_idx -= Ctrl_Base_DepTag;
1200         setMiscReg(reg_idx, val, tid); // Misc. Register File
1201     }
1202 }
1203
1204 MiscReg
1205 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1206 {
1207     return isa[tid].readMiscRegNoEffect(misc_reg);
1208 }
1209
1210 MiscReg
1211 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1212 {
1213     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1214 }
1215
1216 void
1217 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1218 {
1219     isa[tid].setMiscRegNoEffect(misc_reg, val);
1220 }
1221
1222 void
1223 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1224 {
1225     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1226 }
1227
1228
1229 InOrderCPU::ListIt
1230 InOrderCPU::addInst(DynInstPtr inst)
1231 {
1232     ThreadID tid = inst->readTid();
1233
1234     instList[tid].push_back(inst);
1235
1236     return --(instList[tid].end());
1237 }
1238
1239 void
1240 InOrderCPU::updateContextSwitchStats()
1241 {
1242     // Set Average Stat Here, then reset to 0
1243     instsPerCtxtSwitch = instsPerSwitch;
1244     instsPerSwitch = 0;
1245 }
1246
1247
1248 void
1249 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1250 {
1251     // Set the CPU's PCs - This contributes to the precise state of the CPU
1252     // which can be used when restoring a thread to the CPU after after any
1253     // type of context switching activity (fork, exception, etc.)
1254     pcState(inst->pcState(), tid);
1255
1256     if (inst->isControl()) {
1257         thread[tid]->lastGradIsBranch = true;
1258         thread[tid]->lastBranchPC = inst->pcState();
1259         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1260     } else {
1261         thread[tid]->lastGradIsBranch = false;
1262     }
1263
1264
1265     // Finalize Trace Data For Instruction
1266     if (inst->traceData) {
1267         //inst->traceData->setCycle(curTick());
1268         inst->traceData->setFetchSeq(inst->seqNum);
1269         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1270         inst->traceData->dump();
1271         delete inst->traceData;
1272         inst->traceData = NULL;
1273     }
1274
1275     // Increment active thread's instruction count
1276     instsPerSwitch++;
1277
1278     // Increment thread-state's instruction count
1279     thread[tid]->numInst++;
1280
1281     // Increment thread-state's instruction stats
1282     thread[tid]->numInsts++;
1283
1284     // Count committed insts per thread stats
1285     committedInsts[tid]++;
1286
1287     // Count total insts committed stat
1288     totalCommittedInsts++;
1289
1290     // Count SMT-committed insts per thread stat
1291     if (numActiveThreads() > 1) {
1292         smtCommittedInsts[tid]++;
1293     }
1294
1295     // Instruction-Mix Stats
1296     if (inst->isLoad()) {
1297         comLoads++;
1298     } else if (inst->isStore()) {
1299         comStores++;
1300     } else if (inst->isControl()) {
1301         comBranches++;
1302     } else if (inst->isNop()) {
1303         comNops++;
1304     } else if (inst->isNonSpeculative()) {
1305         comNonSpec++;
1306     } else if (inst->isInteger()) {
1307         comInts++;
1308     } else if (inst->isFloating()) {
1309         comFloats++;
1310     }
1311
1312     // Check for instruction-count-based events.
1313     comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1314
1315     // Broadcast to other resources an instruction
1316     // has been completed
1317     resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
1318                            0, 0, tid);
1319
1320     // Finally, remove instruction from CPU
1321     removeInst(inst);
1322 }
1323
1324 // currently unused function, but substitute repetitive code w/this function
1325 // call
1326 void
1327 InOrderCPU::addToRemoveList(DynInstPtr inst)
1328 {
1329     removeInstsThisCycle = true;
1330     if (!inst->isRemoveList()) {
1331         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1332                 "[sn:%lli] to remove list\n",
1333                 inst->threadNumber, inst->pcState(), inst->seqNum);
1334         inst->setRemoveList();
1335         removeList.push(inst->getInstListIt());
1336     }  else {
1337         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1338                 "[sn:%lli], already remove list\n",
1339                 inst->threadNumber, inst->pcState(), inst->seqNum);
1340     }
1341
1342 }
1343
1344 void
1345 InOrderCPU::removeInst(DynInstPtr inst)
1346 {
1347     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1348             "[sn:%lli]\n",
1349             inst->threadNumber, inst->pcState(), inst->seqNum);
1350
1351     removeInstsThisCycle = true;
1352
1353     // Remove the instruction.
1354     if (!inst->isRemoveList()) {
1355         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1356                 "[sn:%lli] to remove list\n",
1357                 inst->threadNumber, inst->pcState(), inst->seqNum);
1358         inst->setRemoveList();
1359         removeList.push(inst->getInstListIt());
1360     } else {
1361         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1362                 "[sn:%lli], already on remove list\n",
1363                 inst->threadNumber, inst->pcState(), inst->seqNum);
1364     }
1365
1366 }
1367
1368 void
1369 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1370 {
1371     //assert(!instList[tid].empty());
1372
1373     removeInstsThisCycle = true;
1374
1375     ListIt inst_iter = instList[tid].end();
1376
1377     inst_iter--;
1378
1379     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1380             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1381             tid, seq_num, (*inst_iter)->seqNum);
1382
1383     while ((*inst_iter)->seqNum > seq_num) {
1384
1385         bool break_loop = (inst_iter == instList[tid].begin());
1386
1387         squashInstIt(inst_iter, tid);
1388
1389         inst_iter--;
1390
1391         if (break_loop)
1392             break;
1393     }
1394 }
1395
1396
1397 inline void
1398 InOrderCPU::squashInstIt(const ListIt &instIt, ThreadID tid)
1399 {
1400     if ((*instIt)->threadNumber == tid) {
1401         DPRINTF(InOrderCPU, "Squashing instruction, "
1402                 "[tid:%i] [sn:%lli] PC %s\n",
1403                 (*instIt)->threadNumber,
1404                 (*instIt)->seqNum,
1405                 (*instIt)->pcState());
1406
1407         (*instIt)->setSquashed();
1408
1409         if (!(*instIt)->isRemoveList()) {
1410             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1411                     "[sn:%lli] to remove list\n",
1412                     (*instIt)->threadNumber, (*instIt)->pcState(),
1413                     (*instIt)->seqNum);
1414             (*instIt)->setRemoveList();
1415             removeList.push(instIt);
1416         } else {
1417             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1418                     " PC %s [sn:%lli], already on remove list\n",
1419                     (*instIt)->threadNumber, (*instIt)->pcState(),
1420                     (*instIt)->seqNum);
1421         }
1422
1423     }
1424
1425 }
1426
1427
1428 void
1429 InOrderCPU::cleanUpRemovedInsts()
1430 {
1431     while (!removeList.empty()) {
1432         DPRINTF(InOrderCPU, "Removing instruction, "
1433                 "[tid:%i] [sn:%lli] PC %s\n",
1434                 (*removeList.front())->threadNumber,
1435                 (*removeList.front())->seqNum,
1436                (*removeList.front())->pcState());
1437
1438         DynInstPtr inst = *removeList.front();
1439         ThreadID tid = inst->threadNumber;
1440
1441         // Remove From Register Dependency Map, If Necessary
1442         archRegDepMap[tid].remove(inst);
1443
1444         // Clear if Non-Speculative
1445         if (inst->staticInst &&
1446             inst->seqNum == nonSpecSeqNum[tid] &&
1447             nonSpecInstActive[tid] == true) {
1448             nonSpecInstActive[tid] = false;
1449         }
1450
1451         inst->onInstList = false;
1452
1453         instList[tid].erase(removeList.front());
1454
1455         removeList.pop();
1456     }
1457
1458     removeInstsThisCycle = false;
1459 }
1460
1461 void
1462 InOrderCPU::cleanUpRemovedEvents()
1463 {
1464     while (!cpuEventRemoveList.empty()) {
1465         Event *cpu_event = cpuEventRemoveList.front();
1466         cpuEventRemoveList.pop();
1467         delete cpu_event;
1468     }
1469 }
1470
1471
1472 void
1473 InOrderCPU::dumpInsts()
1474 {
1475     int num = 0;
1476
1477     ListIt inst_list_it = instList[0].begin();
1478
1479     cprintf("Dumping Instruction List\n");
1480
1481     while (inst_list_it != instList[0].end()) {
1482         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1483                 "Squashed:%i\n\n",
1484                 num, (*inst_list_it)->pcState(),
1485                 (*inst_list_it)->threadNumber,
1486                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1487                 (*inst_list_it)->isSquashed());
1488         inst_list_it++;
1489         ++num;
1490     }
1491 }
1492
1493 void
1494 InOrderCPU::wakeCPU()
1495 {
1496     if (/*activityRec.active() || */tickEvent.scheduled()) {
1497         DPRINTF(Activity, "CPU already running.\n");
1498         return;
1499     }
1500
1501     DPRINTF(Activity, "Waking up CPU\n");
1502
1503     Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
1504
1505     idleCycles += extra_cycles;
1506     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1507         pipelineStage[stage_num]->idleCycles += extra_cycles;
1508     }
1509
1510     numCycles += extra_cycles;
1511
1512     schedule(&tickEvent, nextCycle(curTick()));
1513 }
1514
1515 #if FULL_SYSTEM
1516
1517 void
1518 InOrderCPU::wakeup()
1519 {
1520     if (thread[0]->status() != ThreadContext::Suspended)
1521         return;
1522
1523     wakeCPU();
1524
1525     DPRINTF(Quiesce, "Suspended Processor woken\n");
1526     threadContexts[0]->activate();
1527 }
1528 #endif
1529
1530 #if !FULL_SYSTEM
1531 void
1532 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1533 {
1534     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1535
1536     DPRINTF(Activity,"Activity: syscall() called.\n");
1537
1538     // Temporarily increase this by one to account for the syscall
1539     // instruction.
1540     ++(this->thread[tid]->funcExeInst);
1541
1542     // Execute the actual syscall.
1543     this->thread[tid]->syscall(callnum);
1544
1545     // Decrease funcExeInst by one as the normal commit will handle
1546     // incrementing it.
1547     --(this->thread[tid]->funcExeInst);
1548
1549     // Clear Non-Speculative Block Variable
1550     nonSpecInstActive[tid] = false;
1551 }
1552 #endif
1553
1554 TheISA::TLB*
1555 InOrderCPU::getITBPtr()
1556 {
1557     CacheUnit *itb_res =
1558         dynamic_cast<CacheUnit*>(resPool->getResource(fetchPortIdx));
1559     return itb_res->tlb();
1560 }
1561
1562
1563 TheISA::TLB*
1564 InOrderCPU::getDTBPtr()
1565 {
1566     CacheUnit *dtb_res =
1567         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1568     return dtb_res->tlb();
1569 }
1570
1571 Fault
1572 InOrderCPU::read(DynInstPtr inst, Addr addr,
1573                  uint8_t *data, unsigned size, unsigned flags)
1574 {
1575     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1576     //       you want to run w/out caches?
1577     CacheUnit *cache_res =
1578         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1579
1580     return cache_res->read(inst, addr, data, size, flags);
1581 }
1582
1583 Fault
1584 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1585                   Addr addr, unsigned flags, uint64_t *write_res)
1586 {
1587     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1588     //       you want to run w/out caches?
1589     CacheUnit *cache_res =
1590         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1591     return cache_res->write(inst, data, size, addr, flags, write_res);
1592 }