src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <algorithm>
  33
  34 #include "arch/utility.hh"
  35 #include "base/bigint.hh"
  36 #include "config/full_system.hh"
  37 #include "config/the_isa.hh"
  38 #include "cpu/inorder/resources/resource_list.hh"
  39 #include "cpu/inorder/cpu.hh"
  40 #include "cpu/inorder/first_stage.hh"
  41 #include "cpu/inorder/inorder_dyn_inst.hh"
  42 #include "cpu/inorder/pipeline_traits.hh"
  43 #include "cpu/inorder/resource_pool.hh"
  44 #include "cpu/inorder/thread_context.hh"
  45 #include "cpu/inorder/thread_state.hh"
  46 #include "cpu/activity.hh"
  47 #include "cpu/base.hh"
  48 #include "cpu/exetrace.hh"
  49 #include "cpu/simple_thread.hh"
  50 #include "cpu/thread_context.hh"
  51 #include "debug/Activity.hh"
  52 #include "debug/InOrderCPU.hh"
  53 #include "debug/RefCount.hh"
  54 #include "debug/SkedCache.hh"
  55 #include "mem/translating_port.hh"
  56 #include "params/InOrderCPU.hh"
  57 #include "sim/process.hh"
  58 #include "sim/stat_control.hh"
  59
  60 #if FULL_SYSTEM
  61 #include "cpu/quiesce_event.hh"
  62 #include "sim/system.hh"
  63 #endif
  64
  65 #if THE_ISA == ALPHA_ISA
  66 #include "arch/alpha/osfpal.hh"
  67 #endif
  68
  69 using namespace std;
  70 using namespace TheISA;
  71 using namespace ThePipeline;
  72
  73 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
  74   : Event(CPU_Tick_Pri), cpu(c)
  75 { }
  76
  77
  78 void
  79 InOrderCPU::TickEvent::process()
  80 {
  81     cpu->tick();
  82 }
  83
  84
  85 const char *
  86 InOrderCPU::TickEvent::description()
  87 {
  88     return "InOrderCPU tick event";
  89 }
  90
  91 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
  92                                Fault fault, ThreadID _tid, DynInstPtr inst,
  93                                CPUEventPri event_pri)
  94     : Event(event_pri), cpu(_cpu)
  95 {
  96     setEvent(e_type, fault, _tid, inst);
  97 }
  98
  99
 100 std::string InOrderCPU::eventNames[NumCPUEvents] =
 101 {
 102     "ActivateThread",
 103     "ActivateNextReadyThread",
 104     "DeactivateThread",
 105     "HaltThread",
 106     "SuspendThread",
 107     "Trap",
 108     "InstGraduated",
 109     "SquashFromMemStall",
 110     "UpdatePCs"
 111 };
 112
 113 void
 114 InOrderCPU::CPUEvent::process()
 115 {
 116     switch (cpuEventType)
 117     {
 118       case ActivateThread:
 119         cpu->activateThread(tid);
 120         break;
 121
 122       case ActivateNextReadyThread:
 123         cpu->activateNextReadyThread();
 124         break;
 125
 126       case DeactivateThread:
 127         cpu->deactivateThread(tid);
 128         break;
 129
 130       case HaltThread:
 131         cpu->haltThread(tid);
 132         break;
 133
 134       case SuspendThread:
 135         cpu->suspendThread(tid);
 136         break;
 137
 138       case SquashFromMemStall:
 139         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 140         break;
 141
 142       case Trap:
 143         DPRINTF(InOrderCPU, "Trapping CPU\n");
 144         cpu->trap(fault, tid, inst);
 145         cpu->resPool->trap(fault, tid, inst);
 146         break;
 147
 148       default:
 149         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 150     }
 151
 152     cpu->cpuEventRemoveList.push(this);
 153 }
 154
 155
 156
 157 const char *
 158 InOrderCPU::CPUEvent::description()
 159 {
 160     return "InOrderCPU event";
 161 }
 162
 163 void
 164 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 165 {
 166     assert(!scheduled() || squashed());
 167     cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
 168 }
 169
 170 void
 171 InOrderCPU::CPUEvent::unscheduleEvent()
 172 {
 173     if (scheduled())
 174         squash();
 175 }
 176
 177 InOrderCPU::InOrderCPU(Params *params)
 178     : BaseCPU(params),
 179       cpu_id(params->cpu_id),
 180       coreType("default"),
 181       _status(Idle),
 182       tickEvent(this),
 183       stageWidth(params->stageWidth),
 184       timeBuffer(2 , 2),
 185       removeInstsThisCycle(false),
 186       activityRec(params->name, NumStages, 10, params->activity),
 187 #if FULL_SYSTEM
 188       system(params->system),
 189       physmem(system->physmem),
 190 #endif // FULL_SYSTEM
 191 #ifdef DEBUG
 192       cpuEventNum(0),
 193       resReqCount(0),
 194 #endif // DEBUG
 195       switchCount(0),
 196       deferRegistration(false/*params->deferRegistration*/),
 197       stageTracing(params->stageTracing),
 198       instsPerSwitch(0)
 199 {
 200     ThreadID active_threads;
 201     cpu_params = params;
 202
 203     resPool = new ResourcePool(this, params);
 204
 205     // Resize for Multithreading CPUs
 206     thread.resize(numThreads);
 207
 208 #if FULL_SYSTEM
 209     active_threads = 1;
 210 #else
 211     active_threads = params->workload.size();
 212
 213     if (active_threads > MaxThreads) {
 214         panic("Workload Size too large. Increase the 'MaxThreads'"
 215               "in your InOrder implementation or "
 216               "edit your workload size.");
 217     }
 218
 219
 220     if (active_threads > 1) {
 221         threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 222
 223         if (threadModel == SMT) {
 224             DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 225         } else if (threadModel == SwitchOnCacheMiss) {
 226             DPRINTF(InOrderCPU, "Setting Thread Model to "
 227                     "Switch On Cache Miss\n");
 228         }
 229
 230     } else {
 231         threadModel = Single;
 232     }
 233
 234
 235
 236 #endif
 237
 238     // Bind the fetch & data ports from the resource pool.
 239     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
 240     if (fetchPortIdx == 0) {
 241         fatal("Unable to find port to fetch instructions from.\n");
 242     }
 243
 244     dataPortIdx = resPool->getPortIdx(params->dataMemPort);
 245     if (dataPortIdx == 0) {
 246         fatal("Unable to find port for data.\n");
 247     }
 248
 249     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 250 #if FULL_SYSTEM
 251         // SMT is not supported in FS mode yet.
 252         assert(numThreads == 1);
 253         thread[tid] = new Thread(this, 0);
 254 #else
 255         if (tid < (ThreadID)params->workload.size()) {
 256             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 257                     tid, params->workload[tid]->prog_fname);
 258             thread[tid] =
 259                 new Thread(this, tid, params->workload[tid]);
 260         } else {
 261             //Allocate Empty thread so M5 can use later
 262             //when scheduling threads to CPU
 263             Process* dummy_proc = params->workload[0];
 264             thread[tid] = new Thread(this, tid, dummy_proc);
 265         }
 266
 267         // Eventually set this with parameters...
 268         asid[tid] = tid;
 269 #endif
 270
 271         // Setup the TC that will serve as the interface to the threads/CPU.
 272         InOrderThreadContext *tc = new InOrderThreadContext;
 273         tc->cpu = this;
 274         tc->thread = thread[tid];
 275
 276         // Give the thread the TC.
 277         thread[tid]->tc = tc;
 278         thread[tid]->setFuncExeInst(0);
 279         globalSeqNum[tid] = 1;
 280
 281         // Add the TC to the CPU's list of TC's.
 282         this->threadContexts.push_back(tc);
 283     }
 284
 285     // Initialize TimeBuffer Stage Queues
 286     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 287         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 288         stageQueue[stNum]->id(stNum);
 289     }
 290
 291
 292     // Set Up Pipeline Stages
 293     for (int stNum=0; stNum < NumStages; stNum++) {
 294         if (stNum == 0)
 295             pipelineStage[stNum] = new FirstStage(params, stNum);
 296         else
 297             pipelineStage[stNum] = new PipelineStage(params, stNum);
 298
 299         pipelineStage[stNum]->setCPU(this);
 300         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 301         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 302
 303         // Take Care of 1st/Nth stages
 304         if (stNum > 0)
 305             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 306         if (stNum < NumStages - 1)
 307             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 308     }
 309
 310     // Initialize thread specific variables
 311     for (ThreadID tid = 0; tid < numThreads; tid++) {
 312         archRegDepMap[tid].setCPU(this);
 313
 314         nonSpecInstActive[tid] = false;
 315         nonSpecSeqNum[tid] = 0;
 316
 317         squashSeqNum[tid] = MaxAddr;
 318         lastSquashCycle[tid] = 0;
 319
 320         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 321         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 322         isa[tid].clear();
 323
 324         // Define dummy instructions and resource requests to be used.
 325         dummyInst[tid] = new InOrderDynInst(this,
 326                                             thread[tid],
 327                                             0,
 328                                             tid,
 329                                             asid[tid]);
 330
 331         dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
 332     }
 333
 334     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 335     dummyReqInst->setSquashed();
 336     dummyReqInst->resetInstCount();
 337
 338     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 339     dummyBufferInst->setSquashed();
 340     dummyBufferInst->resetInstCount();
 341
 342     endOfSkedIt = skedCache.end();
 343     frontEndSked = createFrontEndSked();
 344
 345     lastRunningCycle = curTick();
 346
 347     // Reset CPU to reset state.
 348 #if FULL_SYSTEM
 349     Fault resetFault = new ResetFault();
 350     resetFault->invoke(tcBase());
 351 #endif
 352
 353
 354     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 355     scheduleTickEvent(0);
 356 }
 357
 358 InOrderCPU::~InOrderCPU()
 359 {
 360     delete resPool;
 361
 362     SkedCacheIt sked_it = skedCache.begin();
 363     SkedCacheIt sked_end = skedCache.end();
 364
 365     while (sked_it != sked_end) {
 366         delete (*sked_it).second;
 367         sked_it++;
 368     }
 369     skedCache.clear();
 370 }
 371
 372 m5::hash_map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
 373
 374 RSkedPtr
 375 InOrderCPU::createFrontEndSked()
 376 {
 377     RSkedPtr res_sked = new ResourceSked();
 378     int stage_num = 0;
 379     StageScheduler F(res_sked, stage_num++);
 380     StageScheduler D(res_sked, stage_num++);
 381
 382     // FETCH
 383     F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
 384     F.needs(ICache, FetchUnit::InitiateFetch);
 385
 386     // DECODE
 387     D.needs(ICache, FetchUnit::CompleteFetch);
 388     D.needs(Decode, DecodeUnit::DecodeInst);
 389     D.needs(BPred, BranchPredictor::PredictBranch);
 390     D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
 391
 392
 393     DPRINTF(SkedCache, "Resource Sked created for instruction \"front_end\"\n");
 394
 395     return res_sked;
 396 }
 397
 398 RSkedPtr
 399 InOrderCPU::createBackEndSked(DynInstPtr inst)
 400 {
 401     RSkedPtr res_sked = lookupSked(inst);
 402     if (res_sked != NULL) {
 403         DPRINTF(SkedCache, "Found %s in sked cache.\n",
 404                 inst->instName());
 405         return res_sked;
 406     } else {
 407         res_sked = new ResourceSked();
 408     }
 409
 410     int stage_num = ThePipeline::BackEndStartStage;
 411     StageScheduler X(res_sked, stage_num++);
 412     StageScheduler M(res_sked, stage_num++);
 413     StageScheduler W(res_sked, stage_num++);
 414
 415     if (!inst->staticInst) {
 416         warn_once("Static Instruction Object Not Set. Can't Create"
 417                   " Back End Schedule");
 418         return NULL;
 419     }
 420
 421     // EXECUTE
 422     X.needs(RegManager, UseDefUnit::MarkDestRegs);
 423     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 424         if (!idx || !inst->isStore()) {
 425             X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
 426         }
 427     }
 428
 429     //@todo: schedule non-spec insts to operate on this cycle
 430     // as long as all previous insts are done
 431     if ( inst->isNonSpeculative() ) {
 432         // skip execution of non speculative insts until later
 433     } else if ( inst->isMemRef() ) {
 434         if ( inst->isLoad() ) {
 435             X.needs(AGEN, AGENUnit::GenerateAddr);
 436         }
 437     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 438         X.needs(MDU, MultDivUnit::StartMultDiv);
 439     } else {
 440         X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 441     }
 442
 443     // MEMORY
 444     if (!inst->isNonSpeculative()) {
 445         if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 446             M.needs(MDU, MultDivUnit::EndMultDiv);
 447         }
 448
 449         if ( inst->isLoad() ) {
 450             M.needs(DCache, CacheUnit::InitiateReadData);
 451             if (inst->splitInst)
 452                 M.needs(DCache, CacheUnit::InitSecondSplitRead);
 453         } else if ( inst->isStore() ) {
 454             for (int i = 1; i < inst->numSrcRegs(); i++ ) {
 455                 M.needs(RegManager, UseDefUnit::ReadSrcReg, i);
 456             }
 457             M.needs(AGEN, AGENUnit::GenerateAddr);
 458             M.needs(DCache, CacheUnit::InitiateWriteData);
 459             if (inst->splitInst)
 460                 M.needs(DCache, CacheUnit::InitSecondSplitWrite);
 461         }
 462     }
 463
 464     // WRITEBACK
 465     if (!inst->isNonSpeculative()) {
 466         if ( inst->isLoad() ) {
 467             W.needs(DCache, CacheUnit::CompleteReadData);
 468             if (inst->splitInst)
 469                 W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
 470         } else if ( inst->isStore() ) {
 471             W.needs(DCache, CacheUnit::CompleteWriteData);
 472             if (inst->splitInst)
 473                 W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
 474         }
 475     } else {
 476         // Finally, Execute Speculative Data
 477         if (inst->isMemRef()) {
 478             if (inst->isLoad()) {
 479                 W.needs(AGEN, AGENUnit::GenerateAddr);
 480                 W.needs(DCache, CacheUnit::InitiateReadData);
 481                 if (inst->splitInst)
 482                     W.needs(DCache, CacheUnit::InitSecondSplitRead);
 483                 W.needs(DCache, CacheUnit::CompleteReadData);
 484                 if (inst->splitInst)
 485                     W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
 486             } else if (inst->isStore()) {
 487                 if ( inst->numSrcRegs() >= 2 ) {
 488                     W.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 489                 }
 490                 W.needs(AGEN, AGENUnit::GenerateAddr);
 491                 W.needs(DCache, CacheUnit::InitiateWriteData);
 492                 if (inst->splitInst)
 493                     W.needs(DCache, CacheUnit::InitSecondSplitWrite);
 494                 W.needs(DCache, CacheUnit::CompleteWriteData);
 495                 if (inst->splitInst)
 496                     W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
 497             }
 498         } else {
 499             W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 500         }
 501     }
 502
 503     W.needs(Grad, GraduationUnit::GraduateInst);
 504
 505     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 506         W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
 507     }
 508
 509     // Insert Back Schedule into our cache of
 510     // resource schedules
 511     addToSkedCache(inst, res_sked);
 512
 513     DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
 514             inst->instName(), inst->getMachInst());
 515     res_sked->print();
 516
 517     return res_sked;
 518 }
 519
 520 void
 521 InOrderCPU::regStats()
 522 {
 523     /* Register the Resource Pool's stats here.*/
 524     resPool->regStats();
 525
 526     /* Register for each Pipeline Stage */
 527     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 528         pipelineStage[stage_num]->regStats();
 529     }
 530
 531     /* Register any of the InOrderCPU's stats here.*/
 532     instsPerCtxtSwitch
 533         .name(name() + ".instsPerContextSwitch")
 534         .desc("Instructions Committed Per Context Switch")
 535         .prereq(instsPerCtxtSwitch);
 536
 537     numCtxtSwitches
 538         .name(name() + ".contextSwitches")
 539         .desc("Number of context switches");
 540
 541     comLoads
 542         .name(name() + ".comLoads")
 543         .desc("Number of Load instructions committed");
 544
 545     comStores
 546         .name(name() + ".comStores")
 547         .desc("Number of Store instructions committed");
 548
 549     comBranches
 550         .name(name() + ".comBranches")
 551         .desc("Number of Branches instructions committed");
 552
 553     comNops
 554         .name(name() + ".comNops")
 555         .desc("Number of Nop instructions committed");
 556
 557     comNonSpec
 558         .name(name() + ".comNonSpec")
 559         .desc("Number of Non-Speculative instructions committed");
 560
 561     comInts
 562         .name(name() + ".comInts")
 563         .desc("Number of Integer instructions committed");
 564
 565     comFloats
 566         .name(name() + ".comFloats")
 567         .desc("Number of Floating Point instructions committed");
 568
 569     timesIdled
 570         .name(name() + ".timesIdled")
 571         .desc("Number of times that the entire CPU went into an idle state and"
 572               " unscheduled itself")
 573         .prereq(timesIdled);
 574
 575     idleCycles
 576         .name(name() + ".idleCycles")
 577         .desc("Number of cycles cpu's stages were not processed");
 578
 579     runCycles
 580         .name(name() + ".runCycles")
 581         .desc("Number of cycles cpu stages are processed.");
 582
 583     activity
 584         .name(name() + ".activity")
 585         .desc("Percentage of cycles cpu is active")
 586         .precision(6);
 587     activity = (runCycles / numCycles) * 100;
 588
 589     threadCycles
 590         .init(numThreads)
 591         .name(name() + ".threadCycles")
 592         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 593
 594     smtCycles
 595         .name(name() + ".smtCycles")
 596         .desc("Total number of cycles that the CPU was in SMT-mode");
 597
 598     committedInsts
 599         .init(numThreads)
 600         .name(name() + ".committedInsts")
 601         .desc("Number of Instructions Simulated (Per-Thread)");
 602
 603     smtCommittedInsts
 604         .init(numThreads)
 605         .name(name() + ".smtCommittedInsts")
 606         .desc("Number of SMT Instructions Simulated (Per-Thread)");
 607
 608     totalCommittedInsts
 609         .name(name() + ".committedInsts_total")
 610         .desc("Number of Instructions Simulated (Total)");
 611
 612     cpi
 613         .name(name() + ".cpi")
 614         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 615         .precision(6);
 616     cpi = numCycles / committedInsts;
 617
 618     smtCpi
 619         .name(name() + ".smt_cpi")
 620         .desc("CPI: Total SMT-CPI")
 621         .precision(6);
 622     smtCpi = smtCycles / smtCommittedInsts;
 623
 624     totalCpi
 625         .name(name() + ".cpi_total")
 626         .desc("CPI: Total CPI of All Threads")
 627         .precision(6);
 628     totalCpi = numCycles / totalCommittedInsts;
 629
 630     ipc
 631         .name(name() + ".ipc")
 632         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 633         .precision(6);
 634     ipc =  committedInsts / numCycles;
 635
 636     smtIpc
 637         .name(name() + ".smt_ipc")
 638         .desc("IPC: Total SMT-IPC")
 639         .precision(6);
 640     smtIpc = smtCommittedInsts / smtCycles;
 641
 642     totalIpc
 643         .name(name() + ".ipc_total")
 644         .desc("IPC: Total IPC of All Threads")
 645         .precision(6);
 646         totalIpc =  totalCommittedInsts / numCycles;
 647
 648     BaseCPU::regStats();
 649 }
 650
 651
 652 void
 653 InOrderCPU::tick()
 654 {
 655     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 656
 657     ++numCycles;
 658
 659     bool pipes_idle = true;
 660
 661     //Tick each of the stages
 662     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 663         pipelineStage[stNum]->tick();
 664
 665         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 666     }
 667
 668     if (pipes_idle)
 669         idleCycles++;
 670     else
 671         runCycles++;
 672
 673     // Now advance the time buffers one tick
 674     timeBuffer.advance();
 675     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 676         stageQueue[sqNum]->advance();
 677     }
 678     activityRec.advance();
 679
 680     // Any squashed events, or insts then remove them now
 681     cleanUpRemovedEvents();
 682     cleanUpRemovedInsts();
 683
 684     // Re-schedule CPU for this cycle
 685     if (!tickEvent.scheduled()) {
 686         if (_status == SwitchedOut) {
 687             // increment stat
 688             lastRunningCycle = curTick();
 689         } else if (!activityRec.active()) {
 690             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 691             lastRunningCycle = curTick();
 692             timesIdled++;
 693         } else {
 694             //Tick next_tick = curTick() + cycles(1);
 695             //tickEvent.schedule(next_tick);
 696             schedule(&tickEvent, nextCycle(curTick() + 1));
 697             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 698                     nextCycle(curTick() + 1));
 699         }
 700     }
 701
 702     tickThreadStats();
 703     updateThreadPriority();
 704 }
 705
 706
 707 void
 708 InOrderCPU::init()
 709 {
 710     if (!deferRegistration) {
 711         registerThreadContexts();
 712     }
 713
 714     // Set inSyscall so that the CPU doesn't squash when initially
 715     // setting up registers.
 716     for (ThreadID tid = 0; tid < numThreads; ++tid)
 717         thread[tid]->inSyscall = true;
 718
 719 #if FULL_SYSTEM
 720     for (ThreadID tid = 0; tid < numThreads; tid++) {
 721         ThreadContext *src_tc = threadContexts[tid];
 722         TheISA::initCPU(src_tc, src_tc->contextId());
 723     }
 724 #endif
 725
 726     // Clear inSyscall.
 727     for (ThreadID tid = 0; tid < numThreads; ++tid)
 728         thread[tid]->inSyscall = false;
 729
 730     // Call Initializiation Routine for Resource Pool
 731     resPool->init();
 732 }
 733
 734 Port*
 735 InOrderCPU::getPort(const std::string &if_name, int idx)
 736 {
 737     return resPool->getPort(if_name, idx);
 738 }
 739
 740 #if FULL_SYSTEM
 741 Fault
 742 InOrderCPU::hwrei(ThreadID tid)
 743 {
 744     panic("hwrei: Unimplemented");
 745
 746     return NoFault;
 747 }
 748
 749
 750 bool
 751 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 752 {
 753     panic("simPalCheck: Unimplemented");
 754
 755     return true;
 756 }
 757
 758
 759 Fault
 760 InOrderCPU::getInterrupts()
 761 {
 762     // Check if there are any outstanding interrupts
 763     return interrupts->getInterrupt(threadContexts[0]);
 764 }
 765
 766
 767 void
 768 InOrderCPU::processInterrupts(Fault interrupt)
 769 {
 770     // Check for interrupts here.  For now can copy the code that
 771     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 772     // is the one that handles the interrupts.
 773     // @todo: Possibly consolidate the interrupt checking code.
 774     // @todo: Allow other threads to handle interrupts.
 775
 776     assert(interrupt != NoFault);
 777     interrupts->updateIntrInfo(threadContexts[0]);
 778
 779     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 780
 781     // Note: Context ID ok here? Impl. of FS mode needs to revisit this
 782     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 783 }
 784
 785
 786 void
 787 InOrderCPU::updateMemPorts()
 788 {
 789     // Update all ThreadContext's memory ports (Functional/Virtual
 790     // Ports)
 791     ThreadID size = thread.size();
 792     for (ThreadID i = 0; i < size; ++i)
 793         thread[i]->connectMemPorts(thread[i]->getTC());
 794 }
 795 #endif
 796
 797 void
 798 InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 799 {
 800     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 801 }
 802
 803 void
 804 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 805 {
 806     fault->invoke(tcBase(tid), inst->staticInst);
 807 }
 808
 809 void
 810 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 811 {
 812     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 813 }
 814
 815
 816 void
 817 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 818                                 ThreadID tid)
 819 {
 820     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 821
 822     // Squash all instructions in each stage including
 823     // instruction that caused the squash (seq_num - 1)
 824     // NOTE: The stage bandwidth needs to be cleared so thats why
 825     //       the stalling instruction is squashed as well. The stalled
 826     //       instruction is previously placed in another intermediate buffer
 827     //       while it's stall is being handled.
 828     InstSeqNum squash_seq_num = seq_num - 1;
 829
 830     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 831         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 832     }
 833 }
 834
 835 void
 836 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 837                              ThreadID tid, DynInstPtr inst,
 838                              unsigned delay, CPUEventPri event_pri)
 839 {
 840     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 841                                        event_pri);
 842
 843     Tick sked_tick = nextCycle(curTick() + ticks(delay));
 844     if (delay >= 0) {
 845         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 846                 eventNames[c_event], curTick() + delay, tid);
 847         schedule(cpu_event, sked_tick);
 848     } else {
 849         cpu_event->process();
 850         cpuEventRemoveList.push(cpu_event);
 851     }
 852
 853     // Broadcast event to the Resource Pool
 854     // Need to reset tid just in case this is a dummy instruction
 855     inst->setTid(tid);
 856     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 857 }
 858
 859 bool
 860 InOrderCPU::isThreadActive(ThreadID tid)
 861 {
 862   list<ThreadID>::iterator isActive =
 863       std::find(activeThreads.begin(), activeThreads.end(), tid);
 864
 865     return (isActive != activeThreads.end());
 866 }
 867
 868 bool
 869 InOrderCPU::isThreadReady(ThreadID tid)
 870 {
 871   list<ThreadID>::iterator isReady =
 872       std::find(readyThreads.begin(), readyThreads.end(), tid);
 873
 874     return (isReady != readyThreads.end());
 875 }
 876
 877 bool
 878 InOrderCPU::isThreadSuspended(ThreadID tid)
 879 {
 880   list<ThreadID>::iterator isSuspended =
 881       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
 882
 883     return (isSuspended != suspendedThreads.end());
 884 }
 885
 886 void
 887 InOrderCPU::activateNextReadyThread()
 888 {
 889     if (readyThreads.size() >= 1) {
 890         ThreadID ready_tid = readyThreads.front();
 891
 892         // Activate in Pipeline
 893         activateThread(ready_tid);
 894
 895         // Activate in Resource Pool
 896         resPool->activateAll(ready_tid);
 897
 898         list<ThreadID>::iterator ready_it =
 899             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
 900         readyThreads.erase(ready_it);
 901     } else {
 902         DPRINTF(InOrderCPU,
 903                 "Attempting to activate new thread, but No Ready Threads to"
 904                 "activate.\n");
 905         DPRINTF(InOrderCPU,
 906                 "Unable to switch to next active thread.\n");
 907     }
 908 }
 909
 910 void
 911 InOrderCPU::activateThread(ThreadID tid)
 912 {
 913     if (isThreadSuspended(tid)) {
 914         DPRINTF(InOrderCPU,
 915                 "Removing [tid:%i] from suspended threads list.\n", tid);
 916
 917         list<ThreadID>::iterator susp_it =
 918             std::find(suspendedThreads.begin(), suspendedThreads.end(),
 919                       tid);
 920         suspendedThreads.erase(susp_it);
 921     }
 922
 923     if (threadModel == SwitchOnCacheMiss &&
 924         numActiveThreads() == 1) {
 925         DPRINTF(InOrderCPU,
 926                 "Ignoring activation of [tid:%i], since [tid:%i] is "
 927                 "already running.\n", tid, activeThreadId());
 928
 929         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
 930                 tid);
 931
 932         readyThreads.push_back(tid);
 933
 934     } else if (!isThreadActive(tid)) {
 935         DPRINTF(InOrderCPU,
 936                 "Adding [tid:%i] to active threads list.\n", tid);
 937         activeThreads.push_back(tid);
 938
 939         activateThreadInPipeline(tid);
 940
 941         thread[tid]->lastActivate = curTick();
 942
 943         tcBase(tid)->setStatus(ThreadContext::Active);
 944
 945         wakeCPU();
 946
 947         numCtxtSwitches++;
 948     }
 949 }
 950
 951 void
 952 InOrderCPU::activateThreadInPipeline(ThreadID tid)
 953 {
 954     for (int stNum=0; stNum < NumStages; stNum++) {
 955         pipelineStage[stNum]->activateThread(tid);
 956     }
 957 }
 958
 959 void
 960 InOrderCPU::deactivateContext(ThreadID tid, int delay)
 961 {
 962     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
 963
 964     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
 965
 966     // Be sure to signal that there's some activity so the CPU doesn't
 967     // deschedule itself.
 968     activityRec.activity();
 969
 970     _status = Running;
 971 }
 972
 973 void
 974 InOrderCPU::deactivateThread(ThreadID tid)
 975 {
 976     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
 977
 978     if (isThreadActive(tid)) {
 979         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
 980                 tid);
 981         list<ThreadID>::iterator thread_it =
 982             std::find(activeThreads.begin(), activeThreads.end(), tid);
 983
 984         removePipelineStalls(*thread_it);
 985
 986         activeThreads.erase(thread_it);
 987
 988         // Ideally, this should be triggered from the
 989         // suspendContext/Thread functions
 990         tcBase(tid)->setStatus(ThreadContext::Suspended);
 991     }
 992
 993     assert(!isThreadActive(tid));
 994 }
 995
 996 void
 997 InOrderCPU::removePipelineStalls(ThreadID tid)
 998 {
 999     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
1000             tid);
1001
1002     for (int stNum = 0; stNum < NumStages ; stNum++) {
1003         pipelineStage[stNum]->removeStalls(tid);
1004     }
1005
1006 }
1007
1008 void
1009 InOrderCPU::updateThreadPriority()
1010 {
1011     if (activeThreads.size() > 1)
1012     {
1013         //DEFAULT TO ROUND ROBIN SCHEME
1014         //e.g. Move highest priority to end of thread list
1015         list<ThreadID>::iterator list_begin = activeThreads.begin();
1016         list<ThreadID>::iterator list_end   = activeThreads.end();
1017
1018         unsigned high_thread = *list_begin;
1019
1020         activeThreads.erase(list_begin);
1021
1022         activeThreads.push_back(high_thread);
1023     }
1024 }
1025
1026 inline void
1027 InOrderCPU::tickThreadStats()
1028 {
1029     /** Keep track of cycles that each thread is active */
1030     list<ThreadID>::iterator thread_it = activeThreads.begin();
1031     while (thread_it != activeThreads.end()) {
1032         threadCycles[*thread_it]++;
1033         thread_it++;
1034     }
1035
1036     // Keep track of cycles where SMT is active
1037     if (activeThreads.size() > 1) {
1038         smtCycles++;
1039     }
1040 }
1041
1042 void
1043 InOrderCPU::activateContext(ThreadID tid, int delay)
1044 {
1045     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
1046
1047
1048     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
1049
1050     // Be sure to signal that there's some activity so the CPU doesn't
1051     // deschedule itself.
1052     activityRec.activity();
1053
1054     _status = Running;
1055 }
1056
1057 void
1058 InOrderCPU::activateNextReadyContext(int delay)
1059 {
1060     DPRINTF(InOrderCPU,"Activating next ready thread\n");
1061
1062     // NOTE: Add 5 to the event priority so that we always activate
1063     // threads after we've finished deactivating, squashing,etc.
1064     // other threads
1065     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
1066                      delay, ActivateNextReadyThread_Pri);
1067
1068     // Be sure to signal that there's some activity so the CPU doesn't
1069     // deschedule itself.
1070     activityRec.activity();
1071
1072     _status = Running;
1073 }
1074
1075 void
1076 InOrderCPU::haltContext(ThreadID tid, int delay)
1077 {
1078     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
1079
1080     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
1081
1082     activityRec.activity();
1083 }
1084
1085 void
1086 InOrderCPU::haltThread(ThreadID tid)
1087 {
1088     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
1089     deactivateThread(tid);
1090     squashThreadInPipeline(tid);
1091     haltedThreads.push_back(tid);
1092
1093     tcBase(tid)->setStatus(ThreadContext::Halted);
1094
1095     if (threadModel == SwitchOnCacheMiss) {
1096         activateNextReadyContext();
1097     }
1098 }
1099
1100 void
1101 InOrderCPU::suspendContext(ThreadID tid, int delay)
1102 {
1103     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
1104 }
1105
1106 void
1107 InOrderCPU::suspendThread(ThreadID tid)
1108 {
1109     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
1110             tid);
1111     deactivateThread(tid);
1112     suspendedThreads.push_back(tid);
1113     thread[tid]->lastSuspend = curTick();
1114
1115     tcBase(tid)->setStatus(ThreadContext::Suspended);
1116 }
1117
1118 void
1119 InOrderCPU::squashThreadInPipeline(ThreadID tid)
1120 {
1121     //Squash all instructions in each stage
1122     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
1123         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
1124     }
1125 }
1126
1127 PipelineStage*
1128 InOrderCPU::getPipeStage(int stage_num)
1129 {
1130     return pipelineStage[stage_num];
1131 }
1132
1133
1134 RegIndex
1135 InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
1136 {
1137     if (reg_idx < FP_Base_DepTag) {
1138         reg_type = IntType;
1139         return isa[tid].flattenIntIndex(reg_idx);
1140     } else if (reg_idx < Ctrl_Base_DepTag) {
1141         reg_type = FloatType;
1142         reg_idx -= FP_Base_DepTag;
1143         return isa[tid].flattenFloatIndex(reg_idx);
1144     } else {
1145         reg_type = MiscType;
1146         return reg_idx - TheISA::Ctrl_Base_DepTag;
1147     }
1148 }
1149
1150 uint64_t
1151 InOrderCPU::readIntReg(RegIndex reg_idx, ThreadID tid)
1152 {
1153     DPRINTF(IntRegs, "[tid:%i]: Reading Int. Reg %i as %x\n",
1154             tid, reg_idx, intRegs[tid][reg_idx]);
1155
1156     return intRegs[tid][reg_idx];
1157 }
1158
1159 FloatReg
1160 InOrderCPU::readFloatReg(RegIndex reg_idx, ThreadID tid)
1161 {
1162     return floatRegs.f[tid][reg_idx];
1163 }
1164
1165 FloatRegBits
1166 InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
1167 {;
1168     return floatRegs.i[tid][reg_idx];
1169 }
1170
1171 void
1172 InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid)
1173 {
1174     if (reg_idx == TheISA::ZeroReg) {
1175         DPRINTF(IntRegs, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1176                 "(Int. Reg %i) to %x\n", tid, reg_idx, val);
1177         return;
1178     } else {
1179         DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
1180                 tid, reg_idx, val);
1181
1182         intRegs[tid][reg_idx] = val;
1183     }
1184 }
1185
1186
1187 void
1188 InOrderCPU::setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid)
1189 {
1190     floatRegs.f[tid][reg_idx] = val;
1191 }
1192
1193
1194 void
1195 InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid)
1196 {
1197     floatRegs.i[tid][reg_idx] = val;
1198 }
1199
1200 uint64_t
1201 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1202 {
1203     // If Default value is set, then retrieve target thread
1204     if (tid == InvalidThreadID) {
1205         tid = TheISA::getTargetThread(tcBase(tid));
1206     }
1207
1208     if (reg_idx < FP_Base_DepTag) {
1209         // Integer Register File
1210         return readIntReg(reg_idx, tid);
1211     } else if (reg_idx < Ctrl_Base_DepTag) {
1212         // Float Register File
1213         reg_idx -= FP_Base_DepTag;
1214         return readFloatRegBits(reg_idx, tid);
1215     } else {
1216         reg_idx -= Ctrl_Base_DepTag;
1217         return readMiscReg(reg_idx, tid);  // Misc. Register File
1218     }
1219 }
1220 void
1221 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1222                               ThreadID tid)
1223 {
1224     // If Default value is set, then retrieve target thread
1225     if (tid == InvalidThreadID) {
1226         tid = TheISA::getTargetThread(tcBase(tid));
1227     }
1228
1229     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1230         setIntReg(reg_idx, val, tid);
1231     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1232         reg_idx -= FP_Base_DepTag;
1233         setFloatRegBits(reg_idx, val, tid);
1234     } else {
1235         reg_idx -= Ctrl_Base_DepTag;
1236         setMiscReg(reg_idx, val, tid); // Misc. Register File
1237     }
1238 }
1239
1240 MiscReg
1241 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1242 {
1243     return isa[tid].readMiscRegNoEffect(misc_reg);
1244 }
1245
1246 MiscReg
1247 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1248 {
1249     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1250 }
1251
1252 void
1253 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1254 {
1255     isa[tid].setMiscRegNoEffect(misc_reg, val);
1256 }
1257
1258 void
1259 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1260 {
1261     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1262 }
1263
1264
1265 InOrderCPU::ListIt
1266 InOrderCPU::addInst(DynInstPtr inst)
1267 {
1268     ThreadID tid = inst->readTid();
1269
1270     instList[tid].push_back(inst);
1271
1272     return --(instList[tid].end());
1273 }
1274
1275 InOrderCPU::ListIt
1276 InOrderCPU::findInst(InstSeqNum seq_num, ThreadID tid)
1277 {
1278     ListIt it = instList[tid].begin();
1279     ListIt end = instList[tid].end();
1280
1281     while (it != end) {
1282         if ((*it)->seqNum == seq_num)
1283             return it;
1284         else if ((*it)->seqNum > seq_num)
1285             break;
1286
1287         it++;
1288     }
1289
1290     return instList[tid].end();
1291 }
1292
1293 void
1294 InOrderCPU::updateContextSwitchStats()
1295 {
1296     // Set Average Stat Here, then reset to 0
1297     instsPerCtxtSwitch = instsPerSwitch;
1298     instsPerSwitch = 0;
1299 }
1300
1301
1302 void
1303 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1304 {
1305     // Set the nextPC to be fetched if this is the last instruction
1306     // committed
1307     // ========
1308     // This contributes to the precise state of the CPU
1309     // which can be used when restoring a thread to the CPU after after any
1310     // type of context switching activity (fork, exception, etc.)
1311     TheISA::PCState comm_pc = inst->pcState();
1312     lastCommittedPC[tid] = comm_pc;
1313     TheISA::advancePC(comm_pc, inst->staticInst);
1314     pcState(comm_pc, tid);
1315
1316     //@todo: may be unnecessary with new-ISA-specific branch handling code
1317     if (inst->isControl()) {
1318         thread[tid]->lastGradIsBranch = true;
1319         thread[tid]->lastBranchPC = inst->pcState();
1320         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1321     } else {
1322         thread[tid]->lastGradIsBranch = false;
1323     }
1324
1325
1326     // Finalize Trace Data For Instruction
1327     if (inst->traceData) {
1328         //inst->traceData->setCycle(curTick());
1329         inst->traceData->setFetchSeq(inst->seqNum);
1330         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1331         inst->traceData->dump();
1332         delete inst->traceData;
1333         inst->traceData = NULL;
1334     }
1335
1336     // Increment active thread's instruction count
1337     instsPerSwitch++;
1338
1339     // Increment thread-state's instruction count
1340     thread[tid]->numInst++;
1341
1342     // Increment thread-state's instruction stats
1343     thread[tid]->numInsts++;
1344
1345     // Count committed insts per thread stats
1346     committedInsts[tid]++;
1347
1348     // Count total insts committed stat
1349     totalCommittedInsts++;
1350
1351     // Count SMT-committed insts per thread stat
1352     if (numActiveThreads() > 1) {
1353         smtCommittedInsts[tid]++;
1354     }
1355
1356     // Instruction-Mix Stats
1357     if (inst->isLoad()) {
1358         comLoads++;
1359     } else if (inst->isStore()) {
1360         comStores++;
1361     } else if (inst->isControl()) {
1362         comBranches++;
1363     } else if (inst->isNop()) {
1364         comNops++;
1365     } else if (inst->isNonSpeculative()) {
1366         comNonSpec++;
1367     } else if (inst->isInteger()) {
1368         comInts++;
1369     } else if (inst->isFloating()) {
1370         comFloats++;
1371     }
1372
1373     // Check for instruction-count-based events.
1374     comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1375
1376     // Broadcast to other resources an instruction
1377     // has been completed
1378     resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
1379                            0, 0, tid);
1380
1381     // Finally, remove instruction from CPU
1382     removeInst(inst);
1383 }
1384
1385 // currently unused function, but substitute repetitive code w/this function
1386 // call
1387 void
1388 InOrderCPU::addToRemoveList(DynInstPtr inst)
1389 {
1390     removeInstsThisCycle = true;
1391     if (!inst->isRemoveList()) {
1392         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1393                 "[sn:%lli] to remove list\n",
1394                 inst->threadNumber, inst->pcState(), inst->seqNum);
1395         inst->setRemoveList();
1396         removeList.push(inst->getInstListIt());
1397     }  else {
1398         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1399                 "[sn:%lli], already remove list\n",
1400                 inst->threadNumber, inst->pcState(), inst->seqNum);
1401     }
1402
1403 }
1404
1405 void
1406 InOrderCPU::removeInst(DynInstPtr inst)
1407 {
1408     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1409             "[sn:%lli]\n",
1410             inst->threadNumber, inst->pcState(), inst->seqNum);
1411
1412     removeInstsThisCycle = true;
1413
1414     // Remove the instruction.
1415     if (!inst->isRemoveList()) {
1416         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1417                 "[sn:%lli] to remove list\n",
1418                 inst->threadNumber, inst->pcState(), inst->seqNum);
1419         inst->setRemoveList();
1420         removeList.push(inst->getInstListIt());
1421     } else {
1422         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1423                 "[sn:%lli], already on remove list\n",
1424                 inst->threadNumber, inst->pcState(), inst->seqNum);
1425     }
1426
1427 }
1428
1429 void
1430 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1431 {
1432     //assert(!instList[tid].empty());
1433
1434     removeInstsThisCycle = true;
1435
1436     ListIt inst_iter = instList[tid].end();
1437
1438     inst_iter--;
1439
1440     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1441             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1442             tid, seq_num, (*inst_iter)->seqNum);
1443
1444     while ((*inst_iter)->seqNum > seq_num) {
1445
1446         bool break_loop = (inst_iter == instList[tid].begin());
1447
1448         squashInstIt(inst_iter, tid);
1449
1450         inst_iter--;
1451
1452         if (break_loop)
1453             break;
1454     }
1455 }
1456
1457
1458 inline void
1459 InOrderCPU::squashInstIt(const ListIt inst_it, ThreadID tid)
1460 {
1461     DynInstPtr inst = (*inst_it);
1462     if (inst->threadNumber == tid) {
1463         DPRINTF(InOrderCPU, "Squashing instruction, "
1464                 "[tid:%i] [sn:%lli] PC %s\n",
1465                 inst->threadNumber,
1466                 inst->seqNum,
1467                 inst->pcState());
1468
1469         inst->setSquashed();
1470         archRegDepMap[tid].remove(inst);
1471
1472         if (!inst->isRemoveList()) {
1473             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1474                     "[sn:%lli] to remove list\n",
1475                     inst->threadNumber, inst->pcState(),
1476                     inst->seqNum);
1477             inst->setRemoveList();
1478             removeList.push(inst_it);
1479         } else {
1480             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1481                     " PC %s [sn:%lli], already on remove list\n",
1482                     inst->threadNumber, inst->pcState(),
1483                     inst->seqNum);
1484         }
1485
1486     }
1487
1488 }
1489
1490
1491 void
1492 InOrderCPU::cleanUpRemovedInsts()
1493 {
1494     while (!removeList.empty()) {
1495         DPRINTF(InOrderCPU, "Removing instruction, "
1496                 "[tid:%i] [sn:%lli] PC %s\n",
1497                 (*removeList.front())->threadNumber,
1498                 (*removeList.front())->seqNum,
1499                (*removeList.front())->pcState());
1500
1501         DynInstPtr inst = *removeList.front();
1502         ThreadID tid = inst->threadNumber;
1503
1504         // Remove From Register Dependency Map, If Necessary
1505         // archRegDepMap[tid].remove(inst);
1506
1507         // Clear if Non-Speculative
1508         if (inst->staticInst &&
1509             inst->seqNum == nonSpecSeqNum[tid] &&
1510             nonSpecInstActive[tid] == true) {
1511             nonSpecInstActive[tid] = false;
1512         }
1513
1514         inst->onInstList = false;
1515
1516         instList[tid].erase(removeList.front());
1517
1518         removeList.pop();
1519     }
1520
1521     removeInstsThisCycle = false;
1522 }
1523
1524 void
1525 InOrderCPU::cleanUpRemovedEvents()
1526 {
1527     while (!cpuEventRemoveList.empty()) {
1528         Event *cpu_event = cpuEventRemoveList.front();
1529         cpuEventRemoveList.pop();
1530         delete cpu_event;
1531     }
1532 }
1533
1534
1535 void
1536 InOrderCPU::dumpInsts()
1537 {
1538     int num = 0;
1539
1540     ListIt inst_list_it = instList[0].begin();
1541
1542     cprintf("Dumping Instruction List\n");
1543
1544     while (inst_list_it != instList[0].end()) {
1545         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1546                 "Squashed:%i\n\n",
1547                 num, (*inst_list_it)->pcState(),
1548                 (*inst_list_it)->threadNumber,
1549                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1550                 (*inst_list_it)->isSquashed());
1551         inst_list_it++;
1552         ++num;
1553     }
1554 }
1555
1556 void
1557 InOrderCPU::wakeCPU()
1558 {
1559     if (/*activityRec.active() || */tickEvent.scheduled()) {
1560         DPRINTF(Activity, "CPU already running.\n");
1561         return;
1562     }
1563
1564     DPRINTF(Activity, "Waking up CPU\n");
1565
1566     Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
1567
1568     idleCycles += extra_cycles;
1569     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1570         pipelineStage[stage_num]->idleCycles += extra_cycles;
1571     }
1572
1573     numCycles += extra_cycles;
1574
1575     schedule(&tickEvent, nextCycle(curTick()));
1576 }
1577
1578 #if FULL_SYSTEM
1579
1580 void
1581 InOrderCPU::wakeup()
1582 {
1583     if (thread[0]->status() != ThreadContext::Suspended)
1584         return;
1585
1586     wakeCPU();
1587
1588     DPRINTF(Quiesce, "Suspended Processor woken\n");
1589     threadContexts[0]->activate();
1590 }
1591 #endif
1592
1593 #if !FULL_SYSTEM
1594 void
1595 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1596 {
1597     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1598
1599     DPRINTF(Activity,"Activity: syscall() called.\n");
1600
1601     // Temporarily increase this by one to account for the syscall
1602     // instruction.
1603     ++(this->thread[tid]->funcExeInst);
1604
1605     // Execute the actual syscall.
1606     this->thread[tid]->syscall(callnum);
1607
1608     // Decrease funcExeInst by one as the normal commit will handle
1609     // incrementing it.
1610     --(this->thread[tid]->funcExeInst);
1611
1612     // Clear Non-Speculative Block Variable
1613     nonSpecInstActive[tid] = false;
1614 }
1615 #endif
1616
1617 TheISA::TLB*
1618 InOrderCPU::getITBPtr()
1619 {
1620     CacheUnit *itb_res =
1621         dynamic_cast<CacheUnit*>(resPool->getResource(fetchPortIdx));
1622     return itb_res->tlb();
1623 }
1624
1625
1626 TheISA::TLB*
1627 InOrderCPU::getDTBPtr()
1628 {
1629     CacheUnit *dtb_res =
1630         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1631     return dtb_res->tlb();
1632 }
1633
1634 Fault
1635 InOrderCPU::read(DynInstPtr inst, Addr addr,
1636                  uint8_t *data, unsigned size, unsigned flags)
1637 {
1638     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1639     //       you want to run w/out caches?
1640     CacheUnit *cache_res =
1641         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1642
1643     return cache_res->read(inst, addr, data, size, flags);
1644 }
1645
1646 Fault
1647 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1648                   Addr addr, unsigned flags, uint64_t *write_res)
1649 {
1650     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1651     //       you want to run w/out caches?
1652     CacheUnit *cache_res =
1653         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1654     return cache_res->write(inst, data, size, addr, flags, write_res);
1655 }