src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007 MIPS Technologies, Inc.
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Korey Sewell
  41  *
  42  */
  43
  44 #include <algorithm>
  45
  46 #include "arch/utility.hh"
  47 #include "base/bigint.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/inorder/resources/cache_unit.hh"
  50 #include "cpu/inorder/resources/resource_list.hh"
  51 #include "cpu/inorder/cpu.hh"
  52 #include "cpu/inorder/first_stage.hh"
  53 #include "cpu/inorder/inorder_dyn_inst.hh"
  54 #include "cpu/inorder/pipeline_traits.hh"
  55 #include "cpu/inorder/resource_pool.hh"
  56 #include "cpu/inorder/thread_context.hh"
  57 #include "cpu/inorder/thread_state.hh"
  58 #include "cpu/activity.hh"
  59 #include "cpu/base.hh"
  60 #include "cpu/exetrace.hh"
  61 #include "cpu/quiesce_event.hh"
  62 #include "cpu/simple_thread.hh"
  63 #include "cpu/thread_context.hh"
  64 #include "debug/Activity.hh"
  65 #include "debug/InOrderCPU.hh"
  66 #include "debug/InOrderCachePort.hh"
  67 #include "debug/Interrupt.hh"
  68 #include "debug/Quiesce.hh"
  69 #include "debug/RefCount.hh"
  70 #include "debug/SkedCache.hh"
  71 #include "params/InOrderCPU.hh"
  72 #include "sim/full_system.hh"
  73 #include "sim/process.hh"
  74 #include "sim/stat_control.hh"
  75 #include "sim/system.hh"
  76
  77 #if THE_ISA == ALPHA_ISA
  78 #include "arch/alpha/osfpal.hh"
  79 #endif
  80
  81 using namespace std;
  82 using namespace TheISA;
  83 using namespace ThePipeline;
  84
  85 InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit) :
  86     CpuPort(_cacheUnit->name() + "-cache-port", _cacheUnit->cpu),
  87     cacheUnit(_cacheUnit)
  88 { }
  89
  90 bool
  91 InOrderCPU::CachePort::recvTiming(Packet *pkt)
  92 {
  93     if (pkt->isError())
  94         DPRINTF(InOrderCachePort, "Got error packet back for address: %x\n",
  95                 pkt->getAddr());
  96     else if (pkt->isResponse())
  97         cacheUnit->processCacheCompletion(pkt);
  98     else {
  99         //@note: depending on consistency model, update here
 100         DPRINTF(InOrderCachePort, "Received snoop pkt %x,Ignoring\n",
 101                 pkt->getAddr());
 102     }
 103
 104     return true;
 105 }
 106
 107 void
 108 InOrderCPU::CachePort::recvRetry()
 109 {
 110     cacheUnit->recvRetry();
 111 }
 112
 113 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
 114   : Event(CPU_Tick_Pri), cpu(c)
 115 { }
 116
 117
 118 void
 119 InOrderCPU::TickEvent::process()
 120 {
 121     cpu->tick();
 122 }
 123
 124
 125 const char *
 126 InOrderCPU::TickEvent::description() const
 127 {
 128     return "InOrderCPU tick event";
 129 }
 130
 131 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
 132                                Fault fault, ThreadID _tid, DynInstPtr inst,
 133                                CPUEventPri event_pri)
 134     : Event(event_pri), cpu(_cpu)
 135 {
 136     setEvent(e_type, fault, _tid, inst);
 137 }
 138
 139
 140 std::string InOrderCPU::eventNames[NumCPUEvents] =
 141 {
 142     "ActivateThread",
 143     "ActivateNextReadyThread",
 144     "DeactivateThread",
 145     "HaltThread",
 146     "SuspendThread",
 147     "Trap",
 148     "Syscall",
 149     "SquashFromMemStall",
 150     "UpdatePCs"
 151 };
 152
 153 void
 154 InOrderCPU::CPUEvent::process()
 155 {
 156     switch (cpuEventType)
 157     {
 158       case ActivateThread:
 159         cpu->activateThread(tid);
 160         cpu->resPool->activateThread(tid);
 161         break;
 162
 163       case ActivateNextReadyThread:
 164         cpu->activateNextReadyThread();
 165         break;
 166
 167       case DeactivateThread:
 168         cpu->deactivateThread(tid);
 169         cpu->resPool->deactivateThread(tid);
 170         break;
 171
 172       case HaltThread:
 173         cpu->haltThread(tid);
 174         cpu->resPool->deactivateThread(tid);
 175         break;
 176
 177       case SuspendThread:
 178         cpu->suspendThread(tid);
 179         cpu->resPool->suspendThread(tid);
 180         break;
 181
 182       case SquashFromMemStall:
 183         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 184         cpu->resPool->squashDueToMemStall(inst, inst->squashingStage,
 185                                           inst->seqNum, tid);
 186         break;
 187
 188       case Trap:
 189         DPRINTF(InOrderCPU, "Trapping CPU\n");
 190         cpu->trap(fault, tid, inst);
 191         cpu->resPool->trap(fault, tid, inst);
 192         cpu->trapPending[tid] = false;
 193         break;
 194
 195       case Syscall:
 196         cpu->syscall(inst->syscallNum, tid);
 197         cpu->resPool->trap(fault, tid, inst);
 198         break;
 199
 200       default:
 201         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 202     }
 203
 204     cpu->cpuEventRemoveList.push(this);
 205 }
 206
 207
 208
 209 const char *
 210 InOrderCPU::CPUEvent::description() const
 211 {
 212     return "InOrderCPU event";
 213 }
 214
 215 void
 216 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 217 {
 218     assert(!scheduled() || squashed());
 219     cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
 220 }
 221
 222 void
 223 InOrderCPU::CPUEvent::unscheduleEvent()
 224 {
 225     if (scheduled())
 226         squash();
 227 }
 228
 229 InOrderCPU::InOrderCPU(Params *params)
 230     : BaseCPU(params),
 231       cpu_id(params->cpu_id),
 232       coreType("default"),
 233       _status(Idle),
 234       tickEvent(this),
 235       stageWidth(params->stageWidth),
 236       resPool(new ResourcePool(this, params)),
 237       timeBuffer(2 , 2),
 238       dataPort(resPool->getDataUnit()),
 239       instPort(resPool->getInstUnit()),
 240       removeInstsThisCycle(false),
 241       activityRec(params->name, NumStages, 10, params->activity),
 242       system(params->system),
 243 #ifdef DEBUG
 244       cpuEventNum(0),
 245       resReqCount(0),
 246 #endif // DEBUG
 247       drainCount(0),
 248       deferRegistration(false/*params->deferRegistration*/),
 249       stageTracing(params->stageTracing),
 250       lastRunningCycle(0),
 251       instsPerSwitch(0)
 252 {
 253     cpu_params = params;
 254
 255     // Resize for Multithreading CPUs
 256     thread.resize(numThreads);
 257
 258     ThreadID active_threads = params->workload.size();
 259     if (FullSystem) {
 260         active_threads = 1;
 261     } else {
 262         active_threads = params->workload.size();
 263
 264         if (active_threads > MaxThreads) {
 265             panic("Workload Size too large. Increase the 'MaxThreads'"
 266                   "in your InOrder implementation or "
 267                   "edit your workload size.");
 268         }
 269
 270
 271         if (active_threads > 1) {
 272             threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 273
 274             if (threadModel == SMT) {
 275                 DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 276             } else if (threadModel == SwitchOnCacheMiss) {
 277                 DPRINTF(InOrderCPU, "Setting Thread Model to "
 278                         "Switch On Cache Miss\n");
 279             }
 280
 281         } else {
 282             threadModel = Single;
 283         }
 284     }
 285
 286     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 287         pc[tid].set(0);
 288         lastCommittedPC[tid].set(0);
 289
 290         if (FullSystem) {
 291             // SMT is not supported in FS mode yet.
 292             assert(numThreads == 1);
 293             thread[tid] = new Thread(this, 0, NULL);
 294         } else {
 295             if (tid < (ThreadID)params->workload.size()) {
 296                 DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 297                         tid, params->workload[tid]->prog_fname);
 298                 thread[tid] =
 299                     new Thread(this, tid, params->workload[tid]);
 300             } else {
 301                 //Allocate Empty thread so M5 can use later
 302                 //when scheduling threads to CPU
 303                 Process* dummy_proc = params->workload[0];
 304                 thread[tid] = new Thread(this, tid, dummy_proc);
 305             }
 306
 307             // Eventually set this with parameters...
 308             asid[tid] = tid;
 309         }
 310
 311         // Setup the TC that will serve as the interface to the threads/CPU.
 312         InOrderThreadContext *tc = new InOrderThreadContext;
 313         tc->cpu = this;
 314         tc->thread = thread[tid];
 315
 316         // Setup quiesce event.
 317         this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
 318
 319         // Give the thread the TC.
 320         thread[tid]->tc = tc;
 321         thread[tid]->setFuncExeInst(0);
 322         globalSeqNum[tid] = 1;
 323
 324         // Add the TC to the CPU's list of TC's.
 325         this->threadContexts.push_back(tc);
 326     }
 327
 328     // Initialize TimeBuffer Stage Queues
 329     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 330         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 331         stageQueue[stNum]->id(stNum);
 332     }
 333
 334
 335     // Set Up Pipeline Stages
 336     for (int stNum=0; stNum < NumStages; stNum++) {
 337         if (stNum == 0)
 338             pipelineStage[stNum] = new FirstStage(params, stNum);
 339         else
 340             pipelineStage[stNum] = new PipelineStage(params, stNum);
 341
 342         pipelineStage[stNum]->setCPU(this);
 343         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 344         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 345
 346         // Take Care of 1st/Nth stages
 347         if (stNum > 0)
 348             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 349         if (stNum < NumStages - 1)
 350             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 351     }
 352
 353     // Initialize thread specific variables
 354     for (ThreadID tid = 0; tid < numThreads; tid++) {
 355         archRegDepMap[tid].setCPU(this);
 356
 357         nonSpecInstActive[tid] = false;
 358         nonSpecSeqNum[tid] = 0;
 359
 360         squashSeqNum[tid] = MaxAddr;
 361         lastSquashCycle[tid] = 0;
 362
 363         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 364         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 365         isa[tid].clear();
 366
 367         // Define dummy instructions and resource requests to be used.
 368         dummyInst[tid] = new InOrderDynInst(this,
 369                                             thread[tid],
 370                                             0,
 371                                             tid,
 372                                             asid[tid]);
 373
 374         dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
 375
 376
 377         if (FullSystem) {
 378             // Use this dummy inst to force squashing behind every instruction
 379             // in pipeline
 380             dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
 381             dummyTrapInst[tid]->seqNum = 0;
 382             dummyTrapInst[tid]->squashSeqNum = 0;
 383             dummyTrapInst[tid]->setTid(tid);
 384         }
 385
 386         trapPending[tid] = false;
 387
 388     }
 389
 390     // InOrderCPU always requires an interrupt controller.
 391     if (!params->defer_registration && !interrupts) {
 392         fatal("InOrderCPU %s has no interrupt controller.\n"
 393               "Ensure createInterruptController() is called.\n", name());
 394     }
 395
 396     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 397     dummyReqInst->setSquashed();
 398     dummyReqInst->resetInstCount();
 399
 400     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 401     dummyBufferInst->setSquashed();
 402     dummyBufferInst->resetInstCount();
 403
 404     endOfSkedIt = skedCache.end();
 405     frontEndSked = createFrontEndSked();
 406     faultSked = createFaultSked();
 407
 408     lastRunningCycle = curTick();
 409
 410     lockAddr = 0;
 411     lockFlag = false;
 412
 413     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 414     scheduleTickEvent(0);
 415 }
 416
 417 InOrderCPU::~InOrderCPU()
 418 {
 419     delete resPool;
 420
 421     SkedCacheIt sked_it = skedCache.begin();
 422     SkedCacheIt sked_end = skedCache.end();
 423
 424     while (sked_it != sked_end) {
 425         delete (*sked_it).second;
 426         sked_it++;
 427     }
 428     skedCache.clear();
 429 }
 430
 431 m5::hash_map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
 432
 433 RSkedPtr
 434 InOrderCPU::createFrontEndSked()
 435 {
 436     RSkedPtr res_sked = new ResourceSked();
 437     int stage_num = 0;
 438     StageScheduler F(res_sked, stage_num++);
 439     StageScheduler D(res_sked, stage_num++);
 440
 441     // FETCH
 442     F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
 443     F.needs(ICache, FetchUnit::InitiateFetch);
 444
 445     // DECODE
 446     D.needs(ICache, FetchUnit::CompleteFetch);
 447     D.needs(Decode, DecodeUnit::DecodeInst);
 448     D.needs(BPred, BranchPredictor::PredictBranch);
 449     D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
 450
 451
 452     DPRINTF(SkedCache, "Resource Sked created for instruction Front End\n");
 453
 454     return res_sked;
 455 }
 456
 457 RSkedPtr
 458 InOrderCPU::createFaultSked()
 459 {
 460     RSkedPtr res_sked = new ResourceSked();
 461     StageScheduler W(res_sked, NumStages - 1);
 462     W.needs(Grad, GraduationUnit::CheckFault);
 463     DPRINTF(SkedCache, "Resource Sked created for instruction Faults\n");
 464     return res_sked;
 465 }
 466
 467 RSkedPtr
 468 InOrderCPU::createBackEndSked(DynInstPtr inst)
 469 {
 470     RSkedPtr res_sked = lookupSked(inst);
 471     if (res_sked != NULL) {
 472         DPRINTF(SkedCache, "Found %s in sked cache.\n",
 473                 inst->instName());
 474         return res_sked;
 475     } else {
 476         res_sked = new ResourceSked();
 477     }
 478
 479     int stage_num = ThePipeline::BackEndStartStage;
 480     StageScheduler X(res_sked, stage_num++);
 481     StageScheduler M(res_sked, stage_num++);
 482     StageScheduler W(res_sked, stage_num++);
 483
 484     if (!inst->staticInst) {
 485         warn_once("Static Instruction Object Not Set. Can't Create"
 486                   " Back End Schedule");
 487         return NULL;
 488     }
 489
 490     // EXECUTE
 491     X.needs(RegManager, UseDefUnit::MarkDestRegs);
 492     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 493         if (!idx || !inst->isStore()) {
 494             X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
 495         }
 496     }
 497
 498     //@todo: schedule non-spec insts to operate on this cycle
 499     // as long as all previous insts are done
 500     if ( inst->isNonSpeculative() ) {
 501         // skip execution of non speculative insts until later
 502     } else if ( inst->isMemRef() ) {
 503         if ( inst->isLoad() ) {
 504             X.needs(AGEN, AGENUnit::GenerateAddr);
 505         }
 506     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 507         X.needs(MDU, MultDivUnit::StartMultDiv);
 508     } else {
 509         X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 510     }
 511
 512     // MEMORY
 513     if (!inst->isNonSpeculative()) {
 514         if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 515             M.needs(MDU, MultDivUnit::EndMultDiv);
 516         }
 517
 518         if ( inst->isLoad() ) {
 519             M.needs(DCache, CacheUnit::InitiateReadData);
 520             if (inst->splitInst)
 521                 M.needs(DCache, CacheUnit::InitSecondSplitRead);
 522         } else if ( inst->isStore() ) {
 523             for (int i = 1; i < inst->numSrcRegs(); i++ ) {
 524                 M.needs(RegManager, UseDefUnit::ReadSrcReg, i);
 525             }
 526             M.needs(AGEN, AGENUnit::GenerateAddr);
 527             M.needs(DCache, CacheUnit::InitiateWriteData);
 528             if (inst->splitInst)
 529                 M.needs(DCache, CacheUnit::InitSecondSplitWrite);
 530         }
 531     }
 532
 533     // WRITEBACK
 534     if (!inst->isNonSpeculative()) {
 535         if ( inst->isLoad() ) {
 536             W.needs(DCache, CacheUnit::CompleteReadData);
 537             if (inst->splitInst)
 538                 W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
 539         } else if ( inst->isStore() ) {
 540             W.needs(DCache, CacheUnit::CompleteWriteData);
 541             if (inst->splitInst)
 542                 W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
 543         }
 544     } else {
 545         // Finally, Execute Speculative Data
 546         if (inst->isMemRef()) {
 547             if (inst->isLoad()) {
 548                 W.needs(AGEN, AGENUnit::GenerateAddr);
 549                 W.needs(DCache, CacheUnit::InitiateReadData);
 550                 if (inst->splitInst)
 551                     W.needs(DCache, CacheUnit::InitSecondSplitRead);
 552                 W.needs(DCache, CacheUnit::CompleteReadData);
 553                 if (inst->splitInst)
 554                     W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
 555             } else if (inst->isStore()) {
 556                 if ( inst->numSrcRegs() >= 2 ) {
 557                     W.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 558                 }
 559                 W.needs(AGEN, AGENUnit::GenerateAddr);
 560                 W.needs(DCache, CacheUnit::InitiateWriteData);
 561                 if (inst->splitInst)
 562                     W.needs(DCache, CacheUnit::InitSecondSplitWrite);
 563                 W.needs(DCache, CacheUnit::CompleteWriteData);
 564                 if (inst->splitInst)
 565                     W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
 566             }
 567         } else {
 568             W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 569         }
 570     }
 571
 572     W.needs(Grad, GraduationUnit::CheckFault);
 573
 574     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 575         W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
 576     }
 577
 578     if (inst->isControl())
 579         W.needs(BPred, BranchPredictor::UpdatePredictor);
 580
 581     W.needs(Grad, GraduationUnit::GraduateInst);
 582
 583     // Insert Back Schedule into our cache of
 584     // resource schedules
 585     addToSkedCache(inst, res_sked);
 586
 587     DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
 588             inst->instName(), inst->getMachInst());
 589     res_sked->print();
 590
 591     return res_sked;
 592 }
 593
 594 void
 595 InOrderCPU::regStats()
 596 {
 597     /* Register the Resource Pool's stats here.*/
 598     resPool->regStats();
 599
 600     /* Register for each Pipeline Stage */
 601     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 602         pipelineStage[stage_num]->regStats();
 603     }
 604
 605     /* Register any of the InOrderCPU's stats here.*/
 606     instsPerCtxtSwitch
 607         .name(name() + ".instsPerContextSwitch")
 608         .desc("Instructions Committed Per Context Switch")
 609         .prereq(instsPerCtxtSwitch);
 610
 611     numCtxtSwitches
 612         .name(name() + ".contextSwitches")
 613         .desc("Number of context switches");
 614
 615     comLoads
 616         .name(name() + ".comLoads")
 617         .desc("Number of Load instructions committed");
 618
 619     comStores
 620         .name(name() + ".comStores")
 621         .desc("Number of Store instructions committed");
 622
 623     comBranches
 624         .name(name() + ".comBranches")
 625         .desc("Number of Branches instructions committed");
 626
 627     comNops
 628         .name(name() + ".comNops")
 629         .desc("Number of Nop instructions committed");
 630
 631     comNonSpec
 632         .name(name() + ".comNonSpec")
 633         .desc("Number of Non-Speculative instructions committed");
 634
 635     comInts
 636         .name(name() + ".comInts")
 637         .desc("Number of Integer instructions committed");
 638
 639     comFloats
 640         .name(name() + ".comFloats")
 641         .desc("Number of Floating Point instructions committed");
 642
 643     timesIdled
 644         .name(name() + ".timesIdled")
 645         .desc("Number of times that the entire CPU went into an idle state and"
 646               " unscheduled itself")
 647         .prereq(timesIdled);
 648
 649     idleCycles
 650         .name(name() + ".idleCycles")
 651         .desc("Number of cycles cpu's stages were not processed");
 652
 653     runCycles
 654         .name(name() + ".runCycles")
 655         .desc("Number of cycles cpu stages are processed.");
 656
 657     activity
 658         .name(name() + ".activity")
 659         .desc("Percentage of cycles cpu is active")
 660         .precision(6);
 661     activity = (runCycles / numCycles) * 100;
 662
 663     threadCycles
 664         .init(numThreads)
 665         .name(name() + ".threadCycles")
 666         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 667
 668     smtCycles
 669         .name(name() + ".smtCycles")
 670         .desc("Total number of cycles that the CPU was in SMT-mode");
 671
 672     committedInsts
 673         .init(numThreads)
 674         .name(name() + ".committedInsts")
 675         .desc("Number of Instructions committed (Per-Thread)");
 676
 677     committedOps
 678         .init(numThreads)
 679         .name(name() + ".committedOps")
 680         .desc("Number of Ops committed (Per-Thread)");
 681
 682     smtCommittedInsts
 683         .init(numThreads)
 684         .name(name() + ".smtCommittedInsts")
 685         .desc("Number of SMT Instructions committed (Per-Thread)");
 686
 687     totalCommittedInsts
 688         .name(name() + ".committedInsts_total")
 689         .desc("Number of Instructions committed (Total)");
 690
 691     cpi
 692         .name(name() + ".cpi")
 693         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 694         .precision(6);
 695     cpi = numCycles / committedInsts;
 696
 697     smtCpi
 698         .name(name() + ".smt_cpi")
 699         .desc("CPI: Total SMT-CPI")
 700         .precision(6);
 701     smtCpi = smtCycles / smtCommittedInsts;
 702
 703     totalCpi
 704         .name(name() + ".cpi_total")
 705         .desc("CPI: Total CPI of All Threads")
 706         .precision(6);
 707     totalCpi = numCycles / totalCommittedInsts;
 708
 709     ipc
 710         .name(name() + ".ipc")
 711         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 712         .precision(6);
 713     ipc =  committedInsts / numCycles;
 714
 715     smtIpc
 716         .name(name() + ".smt_ipc")
 717         .desc("IPC: Total SMT-IPC")
 718         .precision(6);
 719     smtIpc = smtCommittedInsts / smtCycles;
 720
 721     totalIpc
 722         .name(name() + ".ipc_total")
 723         .desc("IPC: Total IPC of All Threads")
 724         .precision(6);
 725         totalIpc =  totalCommittedInsts / numCycles;
 726
 727     BaseCPU::regStats();
 728 }
 729
 730
 731 void
 732 InOrderCPU::tick()
 733 {
 734     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 735
 736     ++numCycles;
 737
 738     checkForInterrupts();
 739
 740     bool pipes_idle = true;
 741     //Tick each of the stages
 742     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 743         pipelineStage[stNum]->tick();
 744
 745         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 746     }
 747
 748     if (pipes_idle)
 749         idleCycles++;
 750     else
 751         runCycles++;
 752
 753     // Now advance the time buffers one tick
 754     timeBuffer.advance();
 755     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 756         stageQueue[sqNum]->advance();
 757     }
 758     activityRec.advance();
 759
 760     // Any squashed events, or insts then remove them now
 761     cleanUpRemovedEvents();
 762     cleanUpRemovedInsts();
 763
 764     // Re-schedule CPU for this cycle
 765     if (!tickEvent.scheduled()) {
 766         if (_status == SwitchedOut) {
 767             // increment stat
 768             lastRunningCycle = curTick();
 769         } else if (!activityRec.active()) {
 770             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 771             lastRunningCycle = curTick();
 772             timesIdled++;
 773         } else {
 774             //Tick next_tick = curTick() + cycles(1);
 775             //tickEvent.schedule(next_tick);
 776             schedule(&tickEvent, nextCycle(curTick() + 1));
 777             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 778                     nextCycle(curTick() + 1));
 779         }
 780     }
 781
 782     tickThreadStats();
 783     updateThreadPriority();
 784 }
 785
 786
 787 void
 788 InOrderCPU::init()
 789 {
 790     if (!deferRegistration) {
 791         registerThreadContexts();
 792     }
 793
 794     // Set inSyscall so that the CPU doesn't squash when initially
 795     // setting up registers.
 796     for (ThreadID tid = 0; tid < numThreads; ++tid)
 797         thread[tid]->inSyscall = true;
 798
 799     if (FullSystem) {
 800         for (ThreadID tid = 0; tid < numThreads; tid++) {
 801             ThreadContext *src_tc = threadContexts[tid];
 802             TheISA::initCPU(src_tc, src_tc->contextId());
 803             // Initialise the ThreadContext's memory proxies
 804             thread[tid]->initMemProxies(thread[tid]->getTC());
 805         }
 806     }
 807
 808     // Clear inSyscall.
 809     for (ThreadID tid = 0; tid < numThreads; ++tid)
 810         thread[tid]->inSyscall = false;
 811
 812     // Call Initializiation Routine for Resource Pool
 813     resPool->init();
 814 }
 815
 816 Fault
 817 InOrderCPU::hwrei(ThreadID tid)
 818 {
 819 #if THE_ISA == ALPHA_ISA
 820     // Need to clear the lock flag upon returning from an interrupt.
 821     setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
 822
 823     thread[tid]->kernelStats->hwrei();
 824     // FIXME: XXX check for interrupts? XXX
 825 #endif
 826
 827     return NoFault;
 828 }
 829
 830
 831 bool
 832 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 833 {
 834 #if THE_ISA == ALPHA_ISA
 835     if (this->thread[tid]->kernelStats)
 836         this->thread[tid]->kernelStats->callpal(palFunc,
 837                                                 this->threadContexts[tid]);
 838
 839     switch (palFunc) {
 840       case PAL::halt:
 841         halt();
 842         if (--System::numSystemsRunning == 0)
 843             exitSimLoop("all cpus halted");
 844         break;
 845
 846       case PAL::bpt:
 847       case PAL::bugchk:
 848         if (this->system->breakpoint())
 849             return false;
 850         break;
 851     }
 852 #endif
 853     return true;
 854 }
 855
 856 void
 857 InOrderCPU::checkForInterrupts()
 858 {
 859     for (int i = 0; i < threadContexts.size(); i++) {
 860         ThreadContext *tc = threadContexts[i];
 861
 862         if (interrupts->checkInterrupts(tc)) {
 863             Fault interrupt = interrupts->getInterrupt(tc);
 864
 865             if (interrupt != NoFault) {
 866                 DPRINTF(Interrupt, "Processing Intterupt for [tid:%i].\n",
 867                         tc->threadId());
 868
 869                 ThreadID tid = tc->threadId();
 870                 interrupts->updateIntrInfo(tc);
 871
 872                 // Squash from Last Stage in Pipeline
 873                 unsigned last_stage = NumStages - 1;
 874                 dummyTrapInst[tid]->squashingStage = last_stage;
 875                 pipelineStage[last_stage]->setupSquash(dummyTrapInst[tid],
 876                                                        tid);
 877
 878                 // By default, setupSquash will always squash from stage + 1
 879                 pipelineStage[BackEndStartStage - 1]->setupSquash(dummyTrapInst[tid],
 880                                                                   tid);
 881
 882                 // Schedule Squash Through-out Resource Pool
 883                 resPool->scheduleEvent(
 884                     (InOrderCPU::CPUEventType)ResourcePool::SquashAll,
 885                     dummyTrapInst[tid], 0);
 886
 887                 // Finally, Setup Trap to happen at end of cycle
 888                 trapContext(interrupt, tid, dummyTrapInst[tid]);
 889             }
 890         }
 891     }
 892 }
 893
 894 Fault
 895 InOrderCPU::getInterrupts()
 896 {
 897     // Check if there are any outstanding interrupts
 898     return interrupts->getInterrupt(threadContexts[0]);
 899 }
 900
 901 void
 902 InOrderCPU::processInterrupts(Fault interrupt)
 903 {
 904     // Check for interrupts here.  For now can copy the code that
 905     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 906     // is the one that handles the interrupts.
 907     // @todo: Possibly consolidate the interrupt checking code.
 908     // @todo: Allow other threads to handle interrupts.
 909
 910     assert(interrupt != NoFault);
 911     interrupts->updateIntrInfo(threadContexts[0]);
 912
 913     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 914
 915     // Note: Context ID ok here? Impl. of FS mode needs to revisit this
 916     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 917 }
 918
 919 void
 920 InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 921 {
 922     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 923     trapPending[tid] = true;
 924 }
 925
 926 void
 927 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 928 {
 929     fault->invoke(tcBase(tid), inst->staticInst);
 930     removePipelineStalls(tid);
 931 }
 932
 933 void
 934 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 935 {
 936     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 937 }
 938
 939
 940 void
 941 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 942                                 ThreadID tid)
 943 {
 944     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 945
 946     // Squash all instructions in each stage including
 947     // instruction that caused the squash (seq_num - 1)
 948     // NOTE: The stage bandwidth needs to be cleared so thats why
 949     //       the stalling instruction is squashed as well. The stalled
 950     //       instruction is previously placed in another intermediate buffer
 951     //       while it's stall is being handled.
 952     InstSeqNum squash_seq_num = seq_num - 1;
 953
 954     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 955         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 956     }
 957 }
 958
 959 void
 960 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 961                              ThreadID tid, DynInstPtr inst,
 962                              unsigned delay, CPUEventPri event_pri)
 963 {
 964     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 965                                        event_pri);
 966
 967     Tick sked_tick = nextCycle(curTick() + ticks(delay));
 968     if (delay >= 0) {
 969         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 970                 eventNames[c_event], curTick() + delay, tid);
 971         schedule(cpu_event, sked_tick);
 972     } else {
 973         cpu_event->process();
 974         cpuEventRemoveList.push(cpu_event);
 975     }
 976
 977     // Broadcast event to the Resource Pool
 978     // Need to reset tid just in case this is a dummy instruction
 979     inst->setTid(tid);
 980     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 981 }
 982
 983 bool
 984 InOrderCPU::isThreadActive(ThreadID tid)
 985 {
 986   list<ThreadID>::iterator isActive =
 987       std::find(activeThreads.begin(), activeThreads.end(), tid);
 988
 989     return (isActive != activeThreads.end());
 990 }
 991
 992 bool
 993 InOrderCPU::isThreadReady(ThreadID tid)
 994 {
 995   list<ThreadID>::iterator isReady =
 996       std::find(readyThreads.begin(), readyThreads.end(), tid);
 997
 998     return (isReady != readyThreads.end());
 999 }
1000
1001 bool
1002 InOrderCPU::isThreadSuspended(ThreadID tid)
1003 {
1004   list<ThreadID>::iterator isSuspended =
1005       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
1006
1007     return (isSuspended != suspendedThreads.end());
1008 }
1009
1010 void
1011 InOrderCPU::activateNextReadyThread()
1012 {
1013     if (readyThreads.size() >= 1) {
1014         ThreadID ready_tid = readyThreads.front();
1015
1016         // Activate in Pipeline
1017         activateThread(ready_tid);
1018
1019         // Activate in Resource Pool
1020         resPool->activateThread(ready_tid);
1021
1022         list<ThreadID>::iterator ready_it =
1023             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
1024         readyThreads.erase(ready_it);
1025     } else {
1026         DPRINTF(InOrderCPU,
1027                 "Attempting to activate new thread, but No Ready Threads to"
1028                 "activate.\n");
1029         DPRINTF(InOrderCPU,
1030                 "Unable to switch to next active thread.\n");
1031     }
1032 }
1033
1034 void
1035 InOrderCPU::activateThread(ThreadID tid)
1036 {
1037     if (isThreadSuspended(tid)) {
1038         DPRINTF(InOrderCPU,
1039                 "Removing [tid:%i] from suspended threads list.\n", tid);
1040
1041         list<ThreadID>::iterator susp_it =
1042             std::find(suspendedThreads.begin(), suspendedThreads.end(),
1043                       tid);
1044         suspendedThreads.erase(susp_it);
1045     }
1046
1047     if (threadModel == SwitchOnCacheMiss &&
1048         numActiveThreads() == 1) {
1049         DPRINTF(InOrderCPU,
1050                 "Ignoring activation of [tid:%i], since [tid:%i] is "
1051                 "already running.\n", tid, activeThreadId());
1052
1053         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
1054                 tid);
1055
1056         readyThreads.push_back(tid);
1057
1058     } else if (!isThreadActive(tid)) {
1059         DPRINTF(InOrderCPU,
1060                 "Adding [tid:%i] to active threads list.\n", tid);
1061         activeThreads.push_back(tid);
1062
1063         activateThreadInPipeline(tid);
1064
1065         thread[tid]->lastActivate = curTick();
1066
1067         tcBase(tid)->setStatus(ThreadContext::Active);
1068
1069         wakeCPU();
1070
1071         numCtxtSwitches++;
1072     }
1073 }
1074
1075 void
1076 InOrderCPU::activateThreadInPipeline(ThreadID tid)
1077 {
1078     for (int stNum=0; stNum < NumStages; stNum++) {
1079         pipelineStage[stNum]->activateThread(tid);
1080     }
1081 }
1082
1083 void
1084 InOrderCPU::deactivateContext(ThreadID tid, int delay)
1085 {
1086     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
1087
1088     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
1089
1090     // Be sure to signal that there's some activity so the CPU doesn't
1091     // deschedule itself.
1092     activityRec.activity();
1093
1094     _status = Running;
1095 }
1096
1097 void
1098 InOrderCPU::deactivateThread(ThreadID tid)
1099 {
1100     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
1101
1102     if (isThreadActive(tid)) {
1103         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
1104                 tid);
1105         list<ThreadID>::iterator thread_it =
1106             std::find(activeThreads.begin(), activeThreads.end(), tid);
1107
1108         removePipelineStalls(*thread_it);
1109
1110         activeThreads.erase(thread_it);
1111
1112         // Ideally, this should be triggered from the
1113         // suspendContext/Thread functions
1114         tcBase(tid)->setStatus(ThreadContext::Suspended);
1115     }
1116
1117     assert(!isThreadActive(tid));
1118 }
1119
1120 void
1121 InOrderCPU::removePipelineStalls(ThreadID tid)
1122 {
1123     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
1124             tid);
1125
1126     for (int stNum = 0; stNum < NumStages ; stNum++) {
1127         pipelineStage[stNum]->removeStalls(tid);
1128     }
1129
1130 }
1131
1132 void
1133 InOrderCPU::updateThreadPriority()
1134 {
1135     if (activeThreads.size() > 1)
1136     {
1137         //DEFAULT TO ROUND ROBIN SCHEME
1138         //e.g. Move highest priority to end of thread list
1139         list<ThreadID>::iterator list_begin = activeThreads.begin();
1140
1141         unsigned high_thread = *list_begin;
1142
1143         activeThreads.erase(list_begin);
1144
1145         activeThreads.push_back(high_thread);
1146     }
1147 }
1148
1149 inline void
1150 InOrderCPU::tickThreadStats()
1151 {
1152     /** Keep track of cycles that each thread is active */
1153     list<ThreadID>::iterator thread_it = activeThreads.begin();
1154     while (thread_it != activeThreads.end()) {
1155         threadCycles[*thread_it]++;
1156         thread_it++;
1157     }
1158
1159     // Keep track of cycles where SMT is active
1160     if (activeThreads.size() > 1) {
1161         smtCycles++;
1162     }
1163 }
1164
1165 void
1166 InOrderCPU::activateContext(ThreadID tid, int delay)
1167 {
1168     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
1169
1170
1171     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
1172
1173     // Be sure to signal that there's some activity so the CPU doesn't
1174     // deschedule itself.
1175     activityRec.activity();
1176
1177     _status = Running;
1178 }
1179
1180 void
1181 InOrderCPU::activateNextReadyContext(int delay)
1182 {
1183     DPRINTF(InOrderCPU,"Activating next ready thread\n");
1184
1185     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
1186                      delay, ActivateNextReadyThread_Pri);
1187
1188     // Be sure to signal that there's some activity so the CPU doesn't
1189     // deschedule itself.
1190     activityRec.activity();
1191
1192     _status = Running;
1193 }
1194
1195 void
1196 InOrderCPU::haltContext(ThreadID tid)
1197 {
1198     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
1199
1200     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid]);
1201
1202     activityRec.activity();
1203 }
1204
1205 void
1206 InOrderCPU::haltThread(ThreadID tid)
1207 {
1208     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
1209     deactivateThread(tid);
1210     squashThreadInPipeline(tid);
1211     haltedThreads.push_back(tid);
1212
1213     tcBase(tid)->setStatus(ThreadContext::Halted);
1214
1215     if (threadModel == SwitchOnCacheMiss) {
1216         activateNextReadyContext();
1217     }
1218 }
1219
1220 void
1221 InOrderCPU::suspendContext(ThreadID tid)
1222 {
1223     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid]);
1224 }
1225
1226 void
1227 InOrderCPU::suspendThread(ThreadID tid)
1228 {
1229     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
1230             tid);
1231     deactivateThread(tid);
1232     suspendedThreads.push_back(tid);
1233     thread[tid]->lastSuspend = curTick();
1234
1235     tcBase(tid)->setStatus(ThreadContext::Suspended);
1236 }
1237
1238 void
1239 InOrderCPU::squashThreadInPipeline(ThreadID tid)
1240 {
1241     //Squash all instructions in each stage
1242     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
1243         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
1244     }
1245 }
1246
1247 PipelineStage*
1248 InOrderCPU::getPipeStage(int stage_num)
1249 {
1250     return pipelineStage[stage_num];
1251 }
1252
1253
1254 RegIndex
1255 InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
1256 {
1257     if (reg_idx < FP_Base_DepTag) {
1258         reg_type = IntType;
1259         return isa[tid].flattenIntIndex(reg_idx);
1260     } else if (reg_idx < Ctrl_Base_DepTag) {
1261         reg_type = FloatType;
1262         reg_idx -= FP_Base_DepTag;
1263         return isa[tid].flattenFloatIndex(reg_idx);
1264     } else {
1265         reg_type = MiscType;
1266         return reg_idx - TheISA::Ctrl_Base_DepTag;
1267     }
1268 }
1269
1270 uint64_t
1271 InOrderCPU::readIntReg(RegIndex reg_idx, ThreadID tid)
1272 {
1273     DPRINTF(IntRegs, "[tid:%i]: Reading Int. Reg %i as %x\n",
1274             tid, reg_idx, intRegs[tid][reg_idx]);
1275
1276     return intRegs[tid][reg_idx];
1277 }
1278
1279 FloatReg
1280 InOrderCPU::readFloatReg(RegIndex reg_idx, ThreadID tid)
1281 {
1282     DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1283             tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
1284
1285     return floatRegs.f[tid][reg_idx];
1286 }
1287
1288 FloatRegBits
1289 InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
1290 {
1291     DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1292             tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
1293
1294     return floatRegs.i[tid][reg_idx];
1295 }
1296
1297 void
1298 InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid)
1299 {
1300     if (reg_idx == TheISA::ZeroReg) {
1301         DPRINTF(IntRegs, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1302                 "(Int. Reg %i) to %x\n", tid, reg_idx, val);
1303         return;
1304     } else {
1305         DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
1306                 tid, reg_idx, val);
1307
1308         intRegs[tid][reg_idx] = val;
1309     }
1310 }
1311
1312
1313 void
1314 InOrderCPU::setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid)
1315 {
1316     floatRegs.f[tid][reg_idx] = val;
1317     DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
1318             "%x, %08f\n",
1319             tid, reg_idx,
1320             floatRegs.i[tid][reg_idx],
1321             floatRegs.f[tid][reg_idx]);
1322 }
1323
1324
1325 void
1326 InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid)
1327 {
1328     floatRegs.i[tid][reg_idx] = val;
1329     DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
1330             "%x, %08f\n",
1331             tid, reg_idx,
1332             floatRegs.i[tid][reg_idx],
1333             floatRegs.f[tid][reg_idx]);
1334 }
1335
1336 uint64_t
1337 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1338 {
1339     // If Default value is set, then retrieve target thread
1340     if (tid == InvalidThreadID) {
1341         tid = TheISA::getTargetThread(tcBase(tid));
1342     }
1343
1344     if (reg_idx < FP_Base_DepTag) {
1345         // Integer Register File
1346         return readIntReg(reg_idx, tid);
1347     } else if (reg_idx < Ctrl_Base_DepTag) {
1348         // Float Register File
1349         reg_idx -= FP_Base_DepTag;
1350         return readFloatRegBits(reg_idx, tid);
1351     } else {
1352         reg_idx -= Ctrl_Base_DepTag;
1353         return readMiscReg(reg_idx, tid);  // Misc. Register File
1354     }
1355 }
1356 void
1357 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1358                               ThreadID tid)
1359 {
1360     // If Default value is set, then retrieve target thread
1361     if (tid == InvalidThreadID) {
1362         tid = TheISA::getTargetThread(tcBase(tid));
1363     }
1364
1365     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1366         setIntReg(reg_idx, val, tid);
1367     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1368         reg_idx -= FP_Base_DepTag;
1369         setFloatRegBits(reg_idx, val, tid);
1370     } else {
1371         reg_idx -= Ctrl_Base_DepTag;
1372         setMiscReg(reg_idx, val, tid); // Misc. Register File
1373     }
1374 }
1375
1376 MiscReg
1377 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1378 {
1379     return isa[tid].readMiscRegNoEffect(misc_reg);
1380 }
1381
1382 MiscReg
1383 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1384 {
1385     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1386 }
1387
1388 void
1389 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1390 {
1391     isa[tid].setMiscRegNoEffect(misc_reg, val);
1392 }
1393
1394 void
1395 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1396 {
1397     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1398 }
1399
1400
1401 InOrderCPU::ListIt
1402 InOrderCPU::addInst(DynInstPtr inst)
1403 {
1404     ThreadID tid = inst->readTid();
1405
1406     instList[tid].push_back(inst);
1407
1408     return --(instList[tid].end());
1409 }
1410
1411 InOrderCPU::ListIt
1412 InOrderCPU::findInst(InstSeqNum seq_num, ThreadID tid)
1413 {
1414     ListIt it = instList[tid].begin();
1415     ListIt end = instList[tid].end();
1416
1417     while (it != end) {
1418         if ((*it)->seqNum == seq_num)
1419             return it;
1420         else if ((*it)->seqNum > seq_num)
1421             break;
1422
1423         it++;
1424     }
1425
1426     return instList[tid].end();
1427 }
1428
1429 void
1430 InOrderCPU::updateContextSwitchStats()
1431 {
1432     // Set Average Stat Here, then reset to 0
1433     instsPerCtxtSwitch = instsPerSwitch;
1434     instsPerSwitch = 0;
1435 }
1436
1437
1438 void
1439 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1440 {
1441     // Set the nextPC to be fetched if this is the last instruction
1442     // committed
1443     // ========
1444     // This contributes to the precise state of the CPU
1445     // which can be used when restoring a thread to the CPU after after any
1446     // type of context switching activity (fork, exception, etc.)
1447     TheISA::PCState comm_pc = inst->pcState();
1448     lastCommittedPC[tid] = comm_pc;
1449     TheISA::advancePC(comm_pc, inst->staticInst);
1450     pcState(comm_pc, tid);
1451
1452     //@todo: may be unnecessary with new-ISA-specific branch handling code
1453     if (inst->isControl()) {
1454         thread[tid]->lastGradIsBranch = true;
1455         thread[tid]->lastBranchPC = inst->pcState();
1456         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1457     } else {
1458         thread[tid]->lastGradIsBranch = false;
1459     }
1460
1461
1462     // Finalize Trace Data For Instruction
1463     if (inst->traceData) {
1464         //inst->traceData->setCycle(curTick());
1465         inst->traceData->setFetchSeq(inst->seqNum);
1466         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1467         inst->traceData->dump();
1468         delete inst->traceData;
1469         inst->traceData = NULL;
1470     }
1471
1472     // Increment active thread's instruction count
1473     instsPerSwitch++;
1474
1475     // Increment thread-state's instruction count
1476     thread[tid]->numInst++;
1477     thread[tid]->numOp++;
1478
1479     // Increment thread-state's instruction stats
1480     thread[tid]->numInsts++;
1481     thread[tid]->numOps++;
1482
1483     // Count committed insts per thread stats
1484     if (!inst->isMicroop() || inst->isLastMicroop()) {
1485         committedInsts[tid]++;
1486
1487         // Count total insts committed stat
1488         totalCommittedInsts++;
1489     }
1490
1491     committedOps[tid]++;
1492
1493     // Count SMT-committed insts per thread stat
1494     if (numActiveThreads() > 1) {
1495         if (!inst->isMicroop() || inst->isLastMicroop())
1496             smtCommittedInsts[tid]++;
1497     }
1498
1499     // Instruction-Mix Stats
1500     if (inst->isLoad()) {
1501         comLoads++;
1502     } else if (inst->isStore()) {
1503         comStores++;
1504     } else if (inst->isControl()) {
1505         comBranches++;
1506     } else if (inst->isNop()) {
1507         comNops++;
1508     } else if (inst->isNonSpeculative()) {
1509         comNonSpec++;
1510     } else if (inst->isInteger()) {
1511         comInts++;
1512     } else if (inst->isFloating()) {
1513         comFloats++;
1514     }
1515
1516     // Check for instruction-count-based events.
1517     comInstEventQueue[tid]->serviceEvents(thread[tid]->numOp);
1518
1519     // Finally, remove instruction from CPU
1520     removeInst(inst);
1521 }
1522
1523 // currently unused function, but substitute repetitive code w/this function
1524 // call
1525 void
1526 InOrderCPU::addToRemoveList(DynInstPtr inst)
1527 {
1528     removeInstsThisCycle = true;
1529     if (!inst->isRemoveList()) {
1530         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1531                 "[sn:%lli] to remove list\n",
1532                 inst->threadNumber, inst->pcState(), inst->seqNum);
1533         inst->setRemoveList();
1534         removeList.push(inst->getInstListIt());
1535     }  else {
1536         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1537                 "[sn:%lli], already remove list\n",
1538                 inst->threadNumber, inst->pcState(), inst->seqNum);
1539     }
1540
1541 }
1542
1543 void
1544 InOrderCPU::removeInst(DynInstPtr inst)
1545 {
1546     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1547             "[sn:%lli]\n",
1548             inst->threadNumber, inst->pcState(), inst->seqNum);
1549
1550     removeInstsThisCycle = true;
1551
1552     // Remove the instruction.
1553     if (!inst->isRemoveList()) {
1554         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1555                 "[sn:%lli] to remove list\n",
1556                 inst->threadNumber, inst->pcState(), inst->seqNum);
1557         inst->setRemoveList();
1558         removeList.push(inst->getInstListIt());
1559     } else {
1560         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1561                 "[sn:%lli], already on remove list\n",
1562                 inst->threadNumber, inst->pcState(), inst->seqNum);
1563     }
1564
1565 }
1566
1567 void
1568 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1569 {
1570     //assert(!instList[tid].empty());
1571
1572     removeInstsThisCycle = true;
1573
1574     ListIt inst_iter = instList[tid].end();
1575
1576     inst_iter--;
1577
1578     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1579             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1580             tid, seq_num, (*inst_iter)->seqNum);
1581
1582     while ((*inst_iter)->seqNum > seq_num) {
1583
1584         bool break_loop = (inst_iter == instList[tid].begin());
1585
1586         squashInstIt(inst_iter, tid);
1587
1588         inst_iter--;
1589
1590         if (break_loop)
1591             break;
1592     }
1593 }
1594
1595
1596 inline void
1597 InOrderCPU::squashInstIt(const ListIt inst_it, ThreadID tid)
1598 {
1599     DynInstPtr inst = (*inst_it);
1600     if (inst->threadNumber == tid) {
1601         DPRINTF(InOrderCPU, "Squashing instruction, "
1602                 "[tid:%i] [sn:%lli] PC %s\n",
1603                 inst->threadNumber,
1604                 inst->seqNum,
1605                 inst->pcState());
1606
1607         inst->setSquashed();
1608         archRegDepMap[tid].remove(inst);
1609
1610         if (!inst->isRemoveList()) {
1611             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1612                     "[sn:%lli] to remove list\n",
1613                     inst->threadNumber, inst->pcState(),
1614                     inst->seqNum);
1615             inst->setRemoveList();
1616             removeList.push(inst_it);
1617         } else {
1618             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1619                     " PC %s [sn:%lli], already on remove list\n",
1620                     inst->threadNumber, inst->pcState(),
1621                     inst->seqNum);
1622         }
1623
1624     }
1625
1626 }
1627
1628
1629 void
1630 InOrderCPU::cleanUpRemovedInsts()
1631 {
1632     while (!removeList.empty()) {
1633         DPRINTF(InOrderCPU, "Removing instruction, "
1634                 "[tid:%i] [sn:%lli] PC %s\n",
1635                 (*removeList.front())->threadNumber,
1636                 (*removeList.front())->seqNum,
1637                (*removeList.front())->pcState());
1638
1639         DynInstPtr inst = *removeList.front();
1640         ThreadID tid = inst->threadNumber;
1641
1642         // Remove From Register Dependency Map, If Necessary
1643         // archRegDepMap[tid].remove(inst);
1644
1645         // Clear if Non-Speculative
1646         if (inst->staticInst &&
1647             inst->seqNum == nonSpecSeqNum[tid] &&
1648             nonSpecInstActive[tid] == true) {
1649             nonSpecInstActive[tid] = false;
1650         }
1651
1652         inst->onInstList = false;
1653
1654         instList[tid].erase(removeList.front());
1655
1656         removeList.pop();
1657     }
1658
1659     removeInstsThisCycle = false;
1660 }
1661
1662 void
1663 InOrderCPU::cleanUpRemovedEvents()
1664 {
1665     while (!cpuEventRemoveList.empty()) {
1666         Event *cpu_event = cpuEventRemoveList.front();
1667         cpuEventRemoveList.pop();
1668         delete cpu_event;
1669     }
1670 }
1671
1672
1673 void
1674 InOrderCPU::dumpInsts()
1675 {
1676     int num = 0;
1677
1678     ListIt inst_list_it = instList[0].begin();
1679
1680     cprintf("Dumping Instruction List\n");
1681
1682     while (inst_list_it != instList[0].end()) {
1683         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1684                 "Squashed:%i\n\n",
1685                 num, (*inst_list_it)->pcState(),
1686                 (*inst_list_it)->threadNumber,
1687                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1688                 (*inst_list_it)->isSquashed());
1689         inst_list_it++;
1690         ++num;
1691     }
1692 }
1693
1694 void
1695 InOrderCPU::wakeCPU()
1696 {
1697     if (/*activityRec.active() || */tickEvent.scheduled()) {
1698         DPRINTF(Activity, "CPU already running.\n");
1699         return;
1700     }
1701
1702     DPRINTF(Activity, "Waking up CPU\n");
1703
1704     Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
1705
1706     idleCycles += extra_cycles;
1707     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1708         pipelineStage[stage_num]->idleCycles += extra_cycles;
1709     }
1710
1711     numCycles += extra_cycles;
1712
1713     schedule(&tickEvent, nextCycle(curTick()));
1714 }
1715
1716 // Lots of copied full system code...place into BaseCPU class?
1717 void
1718 InOrderCPU::wakeup()
1719 {
1720     if (thread[0]->status() != ThreadContext::Suspended)
1721         return;
1722
1723     wakeCPU();
1724
1725     DPRINTF(Quiesce, "Suspended Processor woken\n");
1726     threadContexts[0]->activate();
1727 }
1728
1729 void
1730 InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
1731 {
1732     // Syscall must be non-speculative, so squash from last stage
1733     unsigned squash_stage = NumStages - 1;
1734     inst->setSquashInfo(squash_stage);
1735
1736     // Squash In Pipeline Stage
1737     pipelineStage[squash_stage]->setupSquash(inst, tid);
1738
1739     // Schedule Squash Through-out Resource Pool
1740     resPool->scheduleEvent(
1741         (InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
1742     scheduleCpuEvent(Syscall, fault, tid, inst, delay, Syscall_Pri);
1743 }
1744
1745 void
1746 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1747 {
1748     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1749
1750     DPRINTF(Activity,"Activity: syscall() called.\n");
1751
1752     // Temporarily increase this by one to account for the syscall
1753     // instruction.
1754     ++(this->thread[tid]->funcExeInst);
1755
1756     // Execute the actual syscall.
1757     this->thread[tid]->syscall(callnum);
1758
1759     // Decrease funcExeInst by one as the normal commit will handle
1760     // incrementing it.
1761     --(this->thread[tid]->funcExeInst);
1762
1763     // Clear Non-Speculative Block Variable
1764     nonSpecInstActive[tid] = false;
1765 }
1766
1767 TheISA::TLB*
1768 InOrderCPU::getITBPtr()
1769 {
1770     CacheUnit *itb_res = resPool->getInstUnit();
1771     return itb_res->tlb();
1772 }
1773
1774
1775 TheISA::TLB*
1776 InOrderCPU::getDTBPtr()
1777 {
1778     return resPool->getDataUnit()->tlb();
1779 }
1780
1781 Decoder *
1782 InOrderCPU::getDecoderPtr()
1783 {
1784     return &resPool->getInstUnit()->decoder;
1785 }
1786
1787 Fault
1788 InOrderCPU::read(DynInstPtr inst, Addr addr,
1789                  uint8_t *data, unsigned size, unsigned flags)
1790 {
1791     return resPool->getDataUnit()->read(inst, addr, data, size, flags);
1792 }
1793
1794 Fault
1795 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1796                   Addr addr, unsigned flags, uint64_t *write_res)
1797 {
1798     return resPool->getDataUnit()->write(inst, data, size, addr, flags,
1799                                          write_res);
1800 }