src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007 MIPS Technologies, Inc.
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Korey Sewell
  41  *
  42  */
  43
  44 #include <algorithm>
  45
  46 #include "arch/utility.hh"
  47 #include "base/bigint.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/inorder/resources/cache_unit.hh"
  50 #include "cpu/inorder/resources/resource_list.hh"
  51 #include "cpu/inorder/cpu.hh"
  52 #include "cpu/inorder/first_stage.hh"
  53 #include "cpu/inorder/inorder_dyn_inst.hh"
  54 #include "cpu/inorder/pipeline_traits.hh"
  55 #include "cpu/inorder/resource_pool.hh"
  56 #include "cpu/inorder/thread_context.hh"
  57 #include "cpu/inorder/thread_state.hh"
  58 #include "cpu/activity.hh"
  59 #include "cpu/base.hh"
  60 #include "cpu/exetrace.hh"
  61 #include "cpu/quiesce_event.hh"
  62 #include "cpu/simple_thread.hh"
  63 #include "cpu/thread_context.hh"
  64 #include "debug/Activity.hh"
  65 #include "debug/InOrderCPU.hh"
  66 #include "debug/InOrderCachePort.hh"
  67 #include "debug/Interrupt.hh"
  68 #include "debug/Quiesce.hh"
  69 #include "debug/RefCount.hh"
  70 #include "debug/SkedCache.hh"
  71 #include "params/InOrderCPU.hh"
  72 #include "sim/full_system.hh"
  73 #include "sim/process.hh"
  74 #include "sim/stat_control.hh"
  75 #include "sim/system.hh"
  76
  77 #if THE_ISA == ALPHA_ISA
  78 #include "arch/alpha/osfpal.hh"
  79 #endif
  80
  81 using namespace std;
  82 using namespace TheISA;
  83 using namespace ThePipeline;
  84
  85 InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit) :
  86     CpuPort(_cacheUnit->name() + "-cache-port", _cacheUnit->cpu),
  87     cacheUnit(_cacheUnit)
  88 { }
  89
  90 bool
  91 InOrderCPU::CachePort::recvTimingResp(Packet *pkt)
  92 {
  93     if (pkt->isError())
  94         DPRINTF(InOrderCachePort, "Got error packet back for address: %x\n",
  95                 pkt->getAddr());
  96     else
  97         cacheUnit->processCacheCompletion(pkt);
  98
  99     return true;
 100 }
 101
 102 void
 103 InOrderCPU::CachePort::recvRetry()
 104 {
 105     cacheUnit->recvRetry();
 106 }
 107
 108 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
 109   : Event(CPU_Tick_Pri), cpu(c)
 110 { }
 111
 112
 113 void
 114 InOrderCPU::TickEvent::process()
 115 {
 116     cpu->tick();
 117 }
 118
 119
 120 const char *
 121 InOrderCPU::TickEvent::description() const
 122 {
 123     return "InOrderCPU tick event";
 124 }
 125
 126 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
 127                                Fault fault, ThreadID _tid, DynInstPtr inst,
 128                                CPUEventPri event_pri)
 129     : Event(event_pri), cpu(_cpu)
 130 {
 131     setEvent(e_type, fault, _tid, inst);
 132 }
 133
 134
 135 std::string InOrderCPU::eventNames[NumCPUEvents] =
 136 {
 137     "ActivateThread",
 138     "ActivateNextReadyThread",
 139     "DeactivateThread",
 140     "HaltThread",
 141     "SuspendThread",
 142     "Trap",
 143     "Syscall",
 144     "SquashFromMemStall",
 145     "UpdatePCs"
 146 };
 147
 148 void
 149 InOrderCPU::CPUEvent::process()
 150 {
 151     switch (cpuEventType)
 152     {
 153       case ActivateThread:
 154         cpu->activateThread(tid);
 155         cpu->resPool->activateThread(tid);
 156         break;
 157
 158       case ActivateNextReadyThread:
 159         cpu->activateNextReadyThread();
 160         break;
 161
 162       case DeactivateThread:
 163         cpu->deactivateThread(tid);
 164         cpu->resPool->deactivateThread(tid);
 165         break;
 166
 167       case HaltThread:
 168         cpu->haltThread(tid);
 169         cpu->resPool->deactivateThread(tid);
 170         break;
 171
 172       case SuspendThread:
 173         cpu->suspendThread(tid);
 174         cpu->resPool->suspendThread(tid);
 175         break;
 176
 177       case SquashFromMemStall:
 178         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 179         cpu->resPool->squashDueToMemStall(inst, inst->squashingStage,
 180                                           inst->seqNum, tid);
 181         break;
 182
 183       case Trap:
 184         DPRINTF(InOrderCPU, "Trapping CPU\n");
 185         cpu->trap(fault, tid, inst);
 186         cpu->resPool->trap(fault, tid, inst);
 187         cpu->trapPending[tid] = false;
 188         break;
 189
 190       case Syscall:
 191         cpu->syscall(inst->syscallNum, tid);
 192         cpu->resPool->trap(fault, tid, inst);
 193         break;
 194
 195       default:
 196         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 197     }
 198
 199     cpu->cpuEventRemoveList.push(this);
 200 }
 201
 202
 203
 204 const char *
 205 InOrderCPU::CPUEvent::description() const
 206 {
 207     return "InOrderCPU event";
 208 }
 209
 210 void
 211 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 212 {
 213     assert(!scheduled() || squashed());
 214     cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
 215 }
 216
 217 void
 218 InOrderCPU::CPUEvent::unscheduleEvent()
 219 {
 220     if (scheduled())
 221         squash();
 222 }
 223
 224 InOrderCPU::InOrderCPU(Params *params)
 225     : BaseCPU(params),
 226       cpu_id(params->cpu_id),
 227       coreType("default"),
 228       _status(Idle),
 229       tickEvent(this),
 230       stageWidth(params->stageWidth),
 231       resPool(new ResourcePool(this, params)),
 232       timeBuffer(2 , 2),
 233       dataPort(resPool->getDataUnit()),
 234       instPort(resPool->getInstUnit()),
 235       removeInstsThisCycle(false),
 236       activityRec(params->name, NumStages, 10, params->activity),
 237       system(params->system),
 238 #ifdef DEBUG
 239       cpuEventNum(0),
 240       resReqCount(0),
 241 #endif // DEBUG
 242       drainCount(0),
 243       deferRegistration(false/*params->deferRegistration*/),
 244       stageTracing(params->stageTracing),
 245       lastRunningCycle(0),
 246       instsPerSwitch(0)
 247 {
 248     cpu_params = params;
 249
 250     // Resize for Multithreading CPUs
 251     thread.resize(numThreads);
 252
 253     ThreadID active_threads = params->workload.size();
 254     if (FullSystem) {
 255         active_threads = 1;
 256     } else {
 257         active_threads = params->workload.size();
 258
 259         if (active_threads > MaxThreads) {
 260             panic("Workload Size too large. Increase the 'MaxThreads'"
 261                   "in your InOrder implementation or "
 262                   "edit your workload size.");
 263         }
 264
 265
 266         if (active_threads > 1) {
 267             threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 268
 269             if (threadModel == SMT) {
 270                 DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 271             } else if (threadModel == SwitchOnCacheMiss) {
 272                 DPRINTF(InOrderCPU, "Setting Thread Model to "
 273                         "Switch On Cache Miss\n");
 274             }
 275
 276         } else {
 277             threadModel = Single;
 278         }
 279     }
 280
 281     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 282         pc[tid].set(0);
 283         lastCommittedPC[tid].set(0);
 284
 285         if (FullSystem) {
 286             // SMT is not supported in FS mode yet.
 287             assert(numThreads == 1);
 288             thread[tid] = new Thread(this, 0, NULL);
 289         } else {
 290             if (tid < (ThreadID)params->workload.size()) {
 291                 DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 292                         tid, params->workload[tid]->prog_fname);
 293                 thread[tid] =
 294                     new Thread(this, tid, params->workload[tid]);
 295             } else {
 296                 //Allocate Empty thread so M5 can use later
 297                 //when scheduling threads to CPU
 298                 Process* dummy_proc = params->workload[0];
 299                 thread[tid] = new Thread(this, tid, dummy_proc);
 300             }
 301
 302             // Eventually set this with parameters...
 303             asid[tid] = tid;
 304         }
 305
 306         // Setup the TC that will serve as the interface to the threads/CPU.
 307         InOrderThreadContext *tc = new InOrderThreadContext;
 308         tc->cpu = this;
 309         tc->thread = thread[tid];
 310
 311         // Setup quiesce event.
 312         this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
 313
 314         // Give the thread the TC.
 315         thread[tid]->tc = tc;
 316         thread[tid]->setFuncExeInst(0);
 317         globalSeqNum[tid] = 1;
 318
 319         // Add the TC to the CPU's list of TC's.
 320         this->threadContexts.push_back(tc);
 321     }
 322
 323     // Initialize TimeBuffer Stage Queues
 324     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 325         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 326         stageQueue[stNum]->id(stNum);
 327     }
 328
 329
 330     // Set Up Pipeline Stages
 331     for (int stNum=0; stNum < NumStages; stNum++) {
 332         if (stNum == 0)
 333             pipelineStage[stNum] = new FirstStage(params, stNum);
 334         else
 335             pipelineStage[stNum] = new PipelineStage(params, stNum);
 336
 337         pipelineStage[stNum]->setCPU(this);
 338         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 339         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 340
 341         // Take Care of 1st/Nth stages
 342         if (stNum > 0)
 343             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 344         if (stNum < NumStages - 1)
 345             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 346     }
 347
 348     // Initialize thread specific variables
 349     for (ThreadID tid = 0; tid < numThreads; tid++) {
 350         archRegDepMap[tid].setCPU(this);
 351
 352         nonSpecInstActive[tid] = false;
 353         nonSpecSeqNum[tid] = 0;
 354
 355         squashSeqNum[tid] = MaxAddr;
 356         lastSquashCycle[tid] = 0;
 357
 358         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 359         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 360         isa[tid].clear();
 361
 362         // Define dummy instructions and resource requests to be used.
 363         dummyInst[tid] = new InOrderDynInst(this,
 364                                             thread[tid],
 365                                             0,
 366                                             tid,
 367                                             asid[tid]);
 368
 369         dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
 370
 371
 372         if (FullSystem) {
 373             // Use this dummy inst to force squashing behind every instruction
 374             // in pipeline
 375             dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
 376             dummyTrapInst[tid]->seqNum = 0;
 377             dummyTrapInst[tid]->squashSeqNum = 0;
 378             dummyTrapInst[tid]->setTid(tid);
 379         }
 380
 381         trapPending[tid] = false;
 382
 383     }
 384
 385     // InOrderCPU always requires an interrupt controller.
 386     if (!params->defer_registration && !interrupts) {
 387         fatal("InOrderCPU %s has no interrupt controller.\n"
 388               "Ensure createInterruptController() is called.\n", name());
 389     }
 390
 391     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 392     dummyReqInst->setSquashed();
 393     dummyReqInst->resetInstCount();
 394
 395     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 396     dummyBufferInst->setSquashed();
 397     dummyBufferInst->resetInstCount();
 398
 399     endOfSkedIt = skedCache.end();
 400     frontEndSked = createFrontEndSked();
 401     faultSked = createFaultSked();
 402
 403     lastRunningCycle = curTick();
 404
 405     lockAddr = 0;
 406     lockFlag = false;
 407
 408     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 409     scheduleTickEvent(0);
 410 }
 411
 412 InOrderCPU::~InOrderCPU()
 413 {
 414     delete resPool;
 415
 416     SkedCacheIt sked_it = skedCache.begin();
 417     SkedCacheIt sked_end = skedCache.end();
 418
 419     while (sked_it != sked_end) {
 420         delete (*sked_it).second;
 421         sked_it++;
 422     }
 423     skedCache.clear();
 424 }
 425
 426 m5::hash_map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
 427
 428 RSkedPtr
 429 InOrderCPU::createFrontEndSked()
 430 {
 431     RSkedPtr res_sked = new ResourceSked();
 432     int stage_num = 0;
 433     StageScheduler F(res_sked, stage_num++);
 434     StageScheduler D(res_sked, stage_num++);
 435
 436     // FETCH
 437     F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
 438     F.needs(ICache, FetchUnit::InitiateFetch);
 439
 440     // DECODE
 441     D.needs(ICache, FetchUnit::CompleteFetch);
 442     D.needs(Decode, DecodeUnit::DecodeInst);
 443     D.needs(BPred, BranchPredictor::PredictBranch);
 444     D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
 445
 446
 447     DPRINTF(SkedCache, "Resource Sked created for instruction Front End\n");
 448
 449     return res_sked;
 450 }
 451
 452 RSkedPtr
 453 InOrderCPU::createFaultSked()
 454 {
 455     RSkedPtr res_sked = new ResourceSked();
 456     StageScheduler W(res_sked, NumStages - 1);
 457     W.needs(Grad, GraduationUnit::CheckFault);
 458     DPRINTF(SkedCache, "Resource Sked created for instruction Faults\n");
 459     return res_sked;
 460 }
 461
 462 RSkedPtr
 463 InOrderCPU::createBackEndSked(DynInstPtr inst)
 464 {
 465     RSkedPtr res_sked = lookupSked(inst);
 466     if (res_sked != NULL) {
 467         DPRINTF(SkedCache, "Found %s in sked cache.\n",
 468                 inst->instName());
 469         return res_sked;
 470     } else {
 471         res_sked = new ResourceSked();
 472     }
 473
 474     int stage_num = ThePipeline::BackEndStartStage;
 475     StageScheduler X(res_sked, stage_num++);
 476     StageScheduler M(res_sked, stage_num++);
 477     StageScheduler W(res_sked, stage_num++);
 478
 479     if (!inst->staticInst) {
 480         warn_once("Static Instruction Object Not Set. Can't Create"
 481                   " Back End Schedule");
 482         return NULL;
 483     }
 484
 485     // EXECUTE
 486     X.needs(RegManager, UseDefUnit::MarkDestRegs);
 487     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 488         if (!idx || !inst->isStore()) {
 489             X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
 490         }
 491     }
 492
 493     //@todo: schedule non-spec insts to operate on this cycle
 494     // as long as all previous insts are done
 495     if ( inst->isNonSpeculative() ) {
 496         // skip execution of non speculative insts until later
 497     } else if ( inst->isMemRef() ) {
 498         if ( inst->isLoad() ) {
 499             X.needs(AGEN, AGENUnit::GenerateAddr);
 500         }
 501     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 502         X.needs(MDU, MultDivUnit::StartMultDiv);
 503     } else {
 504         X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 505     }
 506
 507     // MEMORY
 508     if (!inst->isNonSpeculative()) {
 509         if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 510             M.needs(MDU, MultDivUnit::EndMultDiv);
 511         }
 512
 513         if ( inst->isLoad() ) {
 514             M.needs(DCache, CacheUnit::InitiateReadData);
 515             if (inst->splitInst)
 516                 M.needs(DCache, CacheUnit::InitSecondSplitRead);
 517         } else if ( inst->isStore() ) {
 518             for (int i = 1; i < inst->numSrcRegs(); i++ ) {
 519                 M.needs(RegManager, UseDefUnit::ReadSrcReg, i);
 520             }
 521             M.needs(AGEN, AGENUnit::GenerateAddr);
 522             M.needs(DCache, CacheUnit::InitiateWriteData);
 523             if (inst->splitInst)
 524                 M.needs(DCache, CacheUnit::InitSecondSplitWrite);
 525         }
 526     }
 527
 528     // WRITEBACK
 529     if (!inst->isNonSpeculative()) {
 530         if ( inst->isLoad() ) {
 531             W.needs(DCache, CacheUnit::CompleteReadData);
 532             if (inst->splitInst)
 533                 W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
 534         } else if ( inst->isStore() ) {
 535             W.needs(DCache, CacheUnit::CompleteWriteData);
 536             if (inst->splitInst)
 537                 W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
 538         }
 539     } else {
 540         // Finally, Execute Speculative Data
 541         if (inst->isMemRef()) {
 542             if (inst->isLoad()) {
 543                 W.needs(AGEN, AGENUnit::GenerateAddr);
 544                 W.needs(DCache, CacheUnit::InitiateReadData);
 545                 if (inst->splitInst)
 546                     W.needs(DCache, CacheUnit::InitSecondSplitRead);
 547                 W.needs(DCache, CacheUnit::CompleteReadData);
 548                 if (inst->splitInst)
 549                     W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
 550             } else if (inst->isStore()) {
 551                 if ( inst->numSrcRegs() >= 2 ) {
 552                     W.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 553                 }
 554                 W.needs(AGEN, AGENUnit::GenerateAddr);
 555                 W.needs(DCache, CacheUnit::InitiateWriteData);
 556                 if (inst->splitInst)
 557                     W.needs(DCache, CacheUnit::InitSecondSplitWrite);
 558                 W.needs(DCache, CacheUnit::CompleteWriteData);
 559                 if (inst->splitInst)
 560                     W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
 561             }
 562         } else {
 563             W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 564         }
 565     }
 566
 567     W.needs(Grad, GraduationUnit::CheckFault);
 568
 569     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 570         W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
 571     }
 572
 573     if (inst->isControl())
 574         W.needs(BPred, BranchPredictor::UpdatePredictor);
 575
 576     W.needs(Grad, GraduationUnit::GraduateInst);
 577
 578     // Insert Back Schedule into our cache of
 579     // resource schedules
 580     addToSkedCache(inst, res_sked);
 581
 582     DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
 583             inst->instName(), inst->getMachInst());
 584     res_sked->print();
 585
 586     return res_sked;
 587 }
 588
 589 void
 590 InOrderCPU::regStats()
 591 {
 592     /* Register the Resource Pool's stats here.*/
 593     resPool->regStats();
 594
 595     /* Register for each Pipeline Stage */
 596     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 597         pipelineStage[stage_num]->regStats();
 598     }
 599
 600     /* Register any of the InOrderCPU's stats here.*/
 601     instsPerCtxtSwitch
 602         .name(name() + ".instsPerContextSwitch")
 603         .desc("Instructions Committed Per Context Switch")
 604         .prereq(instsPerCtxtSwitch);
 605
 606     numCtxtSwitches
 607         .name(name() + ".contextSwitches")
 608         .desc("Number of context switches");
 609
 610     comLoads
 611         .name(name() + ".comLoads")
 612         .desc("Number of Load instructions committed");
 613
 614     comStores
 615         .name(name() + ".comStores")
 616         .desc("Number of Store instructions committed");
 617
 618     comBranches
 619         .name(name() + ".comBranches")
 620         .desc("Number of Branches instructions committed");
 621
 622     comNops
 623         .name(name() + ".comNops")
 624         .desc("Number of Nop instructions committed");
 625
 626     comNonSpec
 627         .name(name() + ".comNonSpec")
 628         .desc("Number of Non-Speculative instructions committed");
 629
 630     comInts
 631         .name(name() + ".comInts")
 632         .desc("Number of Integer instructions committed");
 633
 634     comFloats
 635         .name(name() + ".comFloats")
 636         .desc("Number of Floating Point instructions committed");
 637
 638     timesIdled
 639         .name(name() + ".timesIdled")
 640         .desc("Number of times that the entire CPU went into an idle state and"
 641               " unscheduled itself")
 642         .prereq(timesIdled);
 643
 644     idleCycles
 645         .name(name() + ".idleCycles")
 646         .desc("Number of cycles cpu's stages were not processed");
 647
 648     runCycles
 649         .name(name() + ".runCycles")
 650         .desc("Number of cycles cpu stages are processed.");
 651
 652     activity
 653         .name(name() + ".activity")
 654         .desc("Percentage of cycles cpu is active")
 655         .precision(6);
 656     activity = (runCycles / numCycles) * 100;
 657
 658     threadCycles
 659         .init(numThreads)
 660         .name(name() + ".threadCycles")
 661         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 662
 663     smtCycles
 664         .name(name() + ".smtCycles")
 665         .desc("Total number of cycles that the CPU was in SMT-mode");
 666
 667     committedInsts
 668         .init(numThreads)
 669         .name(name() + ".committedInsts")
 670         .desc("Number of Instructions committed (Per-Thread)");
 671
 672     committedOps
 673         .init(numThreads)
 674         .name(name() + ".committedOps")
 675         .desc("Number of Ops committed (Per-Thread)");
 676
 677     smtCommittedInsts
 678         .init(numThreads)
 679         .name(name() + ".smtCommittedInsts")
 680         .desc("Number of SMT Instructions committed (Per-Thread)");
 681
 682     totalCommittedInsts
 683         .name(name() + ".committedInsts_total")
 684         .desc("Number of Instructions committed (Total)");
 685
 686     cpi
 687         .name(name() + ".cpi")
 688         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 689         .precision(6);
 690     cpi = numCycles / committedInsts;
 691
 692     smtCpi
 693         .name(name() + ".smt_cpi")
 694         .desc("CPI: Total SMT-CPI")
 695         .precision(6);
 696     smtCpi = smtCycles / smtCommittedInsts;
 697
 698     totalCpi
 699         .name(name() + ".cpi_total")
 700         .desc("CPI: Total CPI of All Threads")
 701         .precision(6);
 702     totalCpi = numCycles / totalCommittedInsts;
 703
 704     ipc
 705         .name(name() + ".ipc")
 706         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 707         .precision(6);
 708     ipc =  committedInsts / numCycles;
 709
 710     smtIpc
 711         .name(name() + ".smt_ipc")
 712         .desc("IPC: Total SMT-IPC")
 713         .precision(6);
 714     smtIpc = smtCommittedInsts / smtCycles;
 715
 716     totalIpc
 717         .name(name() + ".ipc_total")
 718         .desc("IPC: Total IPC of All Threads")
 719         .precision(6);
 720         totalIpc =  totalCommittedInsts / numCycles;
 721
 722     BaseCPU::regStats();
 723 }
 724
 725
 726 void
 727 InOrderCPU::tick()
 728 {
 729     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 730
 731     ++numCycles;
 732
 733     checkForInterrupts();
 734
 735     bool pipes_idle = true;
 736     //Tick each of the stages
 737     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 738         pipelineStage[stNum]->tick();
 739
 740         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 741     }
 742
 743     if (pipes_idle)
 744         idleCycles++;
 745     else
 746         runCycles++;
 747
 748     // Now advance the time buffers one tick
 749     timeBuffer.advance();
 750     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 751         stageQueue[sqNum]->advance();
 752     }
 753     activityRec.advance();
 754
 755     // Any squashed events, or insts then remove them now
 756     cleanUpRemovedEvents();
 757     cleanUpRemovedInsts();
 758
 759     // Re-schedule CPU for this cycle
 760     if (!tickEvent.scheduled()) {
 761         if (_status == SwitchedOut) {
 762             // increment stat
 763             lastRunningCycle = curTick();
 764         } else if (!activityRec.active()) {
 765             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 766             lastRunningCycle = curTick();
 767             timesIdled++;
 768         } else {
 769             //Tick next_tick = curTick() + cycles(1);
 770             //tickEvent.schedule(next_tick);
 771             schedule(&tickEvent, nextCycle(curTick() + 1));
 772             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 773                     nextCycle(curTick() + 1));
 774         }
 775     }
 776
 777     tickThreadStats();
 778     updateThreadPriority();
 779 }
 780
 781
 782 void
 783 InOrderCPU::init()
 784 {
 785     BaseCPU::init();
 786
 787     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 788         // Set inSyscall so that the CPU doesn't squash when initially
 789         // setting up registers.
 790         thread[tid]->inSyscall = true;
 791         // Initialise the ThreadContext's memory proxies
 792         thread[tid]->initMemProxies(thread[tid]->getTC());
 793     }
 794
 795     if (FullSystem) {
 796         for (ThreadID tid = 0; tid < numThreads; tid++) {
 797             ThreadContext *src_tc = threadContexts[tid];
 798             TheISA::initCPU(src_tc, src_tc->contextId());
 799         }
 800     }
 801
 802     // Clear inSyscall.
 803     for (ThreadID tid = 0; tid < numThreads; ++tid)
 804         thread[tid]->inSyscall = false;
 805
 806     // Call Initializiation Routine for Resource Pool
 807     resPool->init();
 808 }
 809
 810 Fault
 811 InOrderCPU::hwrei(ThreadID tid)
 812 {
 813 #if THE_ISA == ALPHA_ISA
 814     // Need to clear the lock flag upon returning from an interrupt.
 815     setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
 816
 817     thread[tid]->kernelStats->hwrei();
 818     // FIXME: XXX check for interrupts? XXX
 819 #endif
 820
 821     return NoFault;
 822 }
 823
 824
 825 bool
 826 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 827 {
 828 #if THE_ISA == ALPHA_ISA
 829     if (this->thread[tid]->kernelStats)
 830         this->thread[tid]->kernelStats->callpal(palFunc,
 831                                                 this->threadContexts[tid]);
 832
 833     switch (palFunc) {
 834       case PAL::halt:
 835         halt();
 836         if (--System::numSystemsRunning == 0)
 837             exitSimLoop("all cpus halted");
 838         break;
 839
 840       case PAL::bpt:
 841       case PAL::bugchk:
 842         if (this->system->breakpoint())
 843             return false;
 844         break;
 845     }
 846 #endif
 847     return true;
 848 }
 849
 850 void
 851 InOrderCPU::checkForInterrupts()
 852 {
 853     for (int i = 0; i < threadContexts.size(); i++) {
 854         ThreadContext *tc = threadContexts[i];
 855
 856         if (interrupts->checkInterrupts(tc)) {
 857             Fault interrupt = interrupts->getInterrupt(tc);
 858
 859             if (interrupt != NoFault) {
 860                 DPRINTF(Interrupt, "Processing Intterupt for [tid:%i].\n",
 861                         tc->threadId());
 862
 863                 ThreadID tid = tc->threadId();
 864                 interrupts->updateIntrInfo(tc);
 865
 866                 // Squash from Last Stage in Pipeline
 867                 unsigned last_stage = NumStages - 1;
 868                 dummyTrapInst[tid]->squashingStage = last_stage;
 869                 pipelineStage[last_stage]->setupSquash(dummyTrapInst[tid],
 870                                                        tid);
 871
 872                 // By default, setupSquash will always squash from stage + 1
 873                 pipelineStage[BackEndStartStage - 1]->setupSquash(dummyTrapInst[tid],
 874                                                                   tid);
 875
 876                 // Schedule Squash Through-out Resource Pool
 877                 resPool->scheduleEvent(
 878                     (InOrderCPU::CPUEventType)ResourcePool::SquashAll,
 879                     dummyTrapInst[tid], 0);
 880
 881                 // Finally, Setup Trap to happen at end of cycle
 882                 trapContext(interrupt, tid, dummyTrapInst[tid]);
 883             }
 884         }
 885     }
 886 }
 887
 888 Fault
 889 InOrderCPU::getInterrupts()
 890 {
 891     // Check if there are any outstanding interrupts
 892     return interrupts->getInterrupt(threadContexts[0]);
 893 }
 894
 895 void
 896 InOrderCPU::processInterrupts(Fault interrupt)
 897 {
 898     // Check for interrupts here.  For now can copy the code that
 899     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 900     // is the one that handles the interrupts.
 901     // @todo: Possibly consolidate the interrupt checking code.
 902     // @todo: Allow other threads to handle interrupts.
 903
 904     assert(interrupt != NoFault);
 905     interrupts->updateIntrInfo(threadContexts[0]);
 906
 907     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 908
 909     // Note: Context ID ok here? Impl. of FS mode needs to revisit this
 910     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 911 }
 912
 913 void
 914 InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 915 {
 916     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 917     trapPending[tid] = true;
 918 }
 919
 920 void
 921 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 922 {
 923     fault->invoke(tcBase(tid), inst->staticInst);
 924     removePipelineStalls(tid);
 925 }
 926
 927 void
 928 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 929 {
 930     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 931 }
 932
 933
 934 void
 935 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 936                                 ThreadID tid)
 937 {
 938     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 939
 940     // Squash all instructions in each stage including
 941     // instruction that caused the squash (seq_num - 1)
 942     // NOTE: The stage bandwidth needs to be cleared so thats why
 943     //       the stalling instruction is squashed as well. The stalled
 944     //       instruction is previously placed in another intermediate buffer
 945     //       while it's stall is being handled.
 946     InstSeqNum squash_seq_num = seq_num - 1;
 947
 948     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 949         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 950     }
 951 }
 952
 953 void
 954 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 955                              ThreadID tid, DynInstPtr inst,
 956                              unsigned delay, CPUEventPri event_pri)
 957 {
 958     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 959                                        event_pri);
 960
 961     Tick sked_tick = nextCycle(curTick() + ticks(delay));
 962     if (delay >= 0) {
 963         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 964                 eventNames[c_event], curTick() + delay, tid);
 965         schedule(cpu_event, sked_tick);
 966     } else {
 967         cpu_event->process();
 968         cpuEventRemoveList.push(cpu_event);
 969     }
 970
 971     // Broadcast event to the Resource Pool
 972     // Need to reset tid just in case this is a dummy instruction
 973     inst->setTid(tid);
 974     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 975 }
 976
 977 bool
 978 InOrderCPU::isThreadActive(ThreadID tid)
 979 {
 980   list<ThreadID>::iterator isActive =
 981       std::find(activeThreads.begin(), activeThreads.end(), tid);
 982
 983     return (isActive != activeThreads.end());
 984 }
 985
 986 bool
 987 InOrderCPU::isThreadReady(ThreadID tid)
 988 {
 989   list<ThreadID>::iterator isReady =
 990       std::find(readyThreads.begin(), readyThreads.end(), tid);
 991
 992     return (isReady != readyThreads.end());
 993 }
 994
 995 bool
 996 InOrderCPU::isThreadSuspended(ThreadID tid)
 997 {
 998   list<ThreadID>::iterator isSuspended =
 999       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
1000
1001     return (isSuspended != suspendedThreads.end());
1002 }
1003
1004 void
1005 InOrderCPU::activateNextReadyThread()
1006 {
1007     if (readyThreads.size() >= 1) {
1008         ThreadID ready_tid = readyThreads.front();
1009
1010         // Activate in Pipeline
1011         activateThread(ready_tid);
1012
1013         // Activate in Resource Pool
1014         resPool->activateThread(ready_tid);
1015
1016         list<ThreadID>::iterator ready_it =
1017             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
1018         readyThreads.erase(ready_it);
1019     } else {
1020         DPRINTF(InOrderCPU,
1021                 "Attempting to activate new thread, but No Ready Threads to"
1022                 "activate.\n");
1023         DPRINTF(InOrderCPU,
1024                 "Unable to switch to next active thread.\n");
1025     }
1026 }
1027
1028 void
1029 InOrderCPU::activateThread(ThreadID tid)
1030 {
1031     if (isThreadSuspended(tid)) {
1032         DPRINTF(InOrderCPU,
1033                 "Removing [tid:%i] from suspended threads list.\n", tid);
1034
1035         list<ThreadID>::iterator susp_it =
1036             std::find(suspendedThreads.begin(), suspendedThreads.end(),
1037                       tid);
1038         suspendedThreads.erase(susp_it);
1039     }
1040
1041     if (threadModel == SwitchOnCacheMiss &&
1042         numActiveThreads() == 1) {
1043         DPRINTF(InOrderCPU,
1044                 "Ignoring activation of [tid:%i], since [tid:%i] is "
1045                 "already running.\n", tid, activeThreadId());
1046
1047         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
1048                 tid);
1049
1050         readyThreads.push_back(tid);
1051
1052     } else if (!isThreadActive(tid)) {
1053         DPRINTF(InOrderCPU,
1054                 "Adding [tid:%i] to active threads list.\n", tid);
1055         activeThreads.push_back(tid);
1056
1057         activateThreadInPipeline(tid);
1058
1059         thread[tid]->lastActivate = curTick();
1060
1061         tcBase(tid)->setStatus(ThreadContext::Active);
1062
1063         wakeCPU();
1064
1065         numCtxtSwitches++;
1066     }
1067 }
1068
1069 void
1070 InOrderCPU::activateThreadInPipeline(ThreadID tid)
1071 {
1072     for (int stNum=0; stNum < NumStages; stNum++) {
1073         pipelineStage[stNum]->activateThread(tid);
1074     }
1075 }
1076
1077 void
1078 InOrderCPU::deactivateContext(ThreadID tid, int delay)
1079 {
1080     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
1081
1082     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
1083
1084     // Be sure to signal that there's some activity so the CPU doesn't
1085     // deschedule itself.
1086     activityRec.activity();
1087
1088     _status = Running;
1089 }
1090
1091 void
1092 InOrderCPU::deactivateThread(ThreadID tid)
1093 {
1094     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
1095
1096     if (isThreadActive(tid)) {
1097         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
1098                 tid);
1099         list<ThreadID>::iterator thread_it =
1100             std::find(activeThreads.begin(), activeThreads.end(), tid);
1101
1102         removePipelineStalls(*thread_it);
1103
1104         activeThreads.erase(thread_it);
1105
1106         // Ideally, this should be triggered from the
1107         // suspendContext/Thread functions
1108         tcBase(tid)->setStatus(ThreadContext::Suspended);
1109     }
1110
1111     assert(!isThreadActive(tid));
1112 }
1113
1114 void
1115 InOrderCPU::removePipelineStalls(ThreadID tid)
1116 {
1117     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
1118             tid);
1119
1120     for (int stNum = 0; stNum < NumStages ; stNum++) {
1121         pipelineStage[stNum]->removeStalls(tid);
1122     }
1123
1124 }
1125
1126 void
1127 InOrderCPU::updateThreadPriority()
1128 {
1129     if (activeThreads.size() > 1)
1130     {
1131         //DEFAULT TO ROUND ROBIN SCHEME
1132         //e.g. Move highest priority to end of thread list
1133         list<ThreadID>::iterator list_begin = activeThreads.begin();
1134
1135         unsigned high_thread = *list_begin;
1136
1137         activeThreads.erase(list_begin);
1138
1139         activeThreads.push_back(high_thread);
1140     }
1141 }
1142
1143 inline void
1144 InOrderCPU::tickThreadStats()
1145 {
1146     /** Keep track of cycles that each thread is active */
1147     list<ThreadID>::iterator thread_it = activeThreads.begin();
1148     while (thread_it != activeThreads.end()) {
1149         threadCycles[*thread_it]++;
1150         thread_it++;
1151     }
1152
1153     // Keep track of cycles where SMT is active
1154     if (activeThreads.size() > 1) {
1155         smtCycles++;
1156     }
1157 }
1158
1159 void
1160 InOrderCPU::activateContext(ThreadID tid, int delay)
1161 {
1162     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
1163
1164
1165     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
1166
1167     // Be sure to signal that there's some activity so the CPU doesn't
1168     // deschedule itself.
1169     activityRec.activity();
1170
1171     _status = Running;
1172 }
1173
1174 void
1175 InOrderCPU::activateNextReadyContext(int delay)
1176 {
1177     DPRINTF(InOrderCPU,"Activating next ready thread\n");
1178
1179     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
1180                      delay, ActivateNextReadyThread_Pri);
1181
1182     // Be sure to signal that there's some activity so the CPU doesn't
1183     // deschedule itself.
1184     activityRec.activity();
1185
1186     _status = Running;
1187 }
1188
1189 void
1190 InOrderCPU::haltContext(ThreadID tid)
1191 {
1192     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
1193
1194     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid]);
1195
1196     activityRec.activity();
1197 }
1198
1199 void
1200 InOrderCPU::haltThread(ThreadID tid)
1201 {
1202     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
1203     deactivateThread(tid);
1204     squashThreadInPipeline(tid);
1205     haltedThreads.push_back(tid);
1206
1207     tcBase(tid)->setStatus(ThreadContext::Halted);
1208
1209     if (threadModel == SwitchOnCacheMiss) {
1210         activateNextReadyContext();
1211     }
1212 }
1213
1214 void
1215 InOrderCPU::suspendContext(ThreadID tid)
1216 {
1217     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid]);
1218 }
1219
1220 void
1221 InOrderCPU::suspendThread(ThreadID tid)
1222 {
1223     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
1224             tid);
1225     deactivateThread(tid);
1226     suspendedThreads.push_back(tid);
1227     thread[tid]->lastSuspend = curTick();
1228
1229     tcBase(tid)->setStatus(ThreadContext::Suspended);
1230 }
1231
1232 void
1233 InOrderCPU::squashThreadInPipeline(ThreadID tid)
1234 {
1235     //Squash all instructions in each stage
1236     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
1237         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
1238     }
1239 }
1240
1241 PipelineStage*
1242 InOrderCPU::getPipeStage(int stage_num)
1243 {
1244     return pipelineStage[stage_num];
1245 }
1246
1247
1248 RegIndex
1249 InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
1250 {
1251     if (reg_idx < FP_Base_DepTag) {
1252         reg_type = IntType;
1253         return isa[tid].flattenIntIndex(reg_idx);
1254     } else if (reg_idx < Ctrl_Base_DepTag) {
1255         reg_type = FloatType;
1256         reg_idx -= FP_Base_DepTag;
1257         return isa[tid].flattenFloatIndex(reg_idx);
1258     } else {
1259         reg_type = MiscType;
1260         return reg_idx - TheISA::Ctrl_Base_DepTag;
1261     }
1262 }
1263
1264 uint64_t
1265 InOrderCPU::readIntReg(RegIndex reg_idx, ThreadID tid)
1266 {
1267     DPRINTF(IntRegs, "[tid:%i]: Reading Int. Reg %i as %x\n",
1268             tid, reg_idx, intRegs[tid][reg_idx]);
1269
1270     return intRegs[tid][reg_idx];
1271 }
1272
1273 FloatReg
1274 InOrderCPU::readFloatReg(RegIndex reg_idx, ThreadID tid)
1275 {
1276     DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1277             tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
1278
1279     return floatRegs.f[tid][reg_idx];
1280 }
1281
1282 FloatRegBits
1283 InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
1284 {
1285     DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1286             tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
1287
1288     return floatRegs.i[tid][reg_idx];
1289 }
1290
1291 void
1292 InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid)
1293 {
1294     if (reg_idx == TheISA::ZeroReg) {
1295         DPRINTF(IntRegs, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1296                 "(Int. Reg %i) to %x\n", tid, reg_idx, val);
1297         return;
1298     } else {
1299         DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
1300                 tid, reg_idx, val);
1301
1302         intRegs[tid][reg_idx] = val;
1303     }
1304 }
1305
1306
1307 void
1308 InOrderCPU::setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid)
1309 {
1310     floatRegs.f[tid][reg_idx] = val;
1311     DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
1312             "%x, %08f\n",
1313             tid, reg_idx,
1314             floatRegs.i[tid][reg_idx],
1315             floatRegs.f[tid][reg_idx]);
1316 }
1317
1318
1319 void
1320 InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid)
1321 {
1322     floatRegs.i[tid][reg_idx] = val;
1323     DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
1324             "%x, %08f\n",
1325             tid, reg_idx,
1326             floatRegs.i[tid][reg_idx],
1327             floatRegs.f[tid][reg_idx]);
1328 }
1329
1330 uint64_t
1331 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1332 {
1333     // If Default value is set, then retrieve target thread
1334     if (tid == InvalidThreadID) {
1335         tid = TheISA::getTargetThread(tcBase(tid));
1336     }
1337
1338     if (reg_idx < FP_Base_DepTag) {
1339         // Integer Register File
1340         return readIntReg(reg_idx, tid);
1341     } else if (reg_idx < Ctrl_Base_DepTag) {
1342         // Float Register File
1343         reg_idx -= FP_Base_DepTag;
1344         return readFloatRegBits(reg_idx, tid);
1345     } else {
1346         reg_idx -= Ctrl_Base_DepTag;
1347         return readMiscReg(reg_idx, tid);  // Misc. Register File
1348     }
1349 }
1350 void
1351 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1352                               ThreadID tid)
1353 {
1354     // If Default value is set, then retrieve target thread
1355     if (tid == InvalidThreadID) {
1356         tid = TheISA::getTargetThread(tcBase(tid));
1357     }
1358
1359     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1360         setIntReg(reg_idx, val, tid);
1361     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1362         reg_idx -= FP_Base_DepTag;
1363         setFloatRegBits(reg_idx, val, tid);
1364     } else {
1365         reg_idx -= Ctrl_Base_DepTag;
1366         setMiscReg(reg_idx, val, tid); // Misc. Register File
1367     }
1368 }
1369
1370 MiscReg
1371 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1372 {
1373     return isa[tid].readMiscRegNoEffect(misc_reg);
1374 }
1375
1376 MiscReg
1377 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1378 {
1379     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1380 }
1381
1382 void
1383 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1384 {
1385     isa[tid].setMiscRegNoEffect(misc_reg, val);
1386 }
1387
1388 void
1389 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1390 {
1391     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1392 }
1393
1394
1395 InOrderCPU::ListIt
1396 InOrderCPU::addInst(DynInstPtr inst)
1397 {
1398     ThreadID tid = inst->readTid();
1399
1400     instList[tid].push_back(inst);
1401
1402     return --(instList[tid].end());
1403 }
1404
1405 InOrderCPU::ListIt
1406 InOrderCPU::findInst(InstSeqNum seq_num, ThreadID tid)
1407 {
1408     ListIt it = instList[tid].begin();
1409     ListIt end = instList[tid].end();
1410
1411     while (it != end) {
1412         if ((*it)->seqNum == seq_num)
1413             return it;
1414         else if ((*it)->seqNum > seq_num)
1415             break;
1416
1417         it++;
1418     }
1419
1420     return instList[tid].end();
1421 }
1422
1423 void
1424 InOrderCPU::updateContextSwitchStats()
1425 {
1426     // Set Average Stat Here, then reset to 0
1427     instsPerCtxtSwitch = instsPerSwitch;
1428     instsPerSwitch = 0;
1429 }
1430
1431
1432 void
1433 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1434 {
1435     // Set the nextPC to be fetched if this is the last instruction
1436     // committed
1437     // ========
1438     // This contributes to the precise state of the CPU
1439     // which can be used when restoring a thread to the CPU after after any
1440     // type of context switching activity (fork, exception, etc.)
1441     TheISA::PCState comm_pc = inst->pcState();
1442     lastCommittedPC[tid] = comm_pc;
1443     TheISA::advancePC(comm_pc, inst->staticInst);
1444     pcState(comm_pc, tid);
1445
1446     //@todo: may be unnecessary with new-ISA-specific branch handling code
1447     if (inst->isControl()) {
1448         thread[tid]->lastGradIsBranch = true;
1449         thread[tid]->lastBranchPC = inst->pcState();
1450         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1451     } else {
1452         thread[tid]->lastGradIsBranch = false;
1453     }
1454
1455
1456     // Finalize Trace Data For Instruction
1457     if (inst->traceData) {
1458         //inst->traceData->setCycle(curTick());
1459         inst->traceData->setFetchSeq(inst->seqNum);
1460         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1461         inst->traceData->dump();
1462         delete inst->traceData;
1463         inst->traceData = NULL;
1464     }
1465
1466     // Increment active thread's instruction count
1467     instsPerSwitch++;
1468
1469     // Increment thread-state's instruction count
1470     thread[tid]->numInst++;
1471     thread[tid]->numOp++;
1472
1473     // Increment thread-state's instruction stats
1474     thread[tid]->numInsts++;
1475     thread[tid]->numOps++;
1476
1477     // Count committed insts per thread stats
1478     if (!inst->isMicroop() || inst->isLastMicroop()) {
1479         committedInsts[tid]++;
1480
1481         // Count total insts committed stat
1482         totalCommittedInsts++;
1483     }
1484
1485     committedOps[tid]++;
1486
1487     // Count SMT-committed insts per thread stat
1488     if (numActiveThreads() > 1) {
1489         if (!inst->isMicroop() || inst->isLastMicroop())
1490             smtCommittedInsts[tid]++;
1491     }
1492
1493     // Instruction-Mix Stats
1494     if (inst->isLoad()) {
1495         comLoads++;
1496     } else if (inst->isStore()) {
1497         comStores++;
1498     } else if (inst->isControl()) {
1499         comBranches++;
1500     } else if (inst->isNop()) {
1501         comNops++;
1502     } else if (inst->isNonSpeculative()) {
1503         comNonSpec++;
1504     } else if (inst->isInteger()) {
1505         comInts++;
1506     } else if (inst->isFloating()) {
1507         comFloats++;
1508     }
1509
1510     // Check for instruction-count-based events.
1511     comInstEventQueue[tid]->serviceEvents(thread[tid]->numOp);
1512
1513     // Finally, remove instruction from CPU
1514     removeInst(inst);
1515 }
1516
1517 // currently unused function, but substitute repetitive code w/this function
1518 // call
1519 void
1520 InOrderCPU::addToRemoveList(DynInstPtr inst)
1521 {
1522     removeInstsThisCycle = true;
1523     if (!inst->isRemoveList()) {
1524         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1525                 "[sn:%lli] to remove list\n",
1526                 inst->threadNumber, inst->pcState(), inst->seqNum);
1527         inst->setRemoveList();
1528         removeList.push(inst->getInstListIt());
1529     }  else {
1530         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1531                 "[sn:%lli], already remove list\n",
1532                 inst->threadNumber, inst->pcState(), inst->seqNum);
1533     }
1534
1535 }
1536
1537 void
1538 InOrderCPU::removeInst(DynInstPtr inst)
1539 {
1540     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1541             "[sn:%lli]\n",
1542             inst->threadNumber, inst->pcState(), inst->seqNum);
1543
1544     removeInstsThisCycle = true;
1545
1546     // Remove the instruction.
1547     if (!inst->isRemoveList()) {
1548         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1549                 "[sn:%lli] to remove list\n",
1550                 inst->threadNumber, inst->pcState(), inst->seqNum);
1551         inst->setRemoveList();
1552         removeList.push(inst->getInstListIt());
1553     } else {
1554         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1555                 "[sn:%lli], already on remove list\n",
1556                 inst->threadNumber, inst->pcState(), inst->seqNum);
1557     }
1558
1559 }
1560
1561 void
1562 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1563 {
1564     //assert(!instList[tid].empty());
1565
1566     removeInstsThisCycle = true;
1567
1568     ListIt inst_iter = instList[tid].end();
1569
1570     inst_iter--;
1571
1572     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1573             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1574             tid, seq_num, (*inst_iter)->seqNum);
1575
1576     while ((*inst_iter)->seqNum > seq_num) {
1577
1578         bool break_loop = (inst_iter == instList[tid].begin());
1579
1580         squashInstIt(inst_iter, tid);
1581
1582         inst_iter--;
1583
1584         if (break_loop)
1585             break;
1586     }
1587 }
1588
1589
1590 inline void
1591 InOrderCPU::squashInstIt(const ListIt inst_it, ThreadID tid)
1592 {
1593     DynInstPtr inst = (*inst_it);
1594     if (inst->threadNumber == tid) {
1595         DPRINTF(InOrderCPU, "Squashing instruction, "
1596                 "[tid:%i] [sn:%lli] PC %s\n",
1597                 inst->threadNumber,
1598                 inst->seqNum,
1599                 inst->pcState());
1600
1601         inst->setSquashed();
1602         archRegDepMap[tid].remove(inst);
1603
1604         if (!inst->isRemoveList()) {
1605             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1606                     "[sn:%lli] to remove list\n",
1607                     inst->threadNumber, inst->pcState(),
1608                     inst->seqNum);
1609             inst->setRemoveList();
1610             removeList.push(inst_it);
1611         } else {
1612             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1613                     " PC %s [sn:%lli], already on remove list\n",
1614                     inst->threadNumber, inst->pcState(),
1615                     inst->seqNum);
1616         }
1617
1618     }
1619
1620 }
1621
1622
1623 void
1624 InOrderCPU::cleanUpRemovedInsts()
1625 {
1626     while (!removeList.empty()) {
1627         DPRINTF(InOrderCPU, "Removing instruction, "
1628                 "[tid:%i] [sn:%lli] PC %s\n",
1629                 (*removeList.front())->threadNumber,
1630                 (*removeList.front())->seqNum,
1631                (*removeList.front())->pcState());
1632
1633         DynInstPtr inst = *removeList.front();
1634         ThreadID tid = inst->threadNumber;
1635
1636         // Remove From Register Dependency Map, If Necessary
1637         // archRegDepMap[tid].remove(inst);
1638
1639         // Clear if Non-Speculative
1640         if (inst->staticInst &&
1641             inst->seqNum == nonSpecSeqNum[tid] &&
1642             nonSpecInstActive[tid] == true) {
1643             nonSpecInstActive[tid] = false;
1644         }
1645
1646         inst->onInstList = false;
1647
1648         instList[tid].erase(removeList.front());
1649
1650         removeList.pop();
1651     }
1652
1653     removeInstsThisCycle = false;
1654 }
1655
1656 void
1657 InOrderCPU::cleanUpRemovedEvents()
1658 {
1659     while (!cpuEventRemoveList.empty()) {
1660         Event *cpu_event = cpuEventRemoveList.front();
1661         cpuEventRemoveList.pop();
1662         delete cpu_event;
1663     }
1664 }
1665
1666
1667 void
1668 InOrderCPU::dumpInsts()
1669 {
1670     int num = 0;
1671
1672     ListIt inst_list_it = instList[0].begin();
1673
1674     cprintf("Dumping Instruction List\n");
1675
1676     while (inst_list_it != instList[0].end()) {
1677         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1678                 "Squashed:%i\n\n",
1679                 num, (*inst_list_it)->pcState(),
1680                 (*inst_list_it)->threadNumber,
1681                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1682                 (*inst_list_it)->isSquashed());
1683         inst_list_it++;
1684         ++num;
1685     }
1686 }
1687
1688 void
1689 InOrderCPU::wakeCPU()
1690 {
1691     if (/*activityRec.active() || */tickEvent.scheduled()) {
1692         DPRINTF(Activity, "CPU already running.\n");
1693         return;
1694     }
1695
1696     DPRINTF(Activity, "Waking up CPU\n");
1697
1698     Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
1699
1700     idleCycles += extra_cycles;
1701     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1702         pipelineStage[stage_num]->idleCycles += extra_cycles;
1703     }
1704
1705     numCycles += extra_cycles;
1706
1707     schedule(&tickEvent, nextCycle(curTick()));
1708 }
1709
1710 // Lots of copied full system code...place into BaseCPU class?
1711 void
1712 InOrderCPU::wakeup()
1713 {
1714     if (thread[0]->status() != ThreadContext::Suspended)
1715         return;
1716
1717     wakeCPU();
1718
1719     DPRINTF(Quiesce, "Suspended Processor woken\n");
1720     threadContexts[0]->activate();
1721 }
1722
1723 void
1724 InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
1725 {
1726     // Syscall must be non-speculative, so squash from last stage
1727     unsigned squash_stage = NumStages - 1;
1728     inst->setSquashInfo(squash_stage);
1729
1730     // Squash In Pipeline Stage
1731     pipelineStage[squash_stage]->setupSquash(inst, tid);
1732
1733     // Schedule Squash Through-out Resource Pool
1734     resPool->scheduleEvent(
1735         (InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
1736     scheduleCpuEvent(Syscall, fault, tid, inst, delay, Syscall_Pri);
1737 }
1738
1739 void
1740 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1741 {
1742     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1743
1744     DPRINTF(Activity,"Activity: syscall() called.\n");
1745
1746     // Temporarily increase this by one to account for the syscall
1747     // instruction.
1748     ++(this->thread[tid]->funcExeInst);
1749
1750     // Execute the actual syscall.
1751     this->thread[tid]->syscall(callnum);
1752
1753     // Decrease funcExeInst by one as the normal commit will handle
1754     // incrementing it.
1755     --(this->thread[tid]->funcExeInst);
1756
1757     // Clear Non-Speculative Block Variable
1758     nonSpecInstActive[tid] = false;
1759 }
1760
1761 TheISA::TLB*
1762 InOrderCPU::getITBPtr()
1763 {
1764     CacheUnit *itb_res = resPool->getInstUnit();
1765     return itb_res->tlb();
1766 }
1767
1768
1769 TheISA::TLB*
1770 InOrderCPU::getDTBPtr()
1771 {
1772     return resPool->getDataUnit()->tlb();
1773 }
1774
1775 Decoder *
1776 InOrderCPU::getDecoderPtr()
1777 {
1778     return &resPool->getInstUnit()->decoder;
1779 }
1780
1781 Fault
1782 InOrderCPU::read(DynInstPtr inst, Addr addr,
1783                  uint8_t *data, unsigned size, unsigned flags)
1784 {
1785     return resPool->getDataUnit()->read(inst, addr, data, size, flags);
1786 }
1787
1788 Fault
1789 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1790                   Addr addr, unsigned flags, uint64_t *write_res)
1791 {
1792     return resPool->getDataUnit()->write(inst, data, size, addr, flags,
1793                                          write_res);
1794 }