src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <algorithm>
  33
  34 #include "arch/utility.hh"
  35 #include "config/full_system.hh"
  36 #include "config/the_isa.hh"
  37 #include "cpu/activity.hh"
  38 #include "cpu/base.hh"
  39 #include "cpu/exetrace.hh"
  40 #include "cpu/inorder/cpu.hh"
  41 #include "cpu/inorder/first_stage.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource_pool.hh"
  45 #include "cpu/inorder/resources/resource_list.hh"
  46 #include "cpu/inorder/thread_context.hh"
  47 #include "cpu/inorder/thread_state.hh"
  48 #include "cpu/simple_thread.hh"
  49 #include "cpu/thread_context.hh"
  50 #include "mem/translating_port.hh"
  51 #include "params/InOrderCPU.hh"
  52 #include "sim/process.hh"
  53 #include "sim/stat_control.hh"
  54
  55 #if FULL_SYSTEM
  56 #include "cpu/quiesce_event.hh"
  57 #include "sim/system.hh"
  58 #endif
  59
  60 #if THE_ISA == ALPHA_ISA
  61 #include "arch/alpha/osfpal.hh"
  62 #endif
  63
  64 using namespace std;
  65 using namespace TheISA;
  66 using namespace ThePipeline;
  67
  68 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
  69   : Event(CPU_Tick_Pri), cpu(c)
  70 { }
  71
  72
  73 void
  74 InOrderCPU::TickEvent::process()
  75 {
  76     cpu->tick();
  77 }
  78
  79
  80 const char *
  81 InOrderCPU::TickEvent::description()
  82 {
  83     return "InOrderCPU tick event";
  84 }
  85
  86 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
  87                                Fault fault, ThreadID _tid, DynInstPtr inst,
  88                                unsigned event_pri_offset)
  89     : Event(Event::Priority((unsigned int)CPU_Tick_Pri + event_pri_offset)),
  90       cpu(_cpu)
  91 {
  92     setEvent(e_type, fault, _tid, inst);
  93 }
  94
  95
  96 std::string InOrderCPU::eventNames[NumCPUEvents] =
  97 {
  98     "ActivateThread",
  99     "ActivateNextReadyThread",
 100     "DeactivateThread",
 101     "HaltThread",
 102     "SuspendThread",
 103     "Trap",
 104     "InstGraduated",
 105     "SquashFromMemStall",
 106     "UpdatePCs"
 107 };
 108
 109 void
 110 InOrderCPU::CPUEvent::process()
 111 {
 112     switch (cpuEventType)
 113     {
 114       case ActivateThread:
 115         cpu->activateThread(tid);
 116         break;
 117
 118       case ActivateNextReadyThread:
 119         cpu->activateNextReadyThread();
 120         break;
 121
 122       case DeactivateThread:
 123         cpu->deactivateThread(tid);
 124         break;
 125
 126       case HaltThread:
 127         cpu->haltThread(tid);
 128         break;
 129
 130       case SuspendThread:
 131         cpu->suspendThread(tid);
 132         break;
 133
 134       case SquashFromMemStall:
 135         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 136         break;
 137
 138       case Trap:
 139         cpu->trapCPU(fault, tid, inst);
 140         break;
 141
 142       default:
 143         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 144     }
 145
 146     cpu->cpuEventRemoveList.push(this);
 147 }
 148
 149
 150
 151 const char *
 152 InOrderCPU::CPUEvent::description()
 153 {
 154     return "InOrderCPU event";
 155 }
 156
 157 void
 158 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 159 {
 160     assert(!scheduled() || squashed());
 161     cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
 162 }
 163
 164 void
 165 InOrderCPU::CPUEvent::unscheduleEvent()
 166 {
 167     if (scheduled())
 168         squash();
 169 }
 170
 171 InOrderCPU::InOrderCPU(Params *params)
 172     : BaseCPU(params),
 173       cpu_id(params->cpu_id),
 174       coreType("default"),
 175       _status(Idle),
 176       tickEvent(this),
 177       stageWidth(params->stageWidth),
 178       timeBuffer(2 , 2),
 179       removeInstsThisCycle(false),
 180       activityRec(params->name, NumStages, 10, params->activity),
 181 #if FULL_SYSTEM
 182       system(params->system),
 183       physmem(system->physmem),
 184 #endif // FULL_SYSTEM
 185 #ifdef DEBUG
 186       cpuEventNum(0),
 187       resReqCount(0),
 188 #endif // DEBUG
 189       switchCount(0),
 190       deferRegistration(false/*params->deferRegistration*/),
 191       stageTracing(params->stageTracing),
 192       instsPerSwitch(0)
 193 {
 194     ThreadID active_threads;
 195     cpu_params = params;
 196
 197     resPool = new ResourcePool(this, params);
 198
 199     // Resize for Multithreading CPUs
 200     thread.resize(numThreads);
 201
 202 #if FULL_SYSTEM
 203     active_threads = 1;
 204 #else
 205     active_threads = params->workload.size();
 206
 207     if (active_threads > MaxThreads) {
 208         panic("Workload Size too large. Increase the 'MaxThreads'"
 209               "in your InOrder implementation or "
 210               "edit your workload size.");
 211     }
 212
 213
 214     if (active_threads > 1) {
 215         threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 216
 217         if (threadModel == SMT) {
 218             DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 219         } else if (threadModel == SwitchOnCacheMiss) {
 220             DPRINTF(InOrderCPU, "Setting Thread Model to "
 221                     "Switch On Cache Miss\n");
 222         }
 223
 224     } else {
 225         threadModel = Single;
 226     }
 227
 228
 229
 230 #endif
 231
 232     // Bind the fetch & data ports from the resource pool.
 233     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
 234     if (fetchPortIdx == 0) {
 235         fatal("Unable to find port to fetch instructions from.\n");
 236     }
 237
 238     dataPortIdx = resPool->getPortIdx(params->dataMemPort);
 239     if (dataPortIdx == 0) {
 240         fatal("Unable to find port for data.\n");
 241     }
 242
 243     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 244 #if FULL_SYSTEM
 245         // SMT is not supported in FS mode yet.
 246         assert(numThreads == 1);
 247         thread[tid] = new Thread(this, 0);
 248 #else
 249         if (tid < (ThreadID)params->workload.size()) {
 250             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 251                     tid, params->workload[tid]->prog_fname);
 252             thread[tid] =
 253                 new Thread(this, tid, params->workload[tid]);
 254         } else {
 255             //Allocate Empty thread so M5 can use later
 256             //when scheduling threads to CPU
 257             Process* dummy_proc = params->workload[0];
 258             thread[tid] = new Thread(this, tid, dummy_proc);
 259         }
 260
 261         // Eventually set this with parameters...
 262         asid[tid] = tid;
 263 #endif
 264
 265         // Setup the TC that will serve as the interface to the threads/CPU.
 266         InOrderThreadContext *tc = new InOrderThreadContext;
 267         tc->cpu = this;
 268         tc->thread = thread[tid];
 269
 270         // Give the thread the TC.
 271         thread[tid]->tc = tc;
 272         thread[tid]->setFuncExeInst(0);
 273         globalSeqNum[tid] = 1;
 274
 275         // Add the TC to the CPU's list of TC's.
 276         this->threadContexts.push_back(tc);
 277     }
 278
 279     // Initialize TimeBuffer Stage Queues
 280     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 281         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 282         stageQueue[stNum]->id(stNum);
 283     }
 284
 285
 286     // Set Up Pipeline Stages
 287     for (int stNum=0; stNum < NumStages; stNum++) {
 288         if (stNum == 0)
 289             pipelineStage[stNum] = new FirstStage(params, stNum);
 290         else
 291             pipelineStage[stNum] = new PipelineStage(params, stNum);
 292
 293         pipelineStage[stNum]->setCPU(this);
 294         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 295         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 296
 297         // Take Care of 1st/Nth stages
 298         if (stNum > 0)
 299             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 300         if (stNum < NumStages - 1)
 301             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 302     }
 303
 304     // Initialize thread specific variables
 305     for (ThreadID tid = 0; tid < numThreads; tid++) {
 306         archRegDepMap[tid].setCPU(this);
 307
 308         nonSpecInstActive[tid] = false;
 309         nonSpecSeqNum[tid] = 0;
 310
 311         squashSeqNum[tid] = MaxAddr;
 312         lastSquashCycle[tid] = 0;
 313
 314         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 315         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 316         isa[tid].clear();
 317
 318         isa[tid].expandForMultithreading(numThreads, 1/*numVirtProcs*/);
 319
 320         // Define dummy instructions and resource requests to be used.
 321         dummyInst[tid] = new InOrderDynInst(this,
 322                                             thread[tid],
 323                                             0,
 324                                             tid,
 325                                             asid[tid]);
 326
 327         dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
 328     }
 329
 330     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 331     dummyReqInst->setSquashed();
 332     dummyReqInst->resetInstCount();
 333
 334     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 335     dummyBufferInst->setSquashed();
 336     dummyBufferInst->resetInstCount();
 337
 338     endOfSkedIt = skedCache.end();
 339     frontEndSked = createFrontEndSked();
 340
 341     lastRunningCycle = curTick();
 342
 343     // Reset CPU to reset state.
 344 #if FULL_SYSTEM
 345     Fault resetFault = new ResetFault();
 346     resetFault->invoke(tcBase());
 347 #else
 348     reset();
 349 #endif
 350
 351
 352     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 353     scheduleTickEvent(0);
 354 }
 355
 356 InOrderCPU::~InOrderCPU()
 357 {
 358     delete resPool;
 359
 360     std::map<SkedID, ThePipeline::RSkedPtr>::iterator sked_it =
 361         skedCache.begin();
 362     std::map<SkedID, ThePipeline::RSkedPtr>::iterator sked_end =
 363         skedCache.end();
 364
 365     while (sked_it != sked_end) {
 366         delete (*sked_it).second;
 367         sked_it++;
 368     }
 369     skedCache.clear();
 370 }
 371
 372 std::map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
 373
 374 RSkedPtr
 375 InOrderCPU::createFrontEndSked()
 376 {
 377     RSkedPtr res_sked = new ResourceSked();
 378     int stage_num = 0;
 379     StageScheduler F(res_sked, stage_num++);
 380     StageScheduler D(res_sked, stage_num++);
 381
 382     // FETCH
 383     F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
 384     F.needs(ICache, FetchUnit::InitiateFetch);
 385
 386     // DECODE
 387     D.needs(ICache, FetchUnit::CompleteFetch);
 388     D.needs(Decode, DecodeUnit::DecodeInst);
 389     D.needs(BPred, BranchPredictor::PredictBranch);
 390     D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
 391
 392
 393     DPRINTF(SkedCache, "Resource Sked created for instruction \"front_end\"\n");
 394
 395     return res_sked;
 396 }
 397
 398 RSkedPtr
 399 InOrderCPU::createBackEndSked(DynInstPtr inst)
 400 {
 401     RSkedPtr res_sked = lookupSked(inst);
 402     if (res_sked != NULL) {
 403         DPRINTF(SkedCache, "Found %s in sked cache.\n",
 404                 inst->instName());
 405         return res_sked;
 406     } else {
 407         res_sked = new ResourceSked();
 408     }
 409
 410     int stage_num = ThePipeline::BackEndStartStage;
 411     StageScheduler X(res_sked, stage_num++);
 412     StageScheduler M(res_sked, stage_num++);
 413     StageScheduler W(res_sked, stage_num++);
 414
 415     if (!inst->staticInst) {
 416         warn_once("Static Instruction Object Not Set. Can't Create"
 417                   " Back End Schedule");
 418         return NULL;
 419     }
 420
 421     // EXECUTE
 422     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 423         if (!idx || !inst->isStore()) {
 424             X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
 425         }
 426     }
 427
 428     if ( inst->isNonSpeculative() ) {
 429         // skip execution of non speculative insts until later
 430     } else if ( inst->isMemRef() ) {
 431         if ( inst->isLoad() ) {
 432             X.needs(AGEN, AGENUnit::GenerateAddr);
 433         }
 434     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 435         X.needs(MDU, MultDivUnit::StartMultDiv);
 436     } else {
 437         X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 438     }
 439
 440     if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 441         X.needs(MDU, MultDivUnit::EndMultDiv);
 442     }
 443
 444     // MEMORY
 445     if ( inst->isLoad() ) {
 446         M.needs(DCache, CacheUnit::InitiateReadData);
 447     } else if ( inst->isStore() ) {
 448         if ( inst->numSrcRegs() >= 2 ) {
 449             M.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 450         }
 451         M.needs(AGEN, AGENUnit::GenerateAddr);
 452         M.needs(DCache, CacheUnit::InitiateWriteData);
 453     }
 454
 455
 456     // WRITEBACK
 457     if ( inst->isLoad() ) {
 458         W.needs(DCache, CacheUnit::CompleteReadData);
 459     } else if ( inst->isStore() ) {
 460         W.needs(DCache, CacheUnit::CompleteWriteData);
 461     }
 462
 463     if ( inst->isNonSpeculative() ) {
 464         if ( inst->isMemRef() ) fatal("Non-Speculative Memory Instruction");
 465         W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 466     }
 467
 468     W.needs(Grad, GraduationUnit::GraduateInst);
 469
 470     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 471         W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
 472     }
 473
 474     // Insert Back Schedule into our cache of
 475     // resource schedules
 476     addToSkedCache(inst, res_sked);
 477
 478     DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
 479             inst->instName(), inst->getMachInst());
 480     res_sked->print();
 481
 482     return res_sked;
 483 }
 484
 485 void
 486 InOrderCPU::regStats()
 487 {
 488     /* Register the Resource Pool's stats here.*/
 489     resPool->regStats();
 490
 491     /* Register for each Pipeline Stage */
 492     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 493         pipelineStage[stage_num]->regStats();
 494     }
 495
 496     /* Register any of the InOrderCPU's stats here.*/
 497     instsPerCtxtSwitch
 498         .name(name() + ".instsPerContextSwitch")
 499         .desc("Instructions Committed Per Context Switch")
 500         .prereq(instsPerCtxtSwitch);
 501
 502     numCtxtSwitches
 503         .name(name() + ".contextSwitches")
 504         .desc("Number of context switches");
 505
 506     comLoads
 507         .name(name() + ".comLoads")
 508         .desc("Number of Load instructions committed");
 509
 510     comStores
 511         .name(name() + ".comStores")
 512         .desc("Number of Store instructions committed");
 513
 514     comBranches
 515         .name(name() + ".comBranches")
 516         .desc("Number of Branches instructions committed");
 517
 518     comNops
 519         .name(name() + ".comNops")
 520         .desc("Number of Nop instructions committed");
 521
 522     comNonSpec
 523         .name(name() + ".comNonSpec")
 524         .desc("Number of Non-Speculative instructions committed");
 525
 526     comInts
 527         .name(name() + ".comInts")
 528         .desc("Number of Integer instructions committed");
 529
 530     comFloats
 531         .name(name() + ".comFloats")
 532         .desc("Number of Floating Point instructions committed");
 533
 534     timesIdled
 535         .name(name() + ".timesIdled")
 536         .desc("Number of times that the entire CPU went into an idle state and"
 537               " unscheduled itself")
 538         .prereq(timesIdled);
 539
 540     idleCycles
 541         .name(name() + ".idleCycles")
 542         .desc("Number of cycles cpu's stages were not processed");
 543
 544     runCycles
 545         .name(name() + ".runCycles")
 546         .desc("Number of cycles cpu stages are processed.");
 547
 548     activity
 549         .name(name() + ".activity")
 550         .desc("Percentage of cycles cpu is active")
 551         .precision(6);
 552     activity = (runCycles / numCycles) * 100;
 553
 554     threadCycles
 555         .init(numThreads)
 556         .name(name() + ".threadCycles")
 557         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 558
 559     smtCycles
 560         .name(name() + ".smtCycles")
 561         .desc("Total number of cycles that the CPU was in SMT-mode");
 562
 563     committedInsts
 564         .init(numThreads)
 565         .name(name() + ".committedInsts")
 566         .desc("Number of Instructions Simulated (Per-Thread)");
 567
 568     smtCommittedInsts
 569         .init(numThreads)
 570         .name(name() + ".smtCommittedInsts")
 571         .desc("Number of SMT Instructions Simulated (Per-Thread)");
 572
 573     totalCommittedInsts
 574         .name(name() + ".committedInsts_total")
 575         .desc("Number of Instructions Simulated (Total)");
 576
 577     cpi
 578         .name(name() + ".cpi")
 579         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 580         .precision(6);
 581     cpi = numCycles / committedInsts;
 582
 583     smtCpi
 584         .name(name() + ".smt_cpi")
 585         .desc("CPI: Total SMT-CPI")
 586         .precision(6);
 587     smtCpi = smtCycles / smtCommittedInsts;
 588
 589     totalCpi
 590         .name(name() + ".cpi_total")
 591         .desc("CPI: Total CPI of All Threads")
 592         .precision(6);
 593     totalCpi = numCycles / totalCommittedInsts;
 594
 595     ipc
 596         .name(name() + ".ipc")
 597         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 598         .precision(6);
 599     ipc =  committedInsts / numCycles;
 600
 601     smtIpc
 602         .name(name() + ".smt_ipc")
 603         .desc("IPC: Total SMT-IPC")
 604         .precision(6);
 605     smtIpc = smtCommittedInsts / smtCycles;
 606
 607     totalIpc
 608         .name(name() + ".ipc_total")
 609         .desc("IPC: Total IPC of All Threads")
 610         .precision(6);
 611         totalIpc =  totalCommittedInsts / numCycles;
 612
 613     BaseCPU::regStats();
 614 }
 615
 616
 617 void
 618 InOrderCPU::tick()
 619 {
 620     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 621
 622     ++numCycles;
 623
 624     bool pipes_idle = true;
 625
 626     //Tick each of the stages
 627     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 628         pipelineStage[stNum]->tick();
 629
 630         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 631     }
 632
 633     if (pipes_idle)
 634         idleCycles++;
 635     else
 636         runCycles++;
 637
 638     // Now advance the time buffers one tick
 639     timeBuffer.advance();
 640     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 641         stageQueue[sqNum]->advance();
 642     }
 643     activityRec.advance();
 644
 645     // Any squashed events, or insts then remove them now
 646     cleanUpRemovedEvents();
 647     cleanUpRemovedInsts();
 648
 649     // Re-schedule CPU for this cycle
 650     if (!tickEvent.scheduled()) {
 651         if (_status == SwitchedOut) {
 652             // increment stat
 653             lastRunningCycle = curTick();
 654         } else if (!activityRec.active()) {
 655             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 656             lastRunningCycle = curTick();
 657             timesIdled++;
 658         } else {
 659             //Tick next_tick = curTick() + cycles(1);
 660             //tickEvent.schedule(next_tick);
 661             schedule(&tickEvent, nextCycle(curTick() + 1));
 662             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 663                     nextCycle(curTick() + 1));
 664         }
 665     }
 666
 667     tickThreadStats();
 668     updateThreadPriority();
 669 }
 670
 671
 672 void
 673 InOrderCPU::init()
 674 {
 675     if (!deferRegistration) {
 676         registerThreadContexts();
 677     }
 678
 679     // Set inSyscall so that the CPU doesn't squash when initially
 680     // setting up registers.
 681     for (ThreadID tid = 0; tid < numThreads; ++tid)
 682         thread[tid]->inSyscall = true;
 683
 684 #if FULL_SYSTEM
 685     for (ThreadID tid = 0; tid < numThreads; tid++) {
 686         ThreadContext *src_tc = threadContexts[tid];
 687         TheISA::initCPU(src_tc, src_tc->contextId());
 688     }
 689 #endif
 690
 691     // Clear inSyscall.
 692     for (ThreadID tid = 0; tid < numThreads; ++tid)
 693         thread[tid]->inSyscall = false;
 694
 695     // Call Initializiation Routine for Resource Pool
 696     resPool->init();
 697 }
 698
 699 void
 700 InOrderCPU::reset()
 701 {
 702     for (int i = 0; i < numThreads; i++) {
 703         isa[i].reset(coreType, numThreads,
 704                      1/*numVirtProcs*/, dynamic_cast<BaseCPU*>(this));
 705     }
 706 }
 707
 708 Port*
 709 InOrderCPU::getPort(const std::string &if_name, int idx)
 710 {
 711     return resPool->getPort(if_name, idx);
 712 }
 713
 714 #if FULL_SYSTEM
 715 Fault
 716 InOrderCPU::hwrei(ThreadID tid)
 717 {
 718     panic("hwrei: Unimplemented");
 719
 720     return NoFault;
 721 }
 722
 723
 724 bool
 725 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 726 {
 727     panic("simPalCheck: Unimplemented");
 728
 729     return true;
 730 }
 731
 732
 733 Fault
 734 InOrderCPU::getInterrupts()
 735 {
 736     // Check if there are any outstanding interrupts
 737     return interrupts->getInterrupt(threadContexts[0]);
 738 }
 739
 740
 741 void
 742 InOrderCPU::processInterrupts(Fault interrupt)
 743 {
 744     // Check for interrupts here.  For now can copy the code that
 745     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 746     // is the one that handles the interrupts.
 747     // @todo: Possibly consolidate the interrupt checking code.
 748     // @todo: Allow other threads to handle interrupts.
 749
 750     assert(interrupt != NoFault);
 751     interrupts->updateIntrInfo(threadContexts[0]);
 752
 753     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 754
 755     // Note: Context ID ok here? Impl. of FS mode needs to revisit this
 756     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 757 }
 758
 759
 760 void
 761 InOrderCPU::updateMemPorts()
 762 {
 763     // Update all ThreadContext's memory ports (Functional/Virtual
 764     // Ports)
 765     ThreadID size = thread.size();
 766     for (ThreadID i = 0; i < size; ++i)
 767         thread[i]->connectMemPorts(thread[i]->getTC());
 768 }
 769 #endif
 770
 771 void
 772 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 773 {
 774     //@ Squash Pipeline during TRAP
 775     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 776 }
 777
 778 void
 779 InOrderCPU::trapCPU(Fault fault, ThreadID tid, DynInstPtr inst)
 780 {
 781     fault->invoke(tcBase(tid), inst->staticInst);
 782 }
 783
 784 void
 785 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 786 {
 787     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 788 }
 789
 790
 791 void
 792 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 793                                 ThreadID tid)
 794 {
 795     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 796
 797     // Squash all instructions in each stage including
 798     // instruction that caused the squash (seq_num - 1)
 799     // NOTE: The stage bandwidth needs to be cleared so thats why
 800     //       the stalling instruction is squashed as well. The stalled
 801     //       instruction is previously placed in another intermediate buffer
 802     //       while it's stall is being handled.
 803     InstSeqNum squash_seq_num = seq_num - 1;
 804
 805     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 806         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 807     }
 808 }
 809
 810 void
 811 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 812                              ThreadID tid, DynInstPtr inst,
 813                              unsigned delay, unsigned event_pri_offset)
 814 {
 815     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 816                                        event_pri_offset);
 817
 818     Tick sked_tick = nextCycle(curTick() + ticks(delay));
 819     if (delay >= 0) {
 820         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 821                 eventNames[c_event], curTick() + delay, tid);
 822         schedule(cpu_event, sked_tick);
 823     } else {
 824         cpu_event->process();
 825         cpuEventRemoveList.push(cpu_event);
 826     }
 827
 828     // Broadcast event to the Resource Pool
 829     // Need to reset tid just in case this is a dummy instruction
 830     inst->setTid(tid);
 831     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 832 }
 833
 834 bool
 835 InOrderCPU::isThreadActive(ThreadID tid)
 836 {
 837   list<ThreadID>::iterator isActive =
 838       std::find(activeThreads.begin(), activeThreads.end(), tid);
 839
 840     return (isActive != activeThreads.end());
 841 }
 842
 843 bool
 844 InOrderCPU::isThreadReady(ThreadID tid)
 845 {
 846   list<ThreadID>::iterator isReady =
 847       std::find(readyThreads.begin(), readyThreads.end(), tid);
 848
 849     return (isReady != readyThreads.end());
 850 }
 851
 852 bool
 853 InOrderCPU::isThreadSuspended(ThreadID tid)
 854 {
 855   list<ThreadID>::iterator isSuspended =
 856       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
 857
 858     return (isSuspended != suspendedThreads.end());
 859 }
 860
 861 void
 862 InOrderCPU::activateNextReadyThread()
 863 {
 864     if (readyThreads.size() >= 1) {
 865         ThreadID ready_tid = readyThreads.front();
 866
 867         // Activate in Pipeline
 868         activateThread(ready_tid);
 869
 870         // Activate in Resource Pool
 871         resPool->activateAll(ready_tid);
 872
 873         list<ThreadID>::iterator ready_it =
 874             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
 875         readyThreads.erase(ready_it);
 876     } else {
 877         DPRINTF(InOrderCPU,
 878                 "Attempting to activate new thread, but No Ready Threads to"
 879                 "activate.\n");
 880         DPRINTF(InOrderCPU,
 881                 "Unable to switch to next active thread.\n");
 882     }
 883 }
 884
 885 void
 886 InOrderCPU::activateThread(ThreadID tid)
 887 {
 888     if (isThreadSuspended(tid)) {
 889         DPRINTF(InOrderCPU,
 890                 "Removing [tid:%i] from suspended threads list.\n", tid);
 891
 892         list<ThreadID>::iterator susp_it =
 893             std::find(suspendedThreads.begin(), suspendedThreads.end(),
 894                       tid);
 895         suspendedThreads.erase(susp_it);
 896     }
 897
 898     if (threadModel == SwitchOnCacheMiss &&
 899         numActiveThreads() == 1) {
 900         DPRINTF(InOrderCPU,
 901                 "Ignoring activation of [tid:%i], since [tid:%i] is "
 902                 "already running.\n", tid, activeThreadId());
 903
 904         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
 905                 tid);
 906
 907         readyThreads.push_back(tid);
 908
 909     } else if (!isThreadActive(tid)) {
 910         DPRINTF(InOrderCPU,
 911                 "Adding [tid:%i] to active threads list.\n", tid);
 912         activeThreads.push_back(tid);
 913
 914         activateThreadInPipeline(tid);
 915
 916         thread[tid]->lastActivate = curTick();
 917
 918         tcBase(tid)->setStatus(ThreadContext::Active);
 919
 920         wakeCPU();
 921
 922         numCtxtSwitches++;
 923     }
 924 }
 925
 926 void
 927 InOrderCPU::activateThreadInPipeline(ThreadID tid)
 928 {
 929     for (int stNum=0; stNum < NumStages; stNum++) {
 930         pipelineStage[stNum]->activateThread(tid);
 931     }
 932 }
 933
 934 void
 935 InOrderCPU::deactivateContext(ThreadID tid, int delay)
 936 {
 937     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
 938
 939     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
 940
 941     // Be sure to signal that there's some activity so the CPU doesn't
 942     // deschedule itself.
 943     activityRec.activity();
 944
 945     _status = Running;
 946 }
 947
 948 void
 949 InOrderCPU::deactivateThread(ThreadID tid)
 950 {
 951     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
 952
 953     if (isThreadActive(tid)) {
 954         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
 955                 tid);
 956         list<ThreadID>::iterator thread_it =
 957             std::find(activeThreads.begin(), activeThreads.end(), tid);
 958
 959         removePipelineStalls(*thread_it);
 960
 961         activeThreads.erase(thread_it);
 962
 963         // Ideally, this should be triggered from the
 964         // suspendContext/Thread functions
 965         tcBase(tid)->setStatus(ThreadContext::Suspended);
 966     }
 967
 968     assert(!isThreadActive(tid));
 969 }
 970
 971 void
 972 InOrderCPU::removePipelineStalls(ThreadID tid)
 973 {
 974     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
 975             tid);
 976
 977     for (int stNum = 0; stNum < NumStages ; stNum++) {
 978         pipelineStage[stNum]->removeStalls(tid);
 979     }
 980
 981 }
 982
 983 void
 984 InOrderCPU::updateThreadPriority()
 985 {
 986     if (activeThreads.size() > 1)
 987     {
 988         //DEFAULT TO ROUND ROBIN SCHEME
 989         //e.g. Move highest priority to end of thread list
 990         list<ThreadID>::iterator list_begin = activeThreads.begin();
 991         list<ThreadID>::iterator list_end   = activeThreads.end();
 992
 993         unsigned high_thread = *list_begin;
 994
 995         activeThreads.erase(list_begin);
 996
 997         activeThreads.push_back(high_thread);
 998     }
 999 }
1000
1001 inline void
1002 InOrderCPU::tickThreadStats()
1003 {
1004     /** Keep track of cycles that each thread is active */
1005     list<ThreadID>::iterator thread_it = activeThreads.begin();
1006     while (thread_it != activeThreads.end()) {
1007         threadCycles[*thread_it]++;
1008         thread_it++;
1009     }
1010
1011     // Keep track of cycles where SMT is active
1012     if (activeThreads.size() > 1) {
1013         smtCycles++;
1014     }
1015 }
1016
1017 void
1018 InOrderCPU::activateContext(ThreadID tid, int delay)
1019 {
1020     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
1021
1022
1023     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
1024
1025     // Be sure to signal that there's some activity so the CPU doesn't
1026     // deschedule itself.
1027     activityRec.activity();
1028
1029     _status = Running;
1030 }
1031
1032 void
1033 InOrderCPU::activateNextReadyContext(int delay)
1034 {
1035     DPRINTF(InOrderCPU,"Activating next ready thread\n");
1036
1037     // NOTE: Add 5 to the event priority so that we always activate
1038     // threads after we've finished deactivating, squashing,etc.
1039     // other threads
1040     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
1041                      delay, 5);
1042
1043     // Be sure to signal that there's some activity so the CPU doesn't
1044     // deschedule itself.
1045     activityRec.activity();
1046
1047     _status = Running;
1048 }
1049
1050 void
1051 InOrderCPU::haltContext(ThreadID tid, int delay)
1052 {
1053     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
1054
1055     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
1056
1057     activityRec.activity();
1058 }
1059
1060 void
1061 InOrderCPU::haltThread(ThreadID tid)
1062 {
1063     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
1064     deactivateThread(tid);
1065     squashThreadInPipeline(tid);
1066     haltedThreads.push_back(tid);
1067
1068     tcBase(tid)->setStatus(ThreadContext::Halted);
1069
1070     if (threadModel == SwitchOnCacheMiss) {
1071         activateNextReadyContext();
1072     }
1073 }
1074
1075 void
1076 InOrderCPU::suspendContext(ThreadID tid, int delay)
1077 {
1078     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
1079 }
1080
1081 void
1082 InOrderCPU::suspendThread(ThreadID tid)
1083 {
1084     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
1085             tid);
1086     deactivateThread(tid);
1087     suspendedThreads.push_back(tid);
1088     thread[tid]->lastSuspend = curTick();
1089
1090     tcBase(tid)->setStatus(ThreadContext::Suspended);
1091 }
1092
1093 void
1094 InOrderCPU::squashThreadInPipeline(ThreadID tid)
1095 {
1096     //Squash all instructions in each stage
1097     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
1098         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
1099     }
1100 }
1101
1102 PipelineStage*
1103 InOrderCPU::getPipeStage(int stage_num)
1104 {
1105     return pipelineStage[stage_num];
1106 }
1107
1108 uint64_t
1109 InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
1110 {
1111     return intRegs[tid][reg_idx];
1112 }
1113
1114 FloatReg
1115 InOrderCPU::readFloatReg(int reg_idx, ThreadID tid)
1116 {
1117     return floatRegs.f[tid][reg_idx];
1118 }
1119
1120 FloatRegBits
1121 InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
1122 {;
1123     return floatRegs.i[tid][reg_idx];
1124 }
1125
1126 void
1127 InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
1128 {
1129     intRegs[tid][reg_idx] = val;
1130 }
1131
1132
1133 void
1134 InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid)
1135 {
1136     floatRegs.f[tid][reg_idx] = val;
1137 }
1138
1139
1140 void
1141 InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid)
1142 {
1143     floatRegs.i[tid][reg_idx] = val;
1144 }
1145
1146 uint64_t
1147 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1148 {
1149     // If Default value is set, then retrieve target thread
1150     if (tid == InvalidThreadID) {
1151         tid = TheISA::getTargetThread(tcBase(tid));
1152     }
1153
1154     if (reg_idx < FP_Base_DepTag) {
1155         // Integer Register File
1156         return readIntReg(reg_idx, tid);
1157     } else if (reg_idx < Ctrl_Base_DepTag) {
1158         // Float Register File
1159         reg_idx -= FP_Base_DepTag;
1160         return readFloatRegBits(reg_idx, tid);
1161     } else {
1162         reg_idx -= Ctrl_Base_DepTag;
1163         return readMiscReg(reg_idx, tid);  // Misc. Register File
1164     }
1165 }
1166 void
1167 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1168                               ThreadID tid)
1169 {
1170     // If Default value is set, then retrieve target thread
1171     if (tid == InvalidThreadID) {
1172         tid = TheISA::getTargetThread(tcBase(tid));
1173     }
1174
1175     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1176         setIntReg(reg_idx, val, tid);
1177     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1178         reg_idx -= FP_Base_DepTag;
1179         setFloatRegBits(reg_idx, val, tid);
1180     } else {
1181         reg_idx -= Ctrl_Base_DepTag;
1182         setMiscReg(reg_idx, val, tid); // Misc. Register File
1183     }
1184 }
1185
1186 MiscReg
1187 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1188 {
1189     return isa[tid].readMiscRegNoEffect(misc_reg);
1190 }
1191
1192 MiscReg
1193 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1194 {
1195     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1196 }
1197
1198 void
1199 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1200 {
1201     isa[tid].setMiscRegNoEffect(misc_reg, val);
1202 }
1203
1204 void
1205 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1206 {
1207     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1208 }
1209
1210
1211 InOrderCPU::ListIt
1212 InOrderCPU::addInst(DynInstPtr &inst)
1213 {
1214     ThreadID tid = inst->readTid();
1215
1216     instList[tid].push_back(inst);
1217
1218     return --(instList[tid].end());
1219 }
1220
1221 void
1222 InOrderCPU::updateContextSwitchStats()
1223 {
1224     // Set Average Stat Here, then reset to 0
1225     instsPerCtxtSwitch = instsPerSwitch;
1226     instsPerSwitch = 0;
1227 }
1228
1229
1230 void
1231 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1232 {
1233     // Set the CPU's PCs - This contributes to the precise state of the CPU
1234     // which can be used when restoring a thread to the CPU after after any
1235     // type of context switching activity (fork, exception, etc.)
1236     pcState(inst->pcState(), tid);
1237
1238     if (inst->isControl()) {
1239         thread[tid]->lastGradIsBranch = true;
1240         thread[tid]->lastBranchPC = inst->pcState();
1241         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1242     } else {
1243         thread[tid]->lastGradIsBranch = false;
1244     }
1245
1246
1247     // Finalize Trace Data For Instruction
1248     if (inst->traceData) {
1249         //inst->traceData->setCycle(curTick());
1250         inst->traceData->setFetchSeq(inst->seqNum);
1251         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1252         inst->traceData->dump();
1253         delete inst->traceData;
1254         inst->traceData = NULL;
1255     }
1256
1257     // Increment active thread's instruction count
1258     instsPerSwitch++;
1259
1260     // Increment thread-state's instruction count
1261     thread[tid]->numInst++;
1262
1263     // Increment thread-state's instruction stats
1264     thread[tid]->numInsts++;
1265
1266     // Count committed insts per thread stats
1267     committedInsts[tid]++;
1268
1269     // Count total insts committed stat
1270     totalCommittedInsts++;
1271
1272     // Count SMT-committed insts per thread stat
1273     if (numActiveThreads() > 1) {
1274         smtCommittedInsts[tid]++;
1275     }
1276
1277     // Instruction-Mix Stats
1278     if (inst->isLoad()) {
1279         comLoads++;
1280     } else if (inst->isStore()) {
1281         comStores++;
1282     } else if (inst->isControl()) {
1283         comBranches++;
1284     } else if (inst->isNop()) {
1285         comNops++;
1286     } else if (inst->isNonSpeculative()) {
1287         comNonSpec++;
1288     } else if (inst->isInteger()) {
1289         comInts++;
1290     } else if (inst->isFloating()) {
1291         comFloats++;
1292     }
1293
1294     // Check for instruction-count-based events.
1295     comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1296
1297     // Broadcast to other resources an instruction
1298     // has been completed
1299     resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
1300                            0, 0, tid);
1301
1302     // Finally, remove instruction from CPU
1303     removeInst(inst);
1304 }
1305
1306 // currently unused function, but substitute repetitive code w/this function
1307 // call
1308 void
1309 InOrderCPU::addToRemoveList(DynInstPtr &inst)
1310 {
1311     removeInstsThisCycle = true;
1312     if (!inst->isRemoveList()) {
1313         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1314                 "[sn:%lli] to remove list\n",
1315                 inst->threadNumber, inst->pcState(), inst->seqNum);
1316         inst->setRemoveList();
1317         removeList.push(inst->getInstListIt());
1318     }  else {
1319         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1320                 "[sn:%lli], already remove list\n",
1321                 inst->threadNumber, inst->pcState(), inst->seqNum);
1322     }
1323
1324 }
1325
1326 void
1327 InOrderCPU::removeInst(DynInstPtr &inst)
1328 {
1329     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1330             "[sn:%lli]\n",
1331             inst->threadNumber, inst->pcState(), inst->seqNum);
1332
1333     removeInstsThisCycle = true;
1334
1335     // Remove the instruction.
1336     if (!inst->isRemoveList()) {
1337         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1338                 "[sn:%lli] to remove list\n",
1339                 inst->threadNumber, inst->pcState(), inst->seqNum);
1340         inst->setRemoveList();
1341         removeList.push(inst->getInstListIt());
1342     } else {
1343         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1344                 "[sn:%lli], already on remove list\n",
1345                 inst->threadNumber, inst->pcState(), inst->seqNum);
1346     }
1347
1348 }
1349
1350 void
1351 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1352 {
1353     //assert(!instList[tid].empty());
1354
1355     removeInstsThisCycle = true;
1356
1357     ListIt inst_iter = instList[tid].end();
1358
1359     inst_iter--;
1360
1361     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1362             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1363             tid, seq_num, (*inst_iter)->seqNum);
1364
1365     while ((*inst_iter)->seqNum > seq_num) {
1366
1367         bool break_loop = (inst_iter == instList[tid].begin());
1368
1369         squashInstIt(inst_iter, tid);
1370
1371         inst_iter--;
1372
1373         if (break_loop)
1374             break;
1375     }
1376 }
1377
1378
1379 inline void
1380 InOrderCPU::squashInstIt(const ListIt &instIt, ThreadID tid)
1381 {
1382     if ((*instIt)->threadNumber == tid) {
1383         DPRINTF(InOrderCPU, "Squashing instruction, "
1384                 "[tid:%i] [sn:%lli] PC %s\n",
1385                 (*instIt)->threadNumber,
1386                 (*instIt)->seqNum,
1387                 (*instIt)->pcState());
1388
1389         (*instIt)->setSquashed();
1390
1391         if (!(*instIt)->isRemoveList()) {
1392             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1393                     "[sn:%lli] to remove list\n",
1394                     (*instIt)->threadNumber, (*instIt)->pcState(),
1395                     (*instIt)->seqNum);
1396             (*instIt)->setRemoveList();
1397             removeList.push(instIt);
1398         } else {
1399             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1400                     " PC %s [sn:%lli], already on remove list\n",
1401                     (*instIt)->threadNumber, (*instIt)->pcState(),
1402                     (*instIt)->seqNum);
1403         }
1404
1405     }
1406
1407 }
1408
1409
1410 void
1411 InOrderCPU::cleanUpRemovedInsts()
1412 {
1413     while (!removeList.empty()) {
1414         DPRINTF(InOrderCPU, "Removing instruction, "
1415                 "[tid:%i] [sn:%lli] PC %s\n",
1416                 (*removeList.front())->threadNumber,
1417                 (*removeList.front())->seqNum,
1418                (*removeList.front())->pcState());
1419
1420         DynInstPtr inst = *removeList.front();
1421         ThreadID tid = inst->threadNumber;
1422
1423         // Remove From Register Dependency Map, If Necessary
1424         archRegDepMap[(*removeList.front())->threadNumber].
1425             remove((*removeList.front()));
1426
1427
1428         // Clear if Non-Speculative
1429         if (inst->staticInst &&
1430             inst->seqNum == nonSpecSeqNum[tid] &&
1431             nonSpecInstActive[tid] == true) {
1432             nonSpecInstActive[tid] = false;
1433         }
1434
1435         instList[tid].erase(removeList.front());
1436
1437         removeList.pop();
1438     }
1439
1440     removeInstsThisCycle = false;
1441 }
1442
1443 void
1444 InOrderCPU::cleanUpRemovedEvents()
1445 {
1446     while (!cpuEventRemoveList.empty()) {
1447         Event *cpu_event = cpuEventRemoveList.front();
1448         cpuEventRemoveList.pop();
1449         delete cpu_event;
1450     }
1451 }
1452
1453
1454 void
1455 InOrderCPU::dumpInsts()
1456 {
1457     int num = 0;
1458
1459     ListIt inst_list_it = instList[0].begin();
1460
1461     cprintf("Dumping Instruction List\n");
1462
1463     while (inst_list_it != instList[0].end()) {
1464         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1465                 "Squashed:%i\n\n",
1466                 num, (*inst_list_it)->pcState(),
1467                 (*inst_list_it)->threadNumber,
1468                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1469                 (*inst_list_it)->isSquashed());
1470         inst_list_it++;
1471         ++num;
1472     }
1473 }
1474
1475 void
1476 InOrderCPU::wakeCPU()
1477 {
1478     if (/*activityRec.active() || */tickEvent.scheduled()) {
1479         DPRINTF(Activity, "CPU already running.\n");
1480         return;
1481     }
1482
1483     DPRINTF(Activity, "Waking up CPU\n");
1484
1485     Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
1486
1487     idleCycles += extra_cycles;
1488     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1489         pipelineStage[stage_num]->idleCycles += extra_cycles;
1490     }
1491
1492     numCycles += extra_cycles;
1493
1494     schedule(&tickEvent, nextCycle(curTick()));
1495 }
1496
1497 #if FULL_SYSTEM
1498
1499 void
1500 InOrderCPU::wakeup()
1501 {
1502     if (thread[0]->status() != ThreadContext::Suspended)
1503         return;
1504
1505     wakeCPU();
1506
1507     DPRINTF(Quiesce, "Suspended Processor woken\n");
1508     threadContexts[0]->activate();
1509 }
1510 #endif
1511
1512 #if !FULL_SYSTEM
1513 void
1514 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1515 {
1516     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1517
1518     DPRINTF(Activity,"Activity: syscall() called.\n");
1519
1520     // Temporarily increase this by one to account for the syscall
1521     // instruction.
1522     ++(this->thread[tid]->funcExeInst);
1523
1524     // Execute the actual syscall.
1525     this->thread[tid]->syscall(callnum);
1526
1527     // Decrease funcExeInst by one as the normal commit will handle
1528     // incrementing it.
1529     --(this->thread[tid]->funcExeInst);
1530
1531     // Clear Non-Speculative Block Variable
1532     nonSpecInstActive[tid] = false;
1533 }
1534 #endif
1535
1536 TheISA::TLB*
1537 InOrderCPU::getITBPtr()
1538 {
1539     CacheUnit *itb_res =
1540         dynamic_cast<CacheUnit*>(resPool->getResource(fetchPortIdx));
1541     return itb_res->tlb();
1542 }
1543
1544
1545 TheISA::TLB*
1546 InOrderCPU::getDTBPtr()
1547 {
1548     CacheUnit *dtb_res =
1549         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1550     return dtb_res->tlb();
1551 }
1552
1553 Fault
1554 InOrderCPU::read(DynInstPtr inst, Addr addr,
1555                  uint8_t *data, unsigned size, unsigned flags)
1556 {
1557     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1558     //       you want to run w/out caches?
1559     CacheUnit *cache_res =
1560         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1561
1562     return cache_res->read(inst, addr, data, size, flags);
1563 }
1564
1565 Fault
1566 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1567                   Addr addr, unsigned flags, uint64_t *write_res)
1568 {
1569     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1570     //       you want to run w/out caches?
1571     CacheUnit *cache_res =
1572         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1573     return cache_res->write(inst, data, size, addr, flags, write_res);
1574 }