src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <algorithm>
  33
  34 #include "arch/utility.hh"
  35 #include "config/full_system.hh"
  36 #include "config/the_isa.hh"
  37 #include "cpu/activity.hh"
  38 #include "cpu/base.hh"
  39 #include "cpu/exetrace.hh"
  40 #include "cpu/inorder/cpu.hh"
  41 #include "cpu/inorder/first_stage.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource_pool.hh"
  45 #include "cpu/inorder/resources/resource_list.hh"
  46 #include "cpu/inorder/thread_context.hh"
  47 #include "cpu/inorder/thread_state.hh"
  48 #include "cpu/simple_thread.hh"
  49 #include "cpu/thread_context.hh"
  50 #include "mem/translating_port.hh"
  51 #include "params/InOrderCPU.hh"
  52 #include "sim/process.hh"
  53 #include "sim/stat_control.hh"
  54
  55 #if FULL_SYSTEM
  56 #include "cpu/quiesce_event.hh"
  57 #include "sim/system.hh"
  58 #endif
  59
  60 #if THE_ISA == ALPHA_ISA
  61 #include "arch/alpha/osfpal.hh"
  62 #endif
  63
  64 using namespace std;
  65 using namespace TheISA;
  66 using namespace ThePipeline;
  67
  68 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
  69   : Event(CPU_Tick_Pri), cpu(c)
  70 { }
  71
  72
  73 void
  74 InOrderCPU::TickEvent::process()
  75 {
  76     cpu->tick();
  77 }
  78
  79
  80 const char *
  81 InOrderCPU::TickEvent::description()
  82 {
  83     return "InOrderCPU tick event";
  84 }
  85
  86 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
  87                                Fault fault, ThreadID _tid, DynInstPtr inst,
  88                                unsigned event_pri_offset)
  89     : Event(Event::Priority((unsigned int)CPU_Tick_Pri + event_pri_offset)),
  90       cpu(_cpu)
  91 {
  92     setEvent(e_type, fault, _tid, inst);
  93 }
  94
  95
  96 std::string InOrderCPU::eventNames[NumCPUEvents] =
  97 {
  98     "ActivateThread",
  99     "ActivateNextReadyThread",
 100     "DeactivateThread",
 101     "HaltThread",
 102     "SuspendThread",
 103     "Trap",
 104     "InstGraduated",
 105     "SquashFromMemStall",
 106     "UpdatePCs"
 107 };
 108
 109 void
 110 InOrderCPU::CPUEvent::process()
 111 {
 112     switch (cpuEventType)
 113     {
 114       case ActivateThread:
 115         cpu->activateThread(tid);
 116         break;
 117
 118       case ActivateNextReadyThread:
 119         cpu->activateNextReadyThread();
 120         break;
 121
 122       case DeactivateThread:
 123         cpu->deactivateThread(tid);
 124         break;
 125
 126       case HaltThread:
 127         cpu->haltThread(tid);
 128         break;
 129
 130       case SuspendThread:
 131         cpu->suspendThread(tid);
 132         break;
 133
 134       case SquashFromMemStall:
 135         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 136         break;
 137
 138       case Trap:
 139         cpu->trapCPU(fault, tid, inst);
 140         break;
 141
 142       default:
 143         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 144     }
 145
 146     cpu->cpuEventRemoveList.push(this);
 147 }
 148
 149
 150
 151 const char *
 152 InOrderCPU::CPUEvent::description()
 153 {
 154     return "InOrderCPU event";
 155 }
 156
 157 void
 158 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 159 {
 160     if (squashed())
 161         mainEventQueue.reschedule(this, cpu->nextCycle(curTick +
 162                                                        cpu->ticks(delay)));
 163     else if (!scheduled())
 164         mainEventQueue.schedule(this, cpu->nextCycle(curTick +
 165                                                      cpu->ticks(delay)));
 166 }
 167
 168 void
 169 InOrderCPU::CPUEvent::unscheduleEvent()
 170 {
 171     if (scheduled())
 172         squash();
 173 }
 174
 175 InOrderCPU::InOrderCPU(Params *params)
 176     : BaseCPU(params),
 177       cpu_id(params->cpu_id),
 178       coreType("default"),
 179       _status(Idle),
 180       tickEvent(this),
 181       timeBuffer(2 , 2),
 182       removeInstsThisCycle(false),
 183       activityRec(params->name, NumStages, 10, params->activity),
 184 #if FULL_SYSTEM
 185       system(params->system),
 186       physmem(system->physmem),
 187 #endif // FULL_SYSTEM
 188 #ifdef DEBUG
 189       cpuEventNum(0),
 190       resReqCount(0),
 191 #endif // DEBUG
 192       switchCount(0),
 193       deferRegistration(false/*params->deferRegistration*/),
 194       stageTracing(params->stageTracing),
 195       instsPerSwitch(0)
 196 {
 197     ThreadID active_threads;
 198     cpu_params = params;
 199
 200     resPool = new ResourcePool(this, params);
 201
 202     // Resize for Multithreading CPUs
 203     thread.resize(numThreads);
 204
 205 #if FULL_SYSTEM
 206     active_threads = 1;
 207 #else
 208     active_threads = params->workload.size();
 209
 210     if (active_threads > MaxThreads) {
 211         panic("Workload Size too large. Increase the 'MaxThreads'"
 212               "in your InOrder implementation or "
 213               "edit your workload size.");
 214     }
 215
 216
 217     if (active_threads > 1) {
 218         threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 219
 220         if (threadModel == SMT) {
 221             DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 222         } else if (threadModel == SwitchOnCacheMiss) {
 223             DPRINTF(InOrderCPU, "Setting Thread Model to "
 224                     "Switch On Cache Miss\n");
 225         }
 226
 227     } else {
 228         threadModel = Single;
 229     }
 230
 231
 232
 233 #endif
 234
 235     // Bind the fetch & data ports from the resource pool.
 236     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
 237     if (fetchPortIdx == 0) {
 238         fatal("Unable to find port to fetch instructions from.\n");
 239     }
 240
 241     dataPortIdx = resPool->getPortIdx(params->dataMemPort);
 242     if (dataPortIdx == 0) {
 243         fatal("Unable to find port for data.\n");
 244     }
 245
 246     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 247 #if FULL_SYSTEM
 248         // SMT is not supported in FS mode yet.
 249         assert(numThreads == 1);
 250         thread[tid] = new Thread(this, 0);
 251 #else
 252         if (tid < (ThreadID)params->workload.size()) {
 253             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 254                     tid, params->workload[tid]->prog_fname);
 255             thread[tid] =
 256                 new Thread(this, tid, params->workload[tid]);
 257         } else {
 258             //Allocate Empty thread so M5 can use later
 259             //when scheduling threads to CPU
 260             Process* dummy_proc = params->workload[0];
 261             thread[tid] = new Thread(this, tid, dummy_proc);
 262         }
 263
 264         // Eventually set this with parameters...
 265         asid[tid] = tid;
 266 #endif
 267
 268         // Setup the TC that will serve as the interface to the threads/CPU.
 269         InOrderThreadContext *tc = new InOrderThreadContext;
 270         tc->cpu = this;
 271         tc->thread = thread[tid];
 272
 273         // Give the thread the TC.
 274         thread[tid]->tc = tc;
 275         thread[tid]->setFuncExeInst(0);
 276         globalSeqNum[tid] = 1;
 277
 278         // Add the TC to the CPU's list of TC's.
 279         this->threadContexts.push_back(tc);
 280     }
 281
 282     // Initialize TimeBuffer Stage Queues
 283     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 284         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 285         stageQueue[stNum]->id(stNum);
 286     }
 287
 288
 289     // Set Up Pipeline Stages
 290     for (int stNum=0; stNum < NumStages; stNum++) {
 291         if (stNum == 0)
 292             pipelineStage[stNum] = new FirstStage(params, stNum);
 293         else
 294             pipelineStage[stNum] = new PipelineStage(params, stNum);
 295
 296         pipelineStage[stNum]->setCPU(this);
 297         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 298         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 299
 300         // Take Care of 1st/Nth stages
 301         if (stNum > 0)
 302             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 303         if (stNum < NumStages - 1)
 304             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 305     }
 306
 307     // Initialize thread specific variables
 308     for (ThreadID tid = 0; tid < numThreads; tid++) {
 309         archRegDepMap[tid].setCPU(this);
 310
 311         nonSpecInstActive[tid] = false;
 312         nonSpecSeqNum[tid] = 0;
 313
 314         squashSeqNum[tid] = MaxAddr;
 315         lastSquashCycle[tid] = 0;
 316
 317         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 318         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 319         isa[tid].clear();
 320
 321         isa[tid].expandForMultithreading(numThreads, 1/*numVirtProcs*/);
 322
 323         // Define dummy instructions and resource requests to be used.
 324         dummyInst[tid] = new InOrderDynInst(this,
 325                                             thread[tid],
 326                                             0,
 327                                             tid,
 328                                             asid[tid]);
 329
 330         dummyReq[tid] = new ResourceRequest(resPool->getResource(0),
 331                                             dummyInst[tid],
 332                                             0,
 333                                             0,
 334                                             0,
 335                                             0);
 336     }
 337
 338     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 339     dummyReqInst->setSquashed();
 340
 341     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 342     dummyBufferInst->setSquashed();
 343
 344     lastRunningCycle = curTick;
 345
 346     // Reset CPU to reset state.
 347 #if FULL_SYSTEM
 348     Fault resetFault = new ResetFault();
 349     resetFault->invoke(tcBase());
 350 #else
 351     reset();
 352 #endif
 353
 354     dummyBufferInst->resetInstCount();
 355
 356     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 357     scheduleTickEvent(0);
 358 }
 359
 360 InOrderCPU::~InOrderCPU()
 361 {
 362     delete resPool;
 363 }
 364
 365
 366 void
 367 InOrderCPU::regStats()
 368 {
 369     /* Register the Resource Pool's stats here.*/
 370     resPool->regStats();
 371
 372     /* Register for each Pipeline Stage */
 373     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 374         pipelineStage[stage_num]->regStats();
 375     }
 376
 377     /* Register any of the InOrderCPU's stats here.*/
 378     instsPerCtxtSwitch
 379         .name(name() + ".instsPerContextSwitch")
 380         .desc("Instructions Committed Per Context Switch")
 381         .prereq(instsPerCtxtSwitch);
 382
 383     numCtxtSwitches
 384         .name(name() + ".contextSwitches")
 385         .desc("Number of context switches");
 386
 387     comLoads
 388         .name(name() + ".comLoads")
 389         .desc("Number of Load instructions committed");
 390
 391     comStores
 392         .name(name() + ".comStores")
 393         .desc("Number of Store instructions committed");
 394
 395     comBranches
 396         .name(name() + ".comBranches")
 397         .desc("Number of Branches instructions committed");
 398
 399     comNops
 400         .name(name() + ".comNops")
 401         .desc("Number of Nop instructions committed");
 402
 403     comNonSpec
 404         .name(name() + ".comNonSpec")
 405         .desc("Number of Non-Speculative instructions committed");
 406
 407     comInts
 408         .name(name() + ".comInts")
 409         .desc("Number of Integer instructions committed");
 410
 411     comFloats
 412         .name(name() + ".comFloats")
 413         .desc("Number of Floating Point instructions committed");
 414
 415     timesIdled
 416         .name(name() + ".timesIdled")
 417         .desc("Number of times that the entire CPU went into an idle state and"
 418               " unscheduled itself")
 419         .prereq(timesIdled);
 420
 421     idleCycles
 422         .name(name() + ".idleCycles")
 423         .desc("Number of cycles cpu's stages were not processed");
 424
 425     runCycles
 426         .name(name() + ".runCycles")
 427         .desc("Number of cycles cpu stages are processed.");
 428
 429     activity
 430         .name(name() + ".activity")
 431         .desc("Percentage of cycles cpu is active")
 432         .precision(6);
 433     activity = (runCycles / numCycles) * 100;
 434
 435     threadCycles
 436         .init(numThreads)
 437         .name(name() + ".threadCycles")
 438         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 439
 440     smtCycles
 441         .name(name() + ".smtCycles")
 442         .desc("Total number of cycles that the CPU was in SMT-mode");
 443
 444     committedInsts
 445         .init(numThreads)
 446         .name(name() + ".committedInsts")
 447         .desc("Number of Instructions Simulated (Per-Thread)");
 448
 449     smtCommittedInsts
 450         .init(numThreads)
 451         .name(name() + ".smtCommittedInsts")
 452         .desc("Number of SMT Instructions Simulated (Per-Thread)");
 453
 454     totalCommittedInsts
 455         .name(name() + ".committedInsts_total")
 456         .desc("Number of Instructions Simulated (Total)");
 457
 458     cpi
 459         .name(name() + ".cpi")
 460         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 461         .precision(6);
 462     cpi = numCycles / committedInsts;
 463
 464     smtCpi
 465         .name(name() + ".smt_cpi")
 466         .desc("CPI: Total SMT-CPI")
 467         .precision(6);
 468     smtCpi = smtCycles / smtCommittedInsts;
 469
 470     totalCpi
 471         .name(name() + ".cpi_total")
 472         .desc("CPI: Total CPI of All Threads")
 473         .precision(6);
 474     totalCpi = numCycles / totalCommittedInsts;
 475
 476     ipc
 477         .name(name() + ".ipc")
 478         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 479         .precision(6);
 480     ipc =  committedInsts / numCycles;
 481
 482     smtIpc
 483         .name(name() + ".smt_ipc")
 484         .desc("IPC: Total SMT-IPC")
 485         .precision(6);
 486     smtIpc = smtCommittedInsts / smtCycles;
 487
 488     totalIpc
 489         .name(name() + ".ipc_total")
 490         .desc("IPC: Total IPC of All Threads")
 491         .precision(6);
 492         totalIpc =  totalCommittedInsts / numCycles;
 493
 494     BaseCPU::regStats();
 495 }
 496
 497
 498 void
 499 InOrderCPU::tick()
 500 {
 501     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 502
 503     ++numCycles;
 504
 505     bool pipes_idle = true;
 506
 507     //Tick each of the stages
 508     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 509         pipelineStage[stNum]->tick();
 510
 511         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 512     }
 513
 514     if (pipes_idle)
 515         idleCycles++;
 516     else
 517         runCycles++;
 518
 519     // Now advance the time buffers one tick
 520     timeBuffer.advance();
 521     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 522         stageQueue[sqNum]->advance();
 523     }
 524     activityRec.advance();
 525
 526     // Any squashed requests, events, or insts then remove them now
 527     cleanUpRemovedReqs();
 528     cleanUpRemovedEvents();
 529     cleanUpRemovedInsts();
 530
 531     // Re-schedule CPU for this cycle
 532     if (!tickEvent.scheduled()) {
 533         if (_status == SwitchedOut) {
 534             // increment stat
 535             lastRunningCycle = curTick;
 536         } else if (!activityRec.active()) {
 537             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 538             lastRunningCycle = curTick;
 539             timesIdled++;
 540         } else {
 541             //Tick next_tick = curTick + cycles(1);
 542             //tickEvent.schedule(next_tick);
 543             mainEventQueue.schedule(&tickEvent, nextCycle(curTick + 1));
 544             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 545                     nextCycle(curTick + 1));
 546         }
 547     }
 548
 549     tickThreadStats();
 550     updateThreadPriority();
 551 }
 552
 553
 554 void
 555 InOrderCPU::init()
 556 {
 557     if (!deferRegistration) {
 558         registerThreadContexts();
 559     }
 560
 561     // Set inSyscall so that the CPU doesn't squash when initially
 562     // setting up registers.
 563     for (ThreadID tid = 0; tid < numThreads; ++tid)
 564         thread[tid]->inSyscall = true;
 565
 566 #if FULL_SYSTEM
 567     for (ThreadID tid = 0; tid < numThreads; tid++) {
 568         ThreadContext *src_tc = threadContexts[tid];
 569         TheISA::initCPU(src_tc, src_tc->contextId());
 570     }
 571 #endif
 572
 573     // Clear inSyscall.
 574     for (ThreadID tid = 0; tid < numThreads; ++tid)
 575         thread[tid]->inSyscall = false;
 576
 577     // Call Initializiation Routine for Resource Pool
 578     resPool->init();
 579 }
 580
 581 void
 582 InOrderCPU::reset()
 583 {
 584     for (int i = 0; i < numThreads; i++) {
 585         isa[i].reset(coreType, numThreads,
 586                      1/*numVirtProcs*/, dynamic_cast<BaseCPU*>(this));
 587     }
 588 }
 589
 590 Port*
 591 InOrderCPU::getPort(const std::string &if_name, int idx)
 592 {
 593     return resPool->getPort(if_name, idx);
 594 }
 595
 596 #if FULL_SYSTEM
 597 Fault
 598 InOrderCPU::hwrei(ThreadID tid)
 599 {
 600     panic("hwrei: Unimplemented");
 601
 602     return NoFault;
 603 }
 604
 605
 606 bool
 607 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 608 {
 609     panic("simPalCheck: Unimplemented");
 610
 611     return true;
 612 }
 613
 614
 615 Fault
 616 InOrderCPU::getInterrupts()
 617 {
 618     // Check if there are any outstanding interrupts
 619     return this->interrupts->getInterrupt(this->threadContexts[0]);
 620 }
 621
 622
 623 void
 624 InOrderCPU::processInterrupts(Fault interrupt)
 625 {
 626     // Check for interrupts here.  For now can copy the code that
 627     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 628     // is the one that handles the interrupts.
 629     // @todo: Possibly consolidate the interrupt checking code.
 630     // @todo: Allow other threads to handle interrupts.
 631
 632     assert(interrupt != NoFault);
 633     this->interrupts->updateIntrInfo(this->threadContexts[0]);
 634
 635     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 636     static StaticInstPtr dummyStatic(TheISA::NoopMachInst, 0);
 637     static DynInstPtr dummyDyn = new Impl::DynInst(dummyStatic);
 638     this->trap(interrupt, dummyDyn);
 639 }
 640
 641
 642 void
 643 InOrderCPU::updateMemPorts()
 644 {
 645     // Update all ThreadContext's memory ports (Functional/Virtual
 646     // Ports)
 647     ThreadID size = thread.size();
 648     for (ThreadID i = 0; i < size; ++i)
 649         thread[i]->connectMemPorts(thread[i]->getTC());
 650 }
 651 #endif
 652
 653 void
 654 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 655 {
 656     //@ Squash Pipeline during TRAP
 657     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 658 }
 659
 660 void
 661 InOrderCPU::trapCPU(Fault fault, ThreadID tid, DynInstPtr inst)
 662 {
 663     fault->invoke(tcBase(tid), inst->staticInst);
 664 }
 665
 666 void
 667 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 668 {
 669     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 670 }
 671
 672
 673 void
 674 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 675                                 ThreadID tid)
 676 {
 677     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 678
 679     // Squash all instructions in each stage including
 680     // instruction that caused the squash (seq_num - 1)
 681     // NOTE: The stage bandwidth needs to be cleared so thats why
 682     //       the stalling instruction is squashed as well. The stalled
 683     //       instruction is previously placed in another intermediate buffer
 684     //       while it's stall is being handled.
 685     InstSeqNum squash_seq_num = seq_num - 1;
 686
 687     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 688         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 689     }
 690 }
 691
 692 void
 693 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 694                              ThreadID tid, DynInstPtr inst,
 695                              unsigned delay, unsigned event_pri_offset)
 696 {
 697     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 698                                        event_pri_offset);
 699
 700     Tick sked_tick = nextCycle(curTick + ticks(delay));
 701     if (delay >= 0) {
 702         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 703                 eventNames[c_event], curTick + delay, tid);
 704         mainEventQueue.schedule(cpu_event, sked_tick);
 705     } else {
 706         cpu_event->process();
 707         cpuEventRemoveList.push(cpu_event);
 708     }
 709
 710     // Broadcast event to the Resource Pool
 711     // Need to reset tid just in case this is a dummy instruction
 712     inst->setTid(tid);
 713     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 714 }
 715
 716 bool
 717 InOrderCPU::isThreadActive(ThreadID tid)
 718 {
 719   list<ThreadID>::iterator isActive =
 720       std::find(activeThreads.begin(), activeThreads.end(), tid);
 721
 722     return (isActive != activeThreads.end());
 723 }
 724
 725 bool
 726 InOrderCPU::isThreadReady(ThreadID tid)
 727 {
 728   list<ThreadID>::iterator isReady =
 729       std::find(readyThreads.begin(), readyThreads.end(), tid);
 730
 731     return (isReady != readyThreads.end());
 732 }
 733
 734 bool
 735 InOrderCPU::isThreadSuspended(ThreadID tid)
 736 {
 737   list<ThreadID>::iterator isSuspended =
 738       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
 739
 740     return (isSuspended != suspendedThreads.end());
 741 }
 742
 743 void
 744 InOrderCPU::activateNextReadyThread()
 745 {
 746     if (readyThreads.size() >= 1) {
 747         ThreadID ready_tid = readyThreads.front();
 748
 749         // Activate in Pipeline
 750         activateThread(ready_tid);
 751
 752         // Activate in Resource Pool
 753         resPool->activateAll(ready_tid);
 754
 755         list<ThreadID>::iterator ready_it =
 756             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
 757         readyThreads.erase(ready_it);
 758     } else {
 759         DPRINTF(InOrderCPU,
 760                 "Attempting to activate new thread, but No Ready Threads to"
 761                 "activate.\n");
 762         DPRINTF(InOrderCPU,
 763                 "Unable to switch to next active thread.\n");
 764     }
 765 }
 766
 767 void
 768 InOrderCPU::activateThread(ThreadID tid)
 769 {
 770     if (isThreadSuspended(tid)) {
 771         DPRINTF(InOrderCPU,
 772                 "Removing [tid:%i] from suspended threads list.\n", tid);
 773
 774         list<ThreadID>::iterator susp_it =
 775             std::find(suspendedThreads.begin(), suspendedThreads.end(),
 776                       tid);
 777         suspendedThreads.erase(susp_it);
 778     }
 779
 780     if (threadModel == SwitchOnCacheMiss &&
 781         numActiveThreads() == 1) {
 782         DPRINTF(InOrderCPU,
 783                 "Ignoring activation of [tid:%i], since [tid:%i] is "
 784                 "already running.\n", tid, activeThreadId());
 785
 786         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
 787                 tid);
 788
 789         readyThreads.push_back(tid);
 790
 791     } else if (!isThreadActive(tid)) {
 792         DPRINTF(InOrderCPU,
 793                 "Adding [tid:%i] to active threads list.\n", tid);
 794         activeThreads.push_back(tid);
 795
 796         activateThreadInPipeline(tid);
 797
 798         thread[tid]->lastActivate = curTick;
 799
 800         tcBase(tid)->setStatus(ThreadContext::Active);
 801
 802         wakeCPU();
 803
 804         numCtxtSwitches++;
 805     }
 806 }
 807
 808 void
 809 InOrderCPU::activateThreadInPipeline(ThreadID tid)
 810 {
 811     for (int stNum=0; stNum < NumStages; stNum++) {
 812         pipelineStage[stNum]->activateThread(tid);
 813     }
 814 }
 815
 816 void
 817 InOrderCPU::deactivateContext(ThreadID tid, int delay)
 818 {
 819     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
 820
 821     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
 822
 823     // Be sure to signal that there's some activity so the CPU doesn't
 824     // deschedule itself.
 825     activityRec.activity();
 826
 827     _status = Running;
 828 }
 829
 830 void
 831 InOrderCPU::deactivateThread(ThreadID tid)
 832 {
 833     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
 834
 835     if (isThreadActive(tid)) {
 836         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
 837                 tid);
 838         list<ThreadID>::iterator thread_it =
 839             std::find(activeThreads.begin(), activeThreads.end(), tid);
 840
 841         removePipelineStalls(*thread_it);
 842
 843         activeThreads.erase(thread_it);
 844
 845         // Ideally, this should be triggered from the
 846         // suspendContext/Thread functions
 847         tcBase(tid)->setStatus(ThreadContext::Suspended);
 848     }
 849
 850     assert(!isThreadActive(tid));
 851 }
 852
 853 void
 854 InOrderCPU::removePipelineStalls(ThreadID tid)
 855 {
 856     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
 857             tid);
 858
 859     for (int stNum = 0; stNum < NumStages ; stNum++) {
 860         pipelineStage[stNum]->removeStalls(tid);
 861     }
 862
 863 }
 864
 865 void
 866 InOrderCPU::updateThreadPriority()
 867 {
 868     if (activeThreads.size() > 1)
 869     {
 870         //DEFAULT TO ROUND ROBIN SCHEME
 871         //e.g. Move highest priority to end of thread list
 872         list<ThreadID>::iterator list_begin = activeThreads.begin();
 873         list<ThreadID>::iterator list_end   = activeThreads.end();
 874
 875         unsigned high_thread = *list_begin;
 876
 877         activeThreads.erase(list_begin);
 878
 879         activeThreads.push_back(high_thread);
 880     }
 881 }
 882
 883 inline void
 884 InOrderCPU::tickThreadStats()
 885 {
 886     /** Keep track of cycles that each thread is active */
 887     list<ThreadID>::iterator thread_it = activeThreads.begin();
 888     while (thread_it != activeThreads.end()) {
 889         threadCycles[*thread_it]++;
 890         thread_it++;
 891     }
 892
 893     // Keep track of cycles where SMT is active
 894     if (activeThreads.size() > 1) {
 895         smtCycles++;
 896     }
 897 }
 898
 899 void
 900 InOrderCPU::activateContext(ThreadID tid, int delay)
 901 {
 902     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
 903
 904
 905     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
 906
 907     // Be sure to signal that there's some activity so the CPU doesn't
 908     // deschedule itself.
 909     activityRec.activity();
 910
 911     _status = Running;
 912 }
 913
 914 void
 915 InOrderCPU::activateNextReadyContext(int delay)
 916 {
 917     DPRINTF(InOrderCPU,"Activating next ready thread\n");
 918
 919     // NOTE: Add 5 to the event priority so that we always activate
 920     // threads after we've finished deactivating, squashing,etc.
 921     // other threads
 922     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
 923                      delay, 5);
 924
 925     // Be sure to signal that there's some activity so the CPU doesn't
 926     // deschedule itself.
 927     activityRec.activity();
 928
 929     _status = Running;
 930 }
 931
 932 void
 933 InOrderCPU::haltContext(ThreadID tid, int delay)
 934 {
 935     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
 936
 937     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
 938
 939     activityRec.activity();
 940 }
 941
 942 void
 943 InOrderCPU::haltThread(ThreadID tid)
 944 {
 945     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
 946     deactivateThread(tid);
 947     squashThreadInPipeline(tid);
 948     haltedThreads.push_back(tid);
 949
 950     tcBase(tid)->setStatus(ThreadContext::Halted);
 951
 952     if (threadModel == SwitchOnCacheMiss) {
 953         activateNextReadyContext();
 954     }
 955 }
 956
 957 void
 958 InOrderCPU::suspendContext(ThreadID tid, int delay)
 959 {
 960     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
 961 }
 962
 963 void
 964 InOrderCPU::suspendThread(ThreadID tid)
 965 {
 966     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
 967             tid);
 968     deactivateThread(tid);
 969     suspendedThreads.push_back(tid);
 970     thread[tid]->lastSuspend = curTick;
 971
 972     tcBase(tid)->setStatus(ThreadContext::Suspended);
 973 }
 974
 975 void
 976 InOrderCPU::squashThreadInPipeline(ThreadID tid)
 977 {
 978     //Squash all instructions in each stage
 979     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 980         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
 981     }
 982 }
 983
 984 PipelineStage*
 985 InOrderCPU::getPipeStage(int stage_num)
 986 {
 987     return pipelineStage[stage_num];
 988 }
 989
 990 uint64_t
 991 InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
 992 {
 993     return intRegs[tid][reg_idx];
 994 }
 995
 996 FloatReg
 997 InOrderCPU::readFloatReg(int reg_idx, ThreadID tid)
 998 {
 999     return floatRegs.f[tid][reg_idx];
1000 }
1001
1002 FloatRegBits
1003 InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
1004 {;
1005     return floatRegs.i[tid][reg_idx];
1006 }
1007
1008 void
1009 InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
1010 {
1011     intRegs[tid][reg_idx] = val;
1012 }
1013
1014
1015 void
1016 InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid)
1017 {
1018     floatRegs.f[tid][reg_idx] = val;
1019 }
1020
1021
1022 void
1023 InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid)
1024 {
1025     floatRegs.i[tid][reg_idx] = val;
1026 }
1027
1028 uint64_t
1029 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1030 {
1031     // If Default value is set, then retrieve target thread
1032     if (tid == InvalidThreadID) {
1033         tid = TheISA::getTargetThread(tcBase(tid));
1034     }
1035
1036     if (reg_idx < FP_Base_DepTag) {
1037         // Integer Register File
1038         return readIntReg(reg_idx, tid);
1039     } else if (reg_idx < Ctrl_Base_DepTag) {
1040         // Float Register File
1041         reg_idx -= FP_Base_DepTag;
1042         return readFloatRegBits(reg_idx, tid);
1043     } else {
1044         reg_idx -= Ctrl_Base_DepTag;
1045         return readMiscReg(reg_idx, tid);  // Misc. Register File
1046     }
1047 }
1048 void
1049 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1050                               ThreadID tid)
1051 {
1052     // If Default value is set, then retrieve target thread
1053     if (tid == InvalidThreadID) {
1054         tid = TheISA::getTargetThread(tcBase(tid));
1055     }
1056
1057     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1058         setIntReg(reg_idx, val, tid);
1059     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1060         reg_idx -= FP_Base_DepTag;
1061         setFloatRegBits(reg_idx, val, tid);
1062     } else {
1063         reg_idx -= Ctrl_Base_DepTag;
1064         setMiscReg(reg_idx, val, tid); // Misc. Register File
1065     }
1066 }
1067
1068 MiscReg
1069 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1070 {
1071     return isa[tid].readMiscRegNoEffect(misc_reg);
1072 }
1073
1074 MiscReg
1075 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1076 {
1077     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1078 }
1079
1080 void
1081 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1082 {
1083     isa[tid].setMiscRegNoEffect(misc_reg, val);
1084 }
1085
1086 void
1087 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1088 {
1089     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1090 }
1091
1092
1093 InOrderCPU::ListIt
1094 InOrderCPU::addInst(DynInstPtr &inst)
1095 {
1096     ThreadID tid = inst->readTid();
1097
1098     instList[tid].push_back(inst);
1099
1100     return --(instList[tid].end());
1101 }
1102
1103 void
1104 InOrderCPU::updateContextSwitchStats()
1105 {
1106     // Set Average Stat Here, then reset to 0
1107     instsPerCtxtSwitch = instsPerSwitch;
1108     instsPerSwitch = 0;
1109 }
1110
1111
1112 void
1113 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1114 {
1115     // Set the CPU's PCs - This contributes to the precise state of the CPU
1116     // which can be used when restoring a thread to the CPU after after any
1117     // type of context switching activity (fork, exception, etc.)
1118     pcState(inst->pcState(), tid);
1119
1120     if (inst->isControl()) {
1121         thread[tid]->lastGradIsBranch = true;
1122         thread[tid]->lastBranchPC = inst->pcState();
1123         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1124     } else {
1125         thread[tid]->lastGradIsBranch = false;
1126     }
1127
1128
1129     // Finalize Trace Data For Instruction
1130     if (inst->traceData) {
1131         //inst->traceData->setCycle(curTick);
1132         inst->traceData->setFetchSeq(inst->seqNum);
1133         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1134         inst->traceData->dump();
1135         delete inst->traceData;
1136         inst->traceData = NULL;
1137     }
1138
1139     // Increment active thread's instruction count
1140     instsPerSwitch++;
1141
1142     // Increment thread-state's instruction count
1143     thread[tid]->numInst++;
1144
1145     // Increment thread-state's instruction stats
1146     thread[tid]->numInsts++;
1147
1148     // Count committed insts per thread stats
1149     committedInsts[tid]++;
1150
1151     // Count total insts committed stat
1152     totalCommittedInsts++;
1153
1154     // Count SMT-committed insts per thread stat
1155     if (numActiveThreads() > 1) {
1156         smtCommittedInsts[tid]++;
1157     }
1158
1159     // Instruction-Mix Stats
1160     if (inst->isLoad()) {
1161         comLoads++;
1162     } else if (inst->isStore()) {
1163         comStores++;
1164     } else if (inst->isControl()) {
1165         comBranches++;
1166     } else if (inst->isNop()) {
1167         comNops++;
1168     } else if (inst->isNonSpeculative()) {
1169         comNonSpec++;
1170     } else if (inst->isInteger()) {
1171         comInts++;
1172     } else if (inst->isFloating()) {
1173         comFloats++;
1174     }
1175
1176     // Check for instruction-count-based events.
1177     comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1178
1179     // Broadcast to other resources an instruction
1180     // has been completed
1181     resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
1182                            0, 0, tid);
1183
1184     // Finally, remove instruction from CPU
1185     removeInst(inst);
1186 }
1187
1188 // currently unused function, but substitute repetitive code w/this function
1189 // call
1190 void
1191 InOrderCPU::addToRemoveList(DynInstPtr &inst)
1192 {
1193     removeInstsThisCycle = true;
1194     if (!inst->isRemoveList()) {
1195         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1196                 "[sn:%lli] to remove list\n",
1197                 inst->threadNumber, inst->pcState(), inst->seqNum);
1198         inst->setRemoveList();
1199         removeList.push(inst->getInstListIt());
1200     }  else {
1201         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1202                 "[sn:%lli], already remove list\n",
1203                 inst->threadNumber, inst->pcState(), inst->seqNum);
1204     }
1205
1206 }
1207
1208 void
1209 InOrderCPU::removeInst(DynInstPtr &inst)
1210 {
1211     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1212             "[sn:%lli]\n",
1213             inst->threadNumber, inst->pcState(), inst->seqNum);
1214
1215     removeInstsThisCycle = true;
1216
1217     // Remove the instruction.
1218     if (!inst->isRemoveList()) {
1219         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1220                 "[sn:%lli] to remove list\n",
1221                 inst->threadNumber, inst->pcState(), inst->seqNum);
1222         inst->setRemoveList();
1223         removeList.push(inst->getInstListIt());
1224     } else {
1225         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1226                 "[sn:%lli], already on remove list\n",
1227                 inst->threadNumber, inst->pcState(), inst->seqNum);
1228     }
1229
1230 }
1231
1232 void
1233 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1234 {
1235     //assert(!instList[tid].empty());
1236
1237     removeInstsThisCycle = true;
1238
1239     ListIt inst_iter = instList[tid].end();
1240
1241     inst_iter--;
1242
1243     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1244             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1245             tid, seq_num, (*inst_iter)->seqNum);
1246
1247     while ((*inst_iter)->seqNum > seq_num) {
1248
1249         bool break_loop = (inst_iter == instList[tid].begin());
1250
1251         squashInstIt(inst_iter, tid);
1252
1253         inst_iter--;
1254
1255         if (break_loop)
1256             break;
1257     }
1258 }
1259
1260
1261 inline void
1262 InOrderCPU::squashInstIt(const ListIt &instIt, ThreadID tid)
1263 {
1264     if ((*instIt)->threadNumber == tid) {
1265         DPRINTF(InOrderCPU, "Squashing instruction, "
1266                 "[tid:%i] [sn:%lli] PC %s\n",
1267                 (*instIt)->threadNumber,
1268                 (*instIt)->seqNum,
1269                 (*instIt)->pcState());
1270
1271         (*instIt)->setSquashed();
1272
1273         if (!(*instIt)->isRemoveList()) {
1274             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1275                     "[sn:%lli] to remove list\n",
1276                     (*instIt)->threadNumber, (*instIt)->pcState(),
1277                     (*instIt)->seqNum);
1278             (*instIt)->setRemoveList();
1279             removeList.push(instIt);
1280         } else {
1281             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1282                     " PC %s [sn:%lli], already on remove list\n",
1283                     (*instIt)->threadNumber, (*instIt)->pcState(),
1284                     (*instIt)->seqNum);
1285         }
1286
1287     }
1288
1289 }
1290
1291
1292 void
1293 InOrderCPU::cleanUpRemovedInsts()
1294 {
1295     while (!removeList.empty()) {
1296         DPRINTF(InOrderCPU, "Removing instruction, "
1297                 "[tid:%i] [sn:%lli] PC %s\n",
1298                 (*removeList.front())->threadNumber,
1299                 (*removeList.front())->seqNum,
1300                (*removeList.front())->pcState());
1301
1302         DynInstPtr inst = *removeList.front();
1303         ThreadID tid = inst->threadNumber;
1304
1305         // Make Sure Resource Schedule Is Emptied Out
1306         ThePipeline::ResSchedule *inst_sched = &inst->resSched;
1307         while (!inst_sched->empty()) {
1308             ScheduleEntry* sch_entry = inst_sched->top();
1309             inst_sched->pop();
1310             delete sch_entry;
1311         }
1312
1313         // Remove From Register Dependency Map, If Necessary
1314         archRegDepMap[(*removeList.front())->threadNumber].
1315             remove((*removeList.front()));
1316
1317
1318         // Clear if Non-Speculative
1319         if (inst->staticInst &&
1320               inst->seqNum == nonSpecSeqNum[tid] &&
1321                 nonSpecInstActive[tid] == true) {
1322             nonSpecInstActive[tid] = false;
1323         }
1324
1325         instList[tid].erase(removeList.front());
1326
1327         removeList.pop();
1328     }
1329
1330     removeInstsThisCycle = false;
1331 }
1332
1333 void
1334 InOrderCPU::cleanUpRemovedReqs()
1335 {
1336     while (!reqRemoveList.empty()) {
1337         ResourceRequest *res_req = reqRemoveList.front();
1338
1339         DPRINTF(RefCount, "[tid:%i] [sn:%lli]: Removing Request "
1340                 "[stage_num:%i] [res:%s] [slot:%i] [completed:%i].\n",
1341                 res_req->inst->threadNumber,
1342                 res_req->inst->seqNum,
1343                 res_req->getStageNum(),
1344                 res_req->res->name(),
1345                 (res_req->isCompleted()) ?
1346                 res_req->getComplSlot() : res_req->getSlot(),
1347                 res_req->isCompleted());
1348
1349         reqRemoveList.pop();
1350
1351         delete res_req;
1352     }
1353 }
1354
1355 void
1356 InOrderCPU::cleanUpRemovedEvents()
1357 {
1358     while (!cpuEventRemoveList.empty()) {
1359         Event *cpu_event = cpuEventRemoveList.front();
1360         cpuEventRemoveList.pop();
1361         delete cpu_event;
1362     }
1363 }
1364
1365
1366 void
1367 InOrderCPU::dumpInsts()
1368 {
1369     int num = 0;
1370
1371     ListIt inst_list_it = instList[0].begin();
1372
1373     cprintf("Dumping Instruction List\n");
1374
1375     while (inst_list_it != instList[0].end()) {
1376         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1377                 "Squashed:%i\n\n",
1378                 num, (*inst_list_it)->pcState(),
1379                 (*inst_list_it)->threadNumber,
1380                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1381                 (*inst_list_it)->isSquashed());
1382         inst_list_it++;
1383         ++num;
1384     }
1385 }
1386
1387 void
1388 InOrderCPU::wakeCPU()
1389 {
1390     if (/*activityRec.active() || */tickEvent.scheduled()) {
1391         DPRINTF(Activity, "CPU already running.\n");
1392         return;
1393     }
1394
1395     DPRINTF(Activity, "Waking up CPU\n");
1396
1397     Tick extra_cycles = tickToCycles((curTick - 1) - lastRunningCycle);
1398
1399     idleCycles += extra_cycles;
1400     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1401         pipelineStage[stage_num]->idleCycles += extra_cycles;
1402     }
1403
1404     numCycles += extra_cycles;
1405
1406     mainEventQueue.schedule(&tickEvent, nextCycle(curTick));
1407 }
1408
1409 #if FULL_SYSTEM
1410
1411 void
1412 InOrderCPU::wakeup()
1413 {
1414     if (this->thread[0]->status() != ThreadContext::Suspended)
1415         return;
1416
1417     this->wakeCPU();
1418
1419     DPRINTF(Quiesce, "Suspended Processor woken\n");
1420     this->threadContexts[0]->activate();
1421 }
1422 #endif
1423
1424 #if !FULL_SYSTEM
1425 void
1426 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1427 {
1428     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1429
1430     DPRINTF(Activity,"Activity: syscall() called.\n");
1431
1432     // Temporarily increase this by one to account for the syscall
1433     // instruction.
1434     ++(this->thread[tid]->funcExeInst);
1435
1436     // Execute the actual syscall.
1437     this->thread[tid]->syscall(callnum);
1438
1439     // Decrease funcExeInst by one as the normal commit will handle
1440     // incrementing it.
1441     --(this->thread[tid]->funcExeInst);
1442
1443     // Clear Non-Speculative Block Variable
1444     nonSpecInstActive[tid] = false;
1445 }
1446 #endif
1447
1448 void
1449 InOrderCPU::prefetch(DynInstPtr inst)
1450 {
1451     Resource *mem_res = resPool->getResource(dataPortIdx);
1452     return mem_res->prefetch(inst);
1453 }
1454
1455 void
1456 InOrderCPU::writeHint(DynInstPtr inst)
1457 {
1458     Resource *mem_res = resPool->getResource(dataPortIdx);
1459     return mem_res->writeHint(inst);
1460 }
1461
1462
1463 TheISA::TLB*
1464 InOrderCPU::getITBPtr()
1465 {
1466     CacheUnit *itb_res =
1467         dynamic_cast<CacheUnit*>(resPool->getResource(fetchPortIdx));
1468     return itb_res->tlb();
1469 }
1470
1471
1472 TheISA::TLB*
1473 InOrderCPU::getDTBPtr()
1474 {
1475     CacheUnit *dtb_res =
1476         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1477     return dtb_res->tlb();
1478 }
1479
1480 Fault
1481 InOrderCPU::read(DynInstPtr inst, Addr addr,
1482                  uint8_t *data, unsigned size, unsigned flags)
1483 {
1484     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1485     //       you want to run w/out caches?
1486     CacheUnit *cache_res =
1487         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1488
1489     return cache_res->read(inst, addr, data, size, flags);
1490 }
1491
1492 Fault
1493 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1494                   Addr addr, unsigned flags, uint64_t *write_res)
1495 {
1496     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1497     //       you want to run w/out caches?
1498     CacheUnit *cache_res =
1499         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1500     return cache_res->write(inst, data, size, addr, flags, write_res);
1501 }