src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007 MIPS Technologies, Inc.
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Korey Sewell
  41  *
  42  */
  43
  44 #include <algorithm>
  45
  46 #include "arch/utility.hh"
  47 #include "base/bigint.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/inorder/resources/cache_unit.hh"
  50 #include "cpu/inorder/resources/resource_list.hh"
  51 #include "cpu/inorder/cpu.hh"
  52 #include "cpu/inorder/first_stage.hh"
  53 #include "cpu/inorder/inorder_dyn_inst.hh"
  54 #include "cpu/inorder/pipeline_traits.hh"
  55 #include "cpu/inorder/resource_pool.hh"
  56 #include "cpu/inorder/thread_context.hh"
  57 #include "cpu/inorder/thread_state.hh"
  58 #include "cpu/activity.hh"
  59 #include "cpu/base.hh"
  60 #include "cpu/exetrace.hh"
  61 #include "cpu/quiesce_event.hh"
  62 #include "cpu/simple_thread.hh"
  63 #include "cpu/thread_context.hh"
  64 #include "debug/Activity.hh"
  65 #include "debug/InOrderCPU.hh"
  66 #include "debug/InOrderCachePort.hh"
  67 #include "debug/Interrupt.hh"
  68 #include "debug/Quiesce.hh"
  69 #include "debug/RefCount.hh"
  70 #include "debug/SkedCache.hh"
  71 #include "params/InOrderCPU.hh"
  72 #include "sim/full_system.hh"
  73 #include "sim/process.hh"
  74 #include "sim/stat_control.hh"
  75 #include "sim/system.hh"
  76
  77 #if THE_ISA == ALPHA_ISA
  78 #include "arch/alpha/osfpal.hh"
  79 #endif
  80
  81 using namespace std;
  82 using namespace TheISA;
  83 using namespace ThePipeline;
  84
  85 InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit,
  86                                  const std::string& name) :
  87     CpuPort(_cacheUnit->name() + name, _cacheUnit->cpu),
  88     cacheUnit(_cacheUnit)
  89 { }
  90
  91 bool
  92 InOrderCPU::CachePort::recvTimingResp(Packet *pkt)
  93 {
  94     if (pkt->isError())
  95         DPRINTF(InOrderCachePort, "Got error packet back for address: %x\n",
  96                 pkt->getAddr());
  97     else
  98         cacheUnit->processCacheCompletion(pkt);
  99
 100     return true;
 101 }
 102
 103 void
 104 InOrderCPU::CachePort::recvRetry()
 105 {
 106     cacheUnit->recvRetry();
 107 }
 108
 109 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
 110   : Event(CPU_Tick_Pri), cpu(c)
 111 { }
 112
 113
 114 void
 115 InOrderCPU::TickEvent::process()
 116 {
 117     cpu->tick();
 118 }
 119
 120
 121 const char *
 122 InOrderCPU::TickEvent::description() const
 123 {
 124     return "InOrderCPU tick event";
 125 }
 126
 127 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
 128                                Fault fault, ThreadID _tid, DynInstPtr inst,
 129                                CPUEventPri event_pri)
 130     : Event(event_pri), cpu(_cpu)
 131 {
 132     setEvent(e_type, fault, _tid, inst);
 133 }
 134
 135
 136 std::string InOrderCPU::eventNames[NumCPUEvents] =
 137 {
 138     "ActivateThread",
 139     "ActivateNextReadyThread",
 140     "DeactivateThread",
 141     "HaltThread",
 142     "SuspendThread",
 143     "Trap",
 144     "Syscall",
 145     "SquashFromMemStall",
 146     "UpdatePCs"
 147 };
 148
 149 void
 150 InOrderCPU::CPUEvent::process()
 151 {
 152     switch (cpuEventType)
 153     {
 154       case ActivateThread:
 155         cpu->activateThread(tid);
 156         cpu->resPool->activateThread(tid);
 157         break;
 158
 159       case ActivateNextReadyThread:
 160         cpu->activateNextReadyThread();
 161         break;
 162
 163       case DeactivateThread:
 164         cpu->deactivateThread(tid);
 165         cpu->resPool->deactivateThread(tid);
 166         break;
 167
 168       case HaltThread:
 169         cpu->haltThread(tid);
 170         cpu->resPool->deactivateThread(tid);
 171         break;
 172
 173       case SuspendThread:
 174         cpu->suspendThread(tid);
 175         cpu->resPool->suspendThread(tid);
 176         break;
 177
 178       case SquashFromMemStall:
 179         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 180         cpu->resPool->squashDueToMemStall(inst, inst->squashingStage,
 181                                           inst->seqNum, tid);
 182         break;
 183
 184       case Trap:
 185         DPRINTF(InOrderCPU, "Trapping CPU\n");
 186         cpu->trap(fault, tid, inst);
 187         cpu->resPool->trap(fault, tid, inst);
 188         cpu->trapPending[tid] = false;
 189         break;
 190
 191       case Syscall:
 192         cpu->syscall(inst->syscallNum, tid);
 193         cpu->resPool->trap(fault, tid, inst);
 194         break;
 195
 196       default:
 197         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 198     }
 199
 200     cpu->cpuEventRemoveList.push(this);
 201 }
 202
 203
 204
 205 const char *
 206 InOrderCPU::CPUEvent::description() const
 207 {
 208     return "InOrderCPU event";
 209 }
 210
 211 void
 212 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 213 {
 214     assert(!scheduled() || squashed());
 215     cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
 216 }
 217
 218 void
 219 InOrderCPU::CPUEvent::unscheduleEvent()
 220 {
 221     if (scheduled())
 222         squash();
 223 }
 224
 225 InOrderCPU::InOrderCPU(Params *params)
 226     : BaseCPU(params),
 227       cpu_id(params->cpu_id),
 228       coreType("default"),
 229       _status(Idle),
 230       tickEvent(this),
 231       stageWidth(params->stageWidth),
 232       resPool(new ResourcePool(this, params)),
 233       timeBuffer(2 , 2),
 234       dataPort(resPool->getDataUnit(), ".dcache_port"),
 235       instPort(resPool->getInstUnit(), ".icache_port"),
 236       removeInstsThisCycle(false),
 237       activityRec(params->name, NumStages, 10, params->activity),
 238       system(params->system),
 239 #ifdef DEBUG
 240       cpuEventNum(0),
 241       resReqCount(0),
 242 #endif // DEBUG
 243       drainCount(0),
 244       deferRegistration(false/*params->deferRegistration*/),
 245       stageTracing(params->stageTracing),
 246       lastRunningCycle(0),
 247       instsPerSwitch(0)
 248 {
 249     cpu_params = params;
 250
 251     // Resize for Multithreading CPUs
 252     thread.resize(numThreads);
 253
 254     ThreadID active_threads = params->workload.size();
 255     if (FullSystem) {
 256         active_threads = 1;
 257     } else {
 258         active_threads = params->workload.size();
 259
 260         if (active_threads > MaxThreads) {
 261             panic("Workload Size too large. Increase the 'MaxThreads'"
 262                   "in your InOrder implementation or "
 263                   "edit your workload size.");
 264         }
 265
 266
 267         if (active_threads > 1) {
 268             threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 269
 270             if (threadModel == SMT) {
 271                 DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 272             } else if (threadModel == SwitchOnCacheMiss) {
 273                 DPRINTF(InOrderCPU, "Setting Thread Model to "
 274                         "Switch On Cache Miss\n");
 275             }
 276
 277         } else {
 278             threadModel = Single;
 279         }
 280     }
 281
 282     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 283         pc[tid].set(0);
 284         lastCommittedPC[tid].set(0);
 285
 286         if (FullSystem) {
 287             // SMT is not supported in FS mode yet.
 288             assert(numThreads == 1);
 289             thread[tid] = new Thread(this, 0, NULL);
 290         } else {
 291             if (tid < (ThreadID)params->workload.size()) {
 292                 DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 293                         tid, params->workload[tid]->progName());
 294                 thread[tid] =
 295                     new Thread(this, tid, params->workload[tid]);
 296             } else {
 297                 //Allocate Empty thread so M5 can use later
 298                 //when scheduling threads to CPU
 299                 Process* dummy_proc = params->workload[0];
 300                 thread[tid] = new Thread(this, tid, dummy_proc);
 301             }
 302
 303             // Eventually set this with parameters...
 304             asid[tid] = tid;
 305         }
 306
 307         // Setup the TC that will serve as the interface to the threads/CPU.
 308         InOrderThreadContext *tc = new InOrderThreadContext;
 309         tc->cpu = this;
 310         tc->thread = thread[tid];
 311
 312         // Setup quiesce event.
 313         this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
 314
 315         // Give the thread the TC.
 316         thread[tid]->tc = tc;
 317         thread[tid]->setFuncExeInst(0);
 318         globalSeqNum[tid] = 1;
 319
 320         // Add the TC to the CPU's list of TC's.
 321         this->threadContexts.push_back(tc);
 322     }
 323
 324     // Initialize TimeBuffer Stage Queues
 325     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 326         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 327         stageQueue[stNum]->id(stNum);
 328     }
 329
 330
 331     // Set Up Pipeline Stages
 332     for (int stNum=0; stNum < NumStages; stNum++) {
 333         if (stNum == 0)
 334             pipelineStage[stNum] = new FirstStage(params, stNum);
 335         else
 336             pipelineStage[stNum] = new PipelineStage(params, stNum);
 337
 338         pipelineStage[stNum]->setCPU(this);
 339         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 340         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 341
 342         // Take Care of 1st/Nth stages
 343         if (stNum > 0)
 344             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 345         if (stNum < NumStages - 1)
 346             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 347     }
 348
 349     // Initialize thread specific variables
 350     for (ThreadID tid = 0; tid < numThreads; tid++) {
 351         archRegDepMap[tid].setCPU(this);
 352
 353         nonSpecInstActive[tid] = false;
 354         nonSpecSeqNum[tid] = 0;
 355
 356         squashSeqNum[tid] = MaxAddr;
 357         lastSquashCycle[tid] = 0;
 358
 359         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 360         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 361         isa[tid].clear();
 362
 363         // Define dummy instructions and resource requests to be used.
 364         dummyInst[tid] = new InOrderDynInst(this,
 365                                             thread[tid],
 366                                             0,
 367                                             tid,
 368                                             asid[tid]);
 369
 370         dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
 371
 372
 373         if (FullSystem) {
 374             // Use this dummy inst to force squashing behind every instruction
 375             // in pipeline
 376             dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
 377             dummyTrapInst[tid]->seqNum = 0;
 378             dummyTrapInst[tid]->squashSeqNum = 0;
 379             dummyTrapInst[tid]->setTid(tid);
 380         }
 381
 382         trapPending[tid] = false;
 383
 384     }
 385
 386     // InOrderCPU always requires an interrupt controller.
 387     if (!params->defer_registration && !interrupts) {
 388         fatal("InOrderCPU %s has no interrupt controller.\n"
 389               "Ensure createInterruptController() is called.\n", name());
 390     }
 391
 392     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 393     dummyReqInst->setSquashed();
 394     dummyReqInst->resetInstCount();
 395
 396     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 397     dummyBufferInst->setSquashed();
 398     dummyBufferInst->resetInstCount();
 399
 400     endOfSkedIt = skedCache.end();
 401     frontEndSked = createFrontEndSked();
 402     faultSked = createFaultSked();
 403
 404     lastRunningCycle = curTick();
 405
 406     lockAddr = 0;
 407     lockFlag = false;
 408
 409     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 410     scheduleTickEvent(0);
 411 }
 412
 413 InOrderCPU::~InOrderCPU()
 414 {
 415     delete resPool;
 416
 417     SkedCacheIt sked_it = skedCache.begin();
 418     SkedCacheIt sked_end = skedCache.end();
 419
 420     while (sked_it != sked_end) {
 421         delete (*sked_it).second;
 422         sked_it++;
 423     }
 424     skedCache.clear();
 425 }
 426
 427 m5::hash_map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
 428
 429 RSkedPtr
 430 InOrderCPU::createFrontEndSked()
 431 {
 432     RSkedPtr res_sked = new ResourceSked();
 433     int stage_num = 0;
 434     StageScheduler F(res_sked, stage_num++);
 435     StageScheduler D(res_sked, stage_num++);
 436
 437     // FETCH
 438     F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
 439     F.needs(ICache, FetchUnit::InitiateFetch);
 440
 441     // DECODE
 442     D.needs(ICache, FetchUnit::CompleteFetch);
 443     D.needs(Decode, DecodeUnit::DecodeInst);
 444     D.needs(BPred, BranchPredictor::PredictBranch);
 445     D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
 446
 447
 448     DPRINTF(SkedCache, "Resource Sked created for instruction Front End\n");
 449
 450     return res_sked;
 451 }
 452
 453 RSkedPtr
 454 InOrderCPU::createFaultSked()
 455 {
 456     RSkedPtr res_sked = new ResourceSked();
 457     StageScheduler W(res_sked, NumStages - 1);
 458     W.needs(Grad, GraduationUnit::CheckFault);
 459     DPRINTF(SkedCache, "Resource Sked created for instruction Faults\n");
 460     return res_sked;
 461 }
 462
 463 RSkedPtr
 464 InOrderCPU::createBackEndSked(DynInstPtr inst)
 465 {
 466     RSkedPtr res_sked = lookupSked(inst);
 467     if (res_sked != NULL) {
 468         DPRINTF(SkedCache, "Found %s in sked cache.\n",
 469                 inst->instName());
 470         return res_sked;
 471     } else {
 472         res_sked = new ResourceSked();
 473     }
 474
 475     int stage_num = ThePipeline::BackEndStartStage;
 476     StageScheduler X(res_sked, stage_num++);
 477     StageScheduler M(res_sked, stage_num++);
 478     StageScheduler W(res_sked, stage_num++);
 479
 480     if (!inst->staticInst) {
 481         warn_once("Static Instruction Object Not Set. Can't Create"
 482                   " Back End Schedule");
 483         return NULL;
 484     }
 485
 486     // EXECUTE
 487     X.needs(RegManager, UseDefUnit::MarkDestRegs);
 488     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 489         if (!idx || !inst->isStore()) {
 490             X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
 491         }
 492     }
 493
 494     //@todo: schedule non-spec insts to operate on this cycle
 495     // as long as all previous insts are done
 496     if ( inst->isNonSpeculative() ) {
 497         // skip execution of non speculative insts until later
 498     } else if ( inst->isMemRef() ) {
 499         if ( inst->isLoad() ) {
 500             X.needs(AGEN, AGENUnit::GenerateAddr);
 501         }
 502     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 503         X.needs(MDU, MultDivUnit::StartMultDiv);
 504     } else {
 505         X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 506     }
 507
 508     // MEMORY
 509     if (!inst->isNonSpeculative()) {
 510         if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 511             M.needs(MDU, MultDivUnit::EndMultDiv);
 512         }
 513
 514         if ( inst->isLoad() ) {
 515             M.needs(DCache, CacheUnit::InitiateReadData);
 516             if (inst->splitInst)
 517                 M.needs(DCache, CacheUnit::InitSecondSplitRead);
 518         } else if ( inst->isStore() ) {
 519             for (int i = 1; i < inst->numSrcRegs(); i++ ) {
 520                 M.needs(RegManager, UseDefUnit::ReadSrcReg, i);
 521             }
 522             M.needs(AGEN, AGENUnit::GenerateAddr);
 523             M.needs(DCache, CacheUnit::InitiateWriteData);
 524             if (inst->splitInst)
 525                 M.needs(DCache, CacheUnit::InitSecondSplitWrite);
 526         }
 527     }
 528
 529     // WRITEBACK
 530     if (!inst->isNonSpeculative()) {
 531         if ( inst->isLoad() ) {
 532             W.needs(DCache, CacheUnit::CompleteReadData);
 533             if (inst->splitInst)
 534                 W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
 535         } else if ( inst->isStore() ) {
 536             W.needs(DCache, CacheUnit::CompleteWriteData);
 537             if (inst->splitInst)
 538                 W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
 539         }
 540     } else {
 541         // Finally, Execute Speculative Data
 542         if (inst->isMemRef()) {
 543             if (inst->isLoad()) {
 544                 W.needs(AGEN, AGENUnit::GenerateAddr);
 545                 W.needs(DCache, CacheUnit::InitiateReadData);
 546                 if (inst->splitInst)
 547                     W.needs(DCache, CacheUnit::InitSecondSplitRead);
 548                 W.needs(DCache, CacheUnit::CompleteReadData);
 549                 if (inst->splitInst)
 550                     W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
 551             } else if (inst->isStore()) {
 552                 if ( inst->numSrcRegs() >= 2 ) {
 553                     W.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 554                 }
 555                 W.needs(AGEN, AGENUnit::GenerateAddr);
 556                 W.needs(DCache, CacheUnit::InitiateWriteData);
 557                 if (inst->splitInst)
 558                     W.needs(DCache, CacheUnit::InitSecondSplitWrite);
 559                 W.needs(DCache, CacheUnit::CompleteWriteData);
 560                 if (inst->splitInst)
 561                     W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
 562             }
 563         } else {
 564             W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 565         }
 566     }
 567
 568     W.needs(Grad, GraduationUnit::CheckFault);
 569
 570     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 571         W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
 572     }
 573
 574     if (inst->isControl())
 575         W.needs(BPred, BranchPredictor::UpdatePredictor);
 576
 577     W.needs(Grad, GraduationUnit::GraduateInst);
 578
 579     // Insert Back Schedule into our cache of
 580     // resource schedules
 581     addToSkedCache(inst, res_sked);
 582
 583     DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
 584             inst->instName(), inst->getMachInst());
 585     res_sked->print();
 586
 587     return res_sked;
 588 }
 589
 590 void
 591 InOrderCPU::regStats()
 592 {
 593     /* Register the Resource Pool's stats here.*/
 594     resPool->regStats();
 595
 596     /* Register for each Pipeline Stage */
 597     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 598         pipelineStage[stage_num]->regStats();
 599     }
 600
 601     /* Register any of the InOrderCPU's stats here.*/
 602     instsPerCtxtSwitch
 603         .name(name() + ".instsPerContextSwitch")
 604         .desc("Instructions Committed Per Context Switch")
 605         .prereq(instsPerCtxtSwitch);
 606
 607     numCtxtSwitches
 608         .name(name() + ".contextSwitches")
 609         .desc("Number of context switches");
 610
 611     comLoads
 612         .name(name() + ".comLoads")
 613         .desc("Number of Load instructions committed");
 614
 615     comStores
 616         .name(name() + ".comStores")
 617         .desc("Number of Store instructions committed");
 618
 619     comBranches
 620         .name(name() + ".comBranches")
 621         .desc("Number of Branches instructions committed");
 622
 623     comNops
 624         .name(name() + ".comNops")
 625         .desc("Number of Nop instructions committed");
 626
 627     comNonSpec
 628         .name(name() + ".comNonSpec")
 629         .desc("Number of Non-Speculative instructions committed");
 630
 631     comInts
 632         .name(name() + ".comInts")
 633         .desc("Number of Integer instructions committed");
 634
 635     comFloats
 636         .name(name() + ".comFloats")
 637         .desc("Number of Floating Point instructions committed");
 638
 639     timesIdled
 640         .name(name() + ".timesIdled")
 641         .desc("Number of times that the entire CPU went into an idle state and"
 642               " unscheduled itself")
 643         .prereq(timesIdled);
 644
 645     idleCycles
 646         .name(name() + ".idleCycles")
 647         .desc("Number of cycles cpu's stages were not processed");
 648
 649     runCycles
 650         .name(name() + ".runCycles")
 651         .desc("Number of cycles cpu stages are processed.");
 652
 653     activity
 654         .name(name() + ".activity")
 655         .desc("Percentage of cycles cpu is active")
 656         .precision(6);
 657     activity = (runCycles / numCycles) * 100;
 658
 659     threadCycles
 660         .init(numThreads)
 661         .name(name() + ".threadCycles")
 662         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 663
 664     smtCycles
 665         .name(name() + ".smtCycles")
 666         .desc("Total number of cycles that the CPU was in SMT-mode");
 667
 668     committedInsts
 669         .init(numThreads)
 670         .name(name() + ".committedInsts")
 671         .desc("Number of Instructions committed (Per-Thread)");
 672
 673     committedOps
 674         .init(numThreads)
 675         .name(name() + ".committedOps")
 676         .desc("Number of Ops committed (Per-Thread)");
 677
 678     smtCommittedInsts
 679         .init(numThreads)
 680         .name(name() + ".smtCommittedInsts")
 681         .desc("Number of SMT Instructions committed (Per-Thread)");
 682
 683     totalCommittedInsts
 684         .name(name() + ".committedInsts_total")
 685         .desc("Number of Instructions committed (Total)");
 686
 687     cpi
 688         .name(name() + ".cpi")
 689         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 690         .precision(6);
 691     cpi = numCycles / committedInsts;
 692
 693     smtCpi
 694         .name(name() + ".smt_cpi")
 695         .desc("CPI: Total SMT-CPI")
 696         .precision(6);
 697     smtCpi = smtCycles / smtCommittedInsts;
 698
 699     totalCpi
 700         .name(name() + ".cpi_total")
 701         .desc("CPI: Total CPI of All Threads")
 702         .precision(6);
 703     totalCpi = numCycles / totalCommittedInsts;
 704
 705     ipc
 706         .name(name() + ".ipc")
 707         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 708         .precision(6);
 709     ipc =  committedInsts / numCycles;
 710
 711     smtIpc
 712         .name(name() + ".smt_ipc")
 713         .desc("IPC: Total SMT-IPC")
 714         .precision(6);
 715     smtIpc = smtCommittedInsts / smtCycles;
 716
 717     totalIpc
 718         .name(name() + ".ipc_total")
 719         .desc("IPC: Total IPC of All Threads")
 720         .precision(6);
 721         totalIpc =  totalCommittedInsts / numCycles;
 722
 723     BaseCPU::regStats();
 724 }
 725
 726
 727 void
 728 InOrderCPU::tick()
 729 {
 730     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 731
 732     ++numCycles;
 733
 734     checkForInterrupts();
 735
 736     bool pipes_idle = true;
 737     //Tick each of the stages
 738     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 739         pipelineStage[stNum]->tick();
 740
 741         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 742     }
 743
 744     if (pipes_idle)
 745         idleCycles++;
 746     else
 747         runCycles++;
 748
 749     // Now advance the time buffers one tick
 750     timeBuffer.advance();
 751     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 752         stageQueue[sqNum]->advance();
 753     }
 754     activityRec.advance();
 755
 756     // Any squashed events, or insts then remove them now
 757     cleanUpRemovedEvents();
 758     cleanUpRemovedInsts();
 759
 760     // Re-schedule CPU for this cycle
 761     if (!tickEvent.scheduled()) {
 762         if (_status == SwitchedOut) {
 763             // increment stat
 764             lastRunningCycle = curTick();
 765         } else if (!activityRec.active()) {
 766             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 767             lastRunningCycle = curTick();
 768             timesIdled++;
 769         } else {
 770             //Tick next_tick = curTick() + cycles(1);
 771             //tickEvent.schedule(next_tick);
 772             schedule(&tickEvent, nextCycle(curTick() + 1));
 773             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 774                     nextCycle(curTick() + 1));
 775         }
 776     }
 777
 778     tickThreadStats();
 779     updateThreadPriority();
 780 }
 781
 782
 783 void
 784 InOrderCPU::init()
 785 {
 786     BaseCPU::init();
 787
 788     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 789         // Set inSyscall so that the CPU doesn't squash when initially
 790         // setting up registers.
 791         thread[tid]->inSyscall = true;
 792         // Initialise the ThreadContext's memory proxies
 793         thread[tid]->initMemProxies(thread[tid]->getTC());
 794     }
 795
 796     if (FullSystem && !params()->defer_registration) {
 797         for (ThreadID tid = 0; tid < numThreads; tid++) {
 798             ThreadContext *src_tc = threadContexts[tid];
 799             TheISA::initCPU(src_tc, src_tc->contextId());
 800         }
 801     }
 802
 803     // Clear inSyscall.
 804     for (ThreadID tid = 0; tid < numThreads; ++tid)
 805         thread[tid]->inSyscall = false;
 806
 807     // Call Initializiation Routine for Resource Pool
 808     resPool->init();
 809 }
 810
 811 Fault
 812 InOrderCPU::hwrei(ThreadID tid)
 813 {
 814 #if THE_ISA == ALPHA_ISA
 815     // Need to clear the lock flag upon returning from an interrupt.
 816     setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
 817
 818     thread[tid]->kernelStats->hwrei();
 819     // FIXME: XXX check for interrupts? XXX
 820 #endif
 821
 822     return NoFault;
 823 }
 824
 825
 826 bool
 827 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 828 {
 829 #if THE_ISA == ALPHA_ISA
 830     if (this->thread[tid]->kernelStats)
 831         this->thread[tid]->kernelStats->callpal(palFunc,
 832                                                 this->threadContexts[tid]);
 833
 834     switch (palFunc) {
 835       case PAL::halt:
 836         halt();
 837         if (--System::numSystemsRunning == 0)
 838             exitSimLoop("all cpus halted");
 839         break;
 840
 841       case PAL::bpt:
 842       case PAL::bugchk:
 843         if (this->system->breakpoint())
 844             return false;
 845         break;
 846     }
 847 #endif
 848     return true;
 849 }
 850
 851 void
 852 InOrderCPU::checkForInterrupts()
 853 {
 854     for (int i = 0; i < threadContexts.size(); i++) {
 855         ThreadContext *tc = threadContexts[i];
 856
 857         if (interrupts->checkInterrupts(tc)) {
 858             Fault interrupt = interrupts->getInterrupt(tc);
 859
 860             if (interrupt != NoFault) {
 861                 DPRINTF(Interrupt, "Processing Intterupt for [tid:%i].\n",
 862                         tc->threadId());
 863
 864                 ThreadID tid = tc->threadId();
 865                 interrupts->updateIntrInfo(tc);
 866
 867                 // Squash from Last Stage in Pipeline
 868                 unsigned last_stage = NumStages - 1;
 869                 dummyTrapInst[tid]->squashingStage = last_stage;
 870                 pipelineStage[last_stage]->setupSquash(dummyTrapInst[tid],
 871                                                        tid);
 872
 873                 // By default, setupSquash will always squash from stage + 1
 874                 pipelineStage[BackEndStartStage - 1]->setupSquash(dummyTrapInst[tid],
 875                                                                   tid);
 876
 877                 // Schedule Squash Through-out Resource Pool
 878                 resPool->scheduleEvent(
 879                     (InOrderCPU::CPUEventType)ResourcePool::SquashAll,
 880                     dummyTrapInst[tid], 0);
 881
 882                 // Finally, Setup Trap to happen at end of cycle
 883                 trapContext(interrupt, tid, dummyTrapInst[tid]);
 884             }
 885         }
 886     }
 887 }
 888
 889 Fault
 890 InOrderCPU::getInterrupts()
 891 {
 892     // Check if there are any outstanding interrupts
 893     return interrupts->getInterrupt(threadContexts[0]);
 894 }
 895
 896 void
 897 InOrderCPU::processInterrupts(Fault interrupt)
 898 {
 899     // Check for interrupts here.  For now can copy the code that
 900     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 901     // is the one that handles the interrupts.
 902     // @todo: Possibly consolidate the interrupt checking code.
 903     // @todo: Allow other threads to handle interrupts.
 904
 905     assert(interrupt != NoFault);
 906     interrupts->updateIntrInfo(threadContexts[0]);
 907
 908     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 909
 910     // Note: Context ID ok here? Impl. of FS mode needs to revisit this
 911     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 912 }
 913
 914 void
 915 InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 916 {
 917     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 918     trapPending[tid] = true;
 919 }
 920
 921 void
 922 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 923 {
 924     fault->invoke(tcBase(tid), inst->staticInst);
 925     removePipelineStalls(tid);
 926 }
 927
 928 void
 929 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 930 {
 931     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 932 }
 933
 934
 935 void
 936 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 937                                 ThreadID tid)
 938 {
 939     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 940
 941     // Squash all instructions in each stage including
 942     // instruction that caused the squash (seq_num - 1)
 943     // NOTE: The stage bandwidth needs to be cleared so thats why
 944     //       the stalling instruction is squashed as well. The stalled
 945     //       instruction is previously placed in another intermediate buffer
 946     //       while it's stall is being handled.
 947     InstSeqNum squash_seq_num = seq_num - 1;
 948
 949     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 950         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 951     }
 952 }
 953
 954 void
 955 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 956                              ThreadID tid, DynInstPtr inst,
 957                              unsigned delay, CPUEventPri event_pri)
 958 {
 959     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 960                                        event_pri);
 961
 962     Tick sked_tick = nextCycle(curTick() + ticks(delay));
 963     if (delay >= 0) {
 964         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 965                 eventNames[c_event], curTick() + delay, tid);
 966         schedule(cpu_event, sked_tick);
 967     } else {
 968         cpu_event->process();
 969         cpuEventRemoveList.push(cpu_event);
 970     }
 971
 972     // Broadcast event to the Resource Pool
 973     // Need to reset tid just in case this is a dummy instruction
 974     inst->setTid(tid);
 975     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 976 }
 977
 978 bool
 979 InOrderCPU::isThreadActive(ThreadID tid)
 980 {
 981   list<ThreadID>::iterator isActive =
 982       std::find(activeThreads.begin(), activeThreads.end(), tid);
 983
 984     return (isActive != activeThreads.end());
 985 }
 986
 987 bool
 988 InOrderCPU::isThreadReady(ThreadID tid)
 989 {
 990   list<ThreadID>::iterator isReady =
 991       std::find(readyThreads.begin(), readyThreads.end(), tid);
 992
 993     return (isReady != readyThreads.end());
 994 }
 995
 996 bool
 997 InOrderCPU::isThreadSuspended(ThreadID tid)
 998 {
 999   list<ThreadID>::iterator isSuspended =
1000       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
1001
1002     return (isSuspended != suspendedThreads.end());
1003 }
1004
1005 void
1006 InOrderCPU::activateNextReadyThread()
1007 {
1008     if (readyThreads.size() >= 1) {
1009         ThreadID ready_tid = readyThreads.front();
1010
1011         // Activate in Pipeline
1012         activateThread(ready_tid);
1013
1014         // Activate in Resource Pool
1015         resPool->activateThread(ready_tid);
1016
1017         list<ThreadID>::iterator ready_it =
1018             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
1019         readyThreads.erase(ready_it);
1020     } else {
1021         DPRINTF(InOrderCPU,
1022                 "Attempting to activate new thread, but No Ready Threads to"
1023                 "activate.\n");
1024         DPRINTF(InOrderCPU,
1025                 "Unable to switch to next active thread.\n");
1026     }
1027 }
1028
1029 void
1030 InOrderCPU::activateThread(ThreadID tid)
1031 {
1032     if (isThreadSuspended(tid)) {
1033         DPRINTF(InOrderCPU,
1034                 "Removing [tid:%i] from suspended threads list.\n", tid);
1035
1036         list<ThreadID>::iterator susp_it =
1037             std::find(suspendedThreads.begin(), suspendedThreads.end(),
1038                       tid);
1039         suspendedThreads.erase(susp_it);
1040     }
1041
1042     if (threadModel == SwitchOnCacheMiss &&
1043         numActiveThreads() == 1) {
1044         DPRINTF(InOrderCPU,
1045                 "Ignoring activation of [tid:%i], since [tid:%i] is "
1046                 "already running.\n", tid, activeThreadId());
1047
1048         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
1049                 tid);
1050
1051         readyThreads.push_back(tid);
1052
1053     } else if (!isThreadActive(tid)) {
1054         DPRINTF(InOrderCPU,
1055                 "Adding [tid:%i] to active threads list.\n", tid);
1056         activeThreads.push_back(tid);
1057
1058         activateThreadInPipeline(tid);
1059
1060         thread[tid]->lastActivate = curTick();
1061
1062         tcBase(tid)->setStatus(ThreadContext::Active);
1063
1064         wakeCPU();
1065
1066         numCtxtSwitches++;
1067     }
1068 }
1069
1070 void
1071 InOrderCPU::activateThreadInPipeline(ThreadID tid)
1072 {
1073     for (int stNum=0; stNum < NumStages; stNum++) {
1074         pipelineStage[stNum]->activateThread(tid);
1075     }
1076 }
1077
1078 void
1079 InOrderCPU::deactivateContext(ThreadID tid, int delay)
1080 {
1081     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
1082
1083     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
1084
1085     // Be sure to signal that there's some activity so the CPU doesn't
1086     // deschedule itself.
1087     activityRec.activity();
1088
1089     _status = Running;
1090 }
1091
1092 void
1093 InOrderCPU::deactivateThread(ThreadID tid)
1094 {
1095     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
1096
1097     if (isThreadActive(tid)) {
1098         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
1099                 tid);
1100         list<ThreadID>::iterator thread_it =
1101             std::find(activeThreads.begin(), activeThreads.end(), tid);
1102
1103         removePipelineStalls(*thread_it);
1104
1105         activeThreads.erase(thread_it);
1106
1107         // Ideally, this should be triggered from the
1108         // suspendContext/Thread functions
1109         tcBase(tid)->setStatus(ThreadContext::Suspended);
1110     }
1111
1112     assert(!isThreadActive(tid));
1113 }
1114
1115 void
1116 InOrderCPU::removePipelineStalls(ThreadID tid)
1117 {
1118     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
1119             tid);
1120
1121     for (int stNum = 0; stNum < NumStages ; stNum++) {
1122         pipelineStage[stNum]->removeStalls(tid);
1123     }
1124
1125 }
1126
1127 void
1128 InOrderCPU::updateThreadPriority()
1129 {
1130     if (activeThreads.size() > 1)
1131     {
1132         //DEFAULT TO ROUND ROBIN SCHEME
1133         //e.g. Move highest priority to end of thread list
1134         list<ThreadID>::iterator list_begin = activeThreads.begin();
1135
1136         unsigned high_thread = *list_begin;
1137
1138         activeThreads.erase(list_begin);
1139
1140         activeThreads.push_back(high_thread);
1141     }
1142 }
1143
1144 inline void
1145 InOrderCPU::tickThreadStats()
1146 {
1147     /** Keep track of cycles that each thread is active */
1148     list<ThreadID>::iterator thread_it = activeThreads.begin();
1149     while (thread_it != activeThreads.end()) {
1150         threadCycles[*thread_it]++;
1151         thread_it++;
1152     }
1153
1154     // Keep track of cycles where SMT is active
1155     if (activeThreads.size() > 1) {
1156         smtCycles++;
1157     }
1158 }
1159
1160 void
1161 InOrderCPU::activateContext(ThreadID tid, int delay)
1162 {
1163     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
1164
1165
1166     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
1167
1168     // Be sure to signal that there's some activity so the CPU doesn't
1169     // deschedule itself.
1170     activityRec.activity();
1171
1172     _status = Running;
1173 }
1174
1175 void
1176 InOrderCPU::activateNextReadyContext(int delay)
1177 {
1178     DPRINTF(InOrderCPU,"Activating next ready thread\n");
1179
1180     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
1181                      delay, ActivateNextReadyThread_Pri);
1182
1183     // Be sure to signal that there's some activity so the CPU doesn't
1184     // deschedule itself.
1185     activityRec.activity();
1186
1187     _status = Running;
1188 }
1189
1190 void
1191 InOrderCPU::haltContext(ThreadID tid)
1192 {
1193     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
1194
1195     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid]);
1196
1197     activityRec.activity();
1198 }
1199
1200 void
1201 InOrderCPU::haltThread(ThreadID tid)
1202 {
1203     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
1204     deactivateThread(tid);
1205     squashThreadInPipeline(tid);
1206     haltedThreads.push_back(tid);
1207
1208     tcBase(tid)->setStatus(ThreadContext::Halted);
1209
1210     if (threadModel == SwitchOnCacheMiss) {
1211         activateNextReadyContext();
1212     }
1213 }
1214
1215 void
1216 InOrderCPU::suspendContext(ThreadID tid)
1217 {
1218     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid]);
1219 }
1220
1221 void
1222 InOrderCPU::suspendThread(ThreadID tid)
1223 {
1224     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
1225             tid);
1226     deactivateThread(tid);
1227     suspendedThreads.push_back(tid);
1228     thread[tid]->lastSuspend = curTick();
1229
1230     tcBase(tid)->setStatus(ThreadContext::Suspended);
1231 }
1232
1233 void
1234 InOrderCPU::squashThreadInPipeline(ThreadID tid)
1235 {
1236     //Squash all instructions in each stage
1237     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
1238         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
1239     }
1240 }
1241
1242 PipelineStage*
1243 InOrderCPU::getPipeStage(int stage_num)
1244 {
1245     return pipelineStage[stage_num];
1246 }
1247
1248
1249 RegIndex
1250 InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
1251 {
1252     if (reg_idx < FP_Base_DepTag) {
1253         reg_type = IntType;
1254         return isa[tid].flattenIntIndex(reg_idx);
1255     } else if (reg_idx < Ctrl_Base_DepTag) {
1256         reg_type = FloatType;
1257         reg_idx -= FP_Base_DepTag;
1258         return isa[tid].flattenFloatIndex(reg_idx);
1259     } else {
1260         reg_type = MiscType;
1261         return reg_idx - TheISA::Ctrl_Base_DepTag;
1262     }
1263 }
1264
1265 uint64_t
1266 InOrderCPU::readIntReg(RegIndex reg_idx, ThreadID tid)
1267 {
1268     DPRINTF(IntRegs, "[tid:%i]: Reading Int. Reg %i as %x\n",
1269             tid, reg_idx, intRegs[tid][reg_idx]);
1270
1271     return intRegs[tid][reg_idx];
1272 }
1273
1274 FloatReg
1275 InOrderCPU::readFloatReg(RegIndex reg_idx, ThreadID tid)
1276 {
1277     DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1278             tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
1279
1280     return floatRegs.f[tid][reg_idx];
1281 }
1282
1283 FloatRegBits
1284 InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
1285 {
1286     DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1287             tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
1288
1289     return floatRegs.i[tid][reg_idx];
1290 }
1291
1292 void
1293 InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid)
1294 {
1295     if (reg_idx == TheISA::ZeroReg) {
1296         DPRINTF(IntRegs, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1297                 "(Int. Reg %i) to %x\n", tid, reg_idx, val);
1298         return;
1299     } else {
1300         DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
1301                 tid, reg_idx, val);
1302
1303         intRegs[tid][reg_idx] = val;
1304     }
1305 }
1306
1307
1308 void
1309 InOrderCPU::setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid)
1310 {
1311     floatRegs.f[tid][reg_idx] = val;
1312     DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
1313             "%x, %08f\n",
1314             tid, reg_idx,
1315             floatRegs.i[tid][reg_idx],
1316             floatRegs.f[tid][reg_idx]);
1317 }
1318
1319
1320 void
1321 InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid)
1322 {
1323     floatRegs.i[tid][reg_idx] = val;
1324     DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
1325             "%x, %08f\n",
1326             tid, reg_idx,
1327             floatRegs.i[tid][reg_idx],
1328             floatRegs.f[tid][reg_idx]);
1329 }
1330
1331 uint64_t
1332 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1333 {
1334     // If Default value is set, then retrieve target thread
1335     if (tid == InvalidThreadID) {
1336         tid = TheISA::getTargetThread(tcBase(tid));
1337     }
1338
1339     if (reg_idx < FP_Base_DepTag) {
1340         // Integer Register File
1341         return readIntReg(reg_idx, tid);
1342     } else if (reg_idx < Ctrl_Base_DepTag) {
1343         // Float Register File
1344         reg_idx -= FP_Base_DepTag;
1345         return readFloatRegBits(reg_idx, tid);
1346     } else {
1347         reg_idx -= Ctrl_Base_DepTag;
1348         return readMiscReg(reg_idx, tid);  // Misc. Register File
1349     }
1350 }
1351 void
1352 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1353                               ThreadID tid)
1354 {
1355     // If Default value is set, then retrieve target thread
1356     if (tid == InvalidThreadID) {
1357         tid = TheISA::getTargetThread(tcBase(tid));
1358     }
1359
1360     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1361         setIntReg(reg_idx, val, tid);
1362     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1363         reg_idx -= FP_Base_DepTag;
1364         setFloatRegBits(reg_idx, val, tid);
1365     } else {
1366         reg_idx -= Ctrl_Base_DepTag;
1367         setMiscReg(reg_idx, val, tid); // Misc. Register File
1368     }
1369 }
1370
1371 MiscReg
1372 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1373 {
1374     return isa[tid].readMiscRegNoEffect(misc_reg);
1375 }
1376
1377 MiscReg
1378 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1379 {
1380     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1381 }
1382
1383 void
1384 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1385 {
1386     isa[tid].setMiscRegNoEffect(misc_reg, val);
1387 }
1388
1389 void
1390 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1391 {
1392     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1393 }
1394
1395
1396 InOrderCPU::ListIt
1397 InOrderCPU::addInst(DynInstPtr inst)
1398 {
1399     ThreadID tid = inst->readTid();
1400
1401     instList[tid].push_back(inst);
1402
1403     return --(instList[tid].end());
1404 }
1405
1406 InOrderCPU::ListIt
1407 InOrderCPU::findInst(InstSeqNum seq_num, ThreadID tid)
1408 {
1409     ListIt it = instList[tid].begin();
1410     ListIt end = instList[tid].end();
1411
1412     while (it != end) {
1413         if ((*it)->seqNum == seq_num)
1414             return it;
1415         else if ((*it)->seqNum > seq_num)
1416             break;
1417
1418         it++;
1419     }
1420
1421     return instList[tid].end();
1422 }
1423
1424 void
1425 InOrderCPU::updateContextSwitchStats()
1426 {
1427     // Set Average Stat Here, then reset to 0
1428     instsPerCtxtSwitch = instsPerSwitch;
1429     instsPerSwitch = 0;
1430 }
1431
1432
1433 void
1434 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1435 {
1436     // Set the nextPC to be fetched if this is the last instruction
1437     // committed
1438     // ========
1439     // This contributes to the precise state of the CPU
1440     // which can be used when restoring a thread to the CPU after after any
1441     // type of context switching activity (fork, exception, etc.)
1442     TheISA::PCState comm_pc = inst->pcState();
1443     lastCommittedPC[tid] = comm_pc;
1444     TheISA::advancePC(comm_pc, inst->staticInst);
1445     pcState(comm_pc, tid);
1446
1447     //@todo: may be unnecessary with new-ISA-specific branch handling code
1448     if (inst->isControl()) {
1449         thread[tid]->lastGradIsBranch = true;
1450         thread[tid]->lastBranchPC = inst->pcState();
1451         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1452     } else {
1453         thread[tid]->lastGradIsBranch = false;
1454     }
1455
1456
1457     // Finalize Trace Data For Instruction
1458     if (inst->traceData) {
1459         //inst->traceData->setCycle(curTick());
1460         inst->traceData->setFetchSeq(inst->seqNum);
1461         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1462         inst->traceData->dump();
1463         delete inst->traceData;
1464         inst->traceData = NULL;
1465     }
1466
1467     // Increment active thread's instruction count
1468     instsPerSwitch++;
1469
1470     // Increment thread-state's instruction count
1471     thread[tid]->numInst++;
1472     thread[tid]->numOp++;
1473
1474     // Increment thread-state's instruction stats
1475     thread[tid]->numInsts++;
1476     thread[tid]->numOps++;
1477
1478     // Count committed insts per thread stats
1479     if (!inst->isMicroop() || inst->isLastMicroop()) {
1480         committedInsts[tid]++;
1481
1482         // Count total insts committed stat
1483         totalCommittedInsts++;
1484     }
1485
1486     committedOps[tid]++;
1487
1488     // Count SMT-committed insts per thread stat
1489     if (numActiveThreads() > 1) {
1490         if (!inst->isMicroop() || inst->isLastMicroop())
1491             smtCommittedInsts[tid]++;
1492     }
1493
1494     // Instruction-Mix Stats
1495     if (inst->isLoad()) {
1496         comLoads++;
1497     } else if (inst->isStore()) {
1498         comStores++;
1499     } else if (inst->isControl()) {
1500         comBranches++;
1501     } else if (inst->isNop()) {
1502         comNops++;
1503     } else if (inst->isNonSpeculative()) {
1504         comNonSpec++;
1505     } else if (inst->isInteger()) {
1506         comInts++;
1507     } else if (inst->isFloating()) {
1508         comFloats++;
1509     }
1510
1511     // Check for instruction-count-based events.
1512     comInstEventQueue[tid]->serviceEvents(thread[tid]->numOp);
1513
1514     // Finally, remove instruction from CPU
1515     removeInst(inst);
1516 }
1517
1518 // currently unused function, but substitute repetitive code w/this function
1519 // call
1520 void
1521 InOrderCPU::addToRemoveList(DynInstPtr inst)
1522 {
1523     removeInstsThisCycle = true;
1524     if (!inst->isRemoveList()) {
1525         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1526                 "[sn:%lli] to remove list\n",
1527                 inst->threadNumber, inst->pcState(), inst->seqNum);
1528         inst->setRemoveList();
1529         removeList.push(inst->getInstListIt());
1530     }  else {
1531         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1532                 "[sn:%lli], already remove list\n",
1533                 inst->threadNumber, inst->pcState(), inst->seqNum);
1534     }
1535
1536 }
1537
1538 void
1539 InOrderCPU::removeInst(DynInstPtr inst)
1540 {
1541     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1542             "[sn:%lli]\n",
1543             inst->threadNumber, inst->pcState(), inst->seqNum);
1544
1545     removeInstsThisCycle = true;
1546
1547     // Remove the instruction.
1548     if (!inst->isRemoveList()) {
1549         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1550                 "[sn:%lli] to remove list\n",
1551                 inst->threadNumber, inst->pcState(), inst->seqNum);
1552         inst->setRemoveList();
1553         removeList.push(inst->getInstListIt());
1554     } else {
1555         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1556                 "[sn:%lli], already on remove list\n",
1557                 inst->threadNumber, inst->pcState(), inst->seqNum);
1558     }
1559
1560 }
1561
1562 void
1563 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1564 {
1565     //assert(!instList[tid].empty());
1566
1567     removeInstsThisCycle = true;
1568
1569     ListIt inst_iter = instList[tid].end();
1570
1571     inst_iter--;
1572
1573     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1574             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1575             tid, seq_num, (*inst_iter)->seqNum);
1576
1577     while ((*inst_iter)->seqNum > seq_num) {
1578
1579         bool break_loop = (inst_iter == instList[tid].begin());
1580
1581         squashInstIt(inst_iter, tid);
1582
1583         inst_iter--;
1584
1585         if (break_loop)
1586             break;
1587     }
1588 }
1589
1590
1591 inline void
1592 InOrderCPU::squashInstIt(const ListIt inst_it, ThreadID tid)
1593 {
1594     DynInstPtr inst = (*inst_it);
1595     if (inst->threadNumber == tid) {
1596         DPRINTF(InOrderCPU, "Squashing instruction, "
1597                 "[tid:%i] [sn:%lli] PC %s\n",
1598                 inst->threadNumber,
1599                 inst->seqNum,
1600                 inst->pcState());
1601
1602         inst->setSquashed();
1603         archRegDepMap[tid].remove(inst);
1604
1605         if (!inst->isRemoveList()) {
1606             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1607                     "[sn:%lli] to remove list\n",
1608                     inst->threadNumber, inst->pcState(),
1609                     inst->seqNum);
1610             inst->setRemoveList();
1611             removeList.push(inst_it);
1612         } else {
1613             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1614                     " PC %s [sn:%lli], already on remove list\n",
1615                     inst->threadNumber, inst->pcState(),
1616                     inst->seqNum);
1617         }
1618
1619     }
1620
1621 }
1622
1623
1624 void
1625 InOrderCPU::cleanUpRemovedInsts()
1626 {
1627     while (!removeList.empty()) {
1628         DPRINTF(InOrderCPU, "Removing instruction, "
1629                 "[tid:%i] [sn:%lli] PC %s\n",
1630                 (*removeList.front())->threadNumber,
1631                 (*removeList.front())->seqNum,
1632                (*removeList.front())->pcState());
1633
1634         DynInstPtr inst = *removeList.front();
1635         ThreadID tid = inst->threadNumber;
1636
1637         // Remove From Register Dependency Map, If Necessary
1638         // archRegDepMap[tid].remove(inst);
1639
1640         // Clear if Non-Speculative
1641         if (inst->staticInst &&
1642             inst->seqNum == nonSpecSeqNum[tid] &&
1643             nonSpecInstActive[tid] == true) {
1644             nonSpecInstActive[tid] = false;
1645         }
1646
1647         inst->onInstList = false;
1648
1649         instList[tid].erase(removeList.front());
1650
1651         removeList.pop();
1652     }
1653
1654     removeInstsThisCycle = false;
1655 }
1656
1657 void
1658 InOrderCPU::cleanUpRemovedEvents()
1659 {
1660     while (!cpuEventRemoveList.empty()) {
1661         Event *cpu_event = cpuEventRemoveList.front();
1662         cpuEventRemoveList.pop();
1663         delete cpu_event;
1664     }
1665 }
1666
1667
1668 void
1669 InOrderCPU::dumpInsts()
1670 {
1671     int num = 0;
1672
1673     ListIt inst_list_it = instList[0].begin();
1674
1675     cprintf("Dumping Instruction List\n");
1676
1677     while (inst_list_it != instList[0].end()) {
1678         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1679                 "Squashed:%i\n\n",
1680                 num, (*inst_list_it)->pcState(),
1681                 (*inst_list_it)->threadNumber,
1682                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1683                 (*inst_list_it)->isSquashed());
1684         inst_list_it++;
1685         ++num;
1686     }
1687 }
1688
1689 void
1690 InOrderCPU::wakeCPU()
1691 {
1692     if (/*activityRec.active() || */tickEvent.scheduled()) {
1693         DPRINTF(Activity, "CPU already running.\n");
1694         return;
1695     }
1696
1697     DPRINTF(Activity, "Waking up CPU\n");
1698
1699     Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
1700
1701     idleCycles += extra_cycles;
1702     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1703         pipelineStage[stage_num]->idleCycles += extra_cycles;
1704     }
1705
1706     numCycles += extra_cycles;
1707
1708     schedule(&tickEvent, nextCycle(curTick()));
1709 }
1710
1711 // Lots of copied full system code...place into BaseCPU class?
1712 void
1713 InOrderCPU::wakeup()
1714 {
1715     if (thread[0]->status() != ThreadContext::Suspended)
1716         return;
1717
1718     wakeCPU();
1719
1720     DPRINTF(Quiesce, "Suspended Processor woken\n");
1721     threadContexts[0]->activate();
1722 }
1723
1724 void
1725 InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
1726 {
1727     // Syscall must be non-speculative, so squash from last stage
1728     unsigned squash_stage = NumStages - 1;
1729     inst->setSquashInfo(squash_stage);
1730
1731     // Squash In Pipeline Stage
1732     pipelineStage[squash_stage]->setupSquash(inst, tid);
1733
1734     // Schedule Squash Through-out Resource Pool
1735     resPool->scheduleEvent(
1736         (InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
1737     scheduleCpuEvent(Syscall, fault, tid, inst, delay, Syscall_Pri);
1738 }
1739
1740 void
1741 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1742 {
1743     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1744
1745     DPRINTF(Activity,"Activity: syscall() called.\n");
1746
1747     // Temporarily increase this by one to account for the syscall
1748     // instruction.
1749     ++(this->thread[tid]->funcExeInst);
1750
1751     // Execute the actual syscall.
1752     this->thread[tid]->syscall(callnum);
1753
1754     // Decrease funcExeInst by one as the normal commit will handle
1755     // incrementing it.
1756     --(this->thread[tid]->funcExeInst);
1757
1758     // Clear Non-Speculative Block Variable
1759     nonSpecInstActive[tid] = false;
1760 }
1761
1762 TheISA::TLB*
1763 InOrderCPU::getITBPtr()
1764 {
1765     CacheUnit *itb_res = resPool->getInstUnit();
1766     return itb_res->tlb();
1767 }
1768
1769
1770 TheISA::TLB*
1771 InOrderCPU::getDTBPtr()
1772 {
1773     return resPool->getDataUnit()->tlb();
1774 }
1775
1776 TheISA::Decoder *
1777 InOrderCPU::getDecoderPtr(unsigned tid)
1778 {
1779     return resPool->getInstUnit()->decoder[tid];
1780 }
1781
1782 Fault
1783 InOrderCPU::read(DynInstPtr inst, Addr addr,
1784                  uint8_t *data, unsigned size, unsigned flags)
1785 {
1786     return resPool->getDataUnit()->read(inst, addr, data, size, flags);
1787 }
1788
1789 Fault
1790 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1791                   Addr addr, unsigned flags, uint64_t *write_res)
1792 {
1793     return resPool->getDataUnit()->write(inst, data, size, addr, flags,
1794                                          write_res);
1795 }