src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2007 MIPS Technologies, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Korey Sewell
  42  *
  43  */
  44
  45 #include <algorithm>
  46
  47 #include "arch/utility.hh"
  48 #include "base/bigint.hh"
  49 #include "config/the_isa.hh"
  50 #include "cpu/inorder/resources/cache_unit.hh"
  51 #include "cpu/inorder/resources/resource_list.hh"
  52 #include "cpu/inorder/cpu.hh"
  53 #include "cpu/inorder/first_stage.hh"
  54 #include "cpu/inorder/inorder_dyn_inst.hh"
  55 #include "cpu/inorder/pipeline_traits.hh"
  56 #include "cpu/inorder/resource_pool.hh"
  57 #include "cpu/inorder/thread_context.hh"
  58 #include "cpu/inorder/thread_state.hh"
  59 #include "cpu/activity.hh"
  60 #include "cpu/base.hh"
  61 #include "cpu/exetrace.hh"
  62 #include "cpu/quiesce_event.hh"
  63 #include "cpu/reg_class.hh"
  64 #include "cpu/simple_thread.hh"
  65 #include "cpu/thread_context.hh"
  66 #include "debug/Activity.hh"
  67 #include "debug/InOrderCPU.hh"
  68 #include "debug/InOrderCachePort.hh"
  69 #include "debug/Interrupt.hh"
  70 #include "debug/Quiesce.hh"
  71 #include "debug/RefCount.hh"
  72 #include "debug/SkedCache.hh"
  73 #include "params/InOrderCPU.hh"
  74 #include "sim/full_system.hh"
  75 #include "sim/process.hh"
  76 #include "sim/stat_control.hh"
  77 #include "sim/system.hh"
  78
  79 #if THE_ISA == ALPHA_ISA
  80 #include "arch/alpha/osfpal.hh"
  81 #endif
  82
  83 using namespace std;
  84 using namespace TheISA;
  85 using namespace ThePipeline;
  86
  87 InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit,
  88                                  const std::string& name) :
  89     MasterPort(_cacheUnit->name() + name, _cacheUnit->cpu),
  90     cacheUnit(_cacheUnit)
  91 { }
  92
  93 bool
  94 InOrderCPU::CachePort::recvTimingResp(Packet *pkt)
  95 {
  96     if (pkt->isError())
  97         DPRINTF(InOrderCachePort, "Got error packet back for address: %x\n",
  98                 pkt->getAddr());
  99     else
 100         cacheUnit->processCacheCompletion(pkt);
 101
 102     return true;
 103 }
 104
 105 void
 106 InOrderCPU::CachePort::recvRetry()
 107 {
 108     cacheUnit->recvRetry();
 109 }
 110
 111 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
 112   : Event(CPU_Tick_Pri), cpu(c)
 113 { }
 114
 115
 116 void
 117 InOrderCPU::TickEvent::process()
 118 {
 119     cpu->tick();
 120 }
 121
 122
 123 const char *
 124 InOrderCPU::TickEvent::description() const
 125 {
 126     return "InOrderCPU tick event";
 127 }
 128
 129 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
 130                                Fault fault, ThreadID _tid, DynInstPtr inst,
 131                                CPUEventPri event_pri)
 132     : Event(event_pri), cpu(_cpu)
 133 {
 134     setEvent(e_type, fault, _tid, inst);
 135 }
 136
 137
 138 std::string InOrderCPU::eventNames[NumCPUEvents] =
 139 {
 140     "ActivateThread",
 141     "ActivateNextReadyThread",
 142     "DeactivateThread",
 143     "HaltThread",
 144     "SuspendThread",
 145     "Trap",
 146     "Syscall",
 147     "SquashFromMemStall",
 148     "UpdatePCs"
 149 };
 150
 151 void
 152 InOrderCPU::CPUEvent::process()
 153 {
 154     switch (cpuEventType)
 155     {
 156       case ActivateThread:
 157         cpu->activateThread(tid);
 158         cpu->resPool->activateThread(tid);
 159         break;
 160
 161       case ActivateNextReadyThread:
 162         cpu->activateNextReadyThread();
 163         break;
 164
 165       case DeactivateThread:
 166         cpu->deactivateThread(tid);
 167         cpu->resPool->deactivateThread(tid);
 168         break;
 169
 170       case HaltThread:
 171         cpu->haltThread(tid);
 172         cpu->resPool->deactivateThread(tid);
 173         break;
 174
 175       case SuspendThread:
 176         cpu->suspendThread(tid);
 177         cpu->resPool->suspendThread(tid);
 178         break;
 179
 180       case SquashFromMemStall:
 181         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 182         cpu->resPool->squashDueToMemStall(inst, inst->squashingStage,
 183                                           inst->seqNum, tid);
 184         break;
 185
 186       case Trap:
 187         DPRINTF(InOrderCPU, "Trapping CPU\n");
 188         cpu->trap(fault, tid, inst);
 189         cpu->resPool->trap(fault, tid, inst);
 190         cpu->trapPending[tid] = false;
 191         break;
 192
 193       case Syscall:
 194         cpu->syscall(inst->syscallNum, tid);
 195         cpu->resPool->trap(fault, tid, inst);
 196         break;
 197
 198       default:
 199         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 200     }
 201
 202     cpu->cpuEventRemoveList.push(this);
 203 }
 204
 205
 206
 207 const char *
 208 InOrderCPU::CPUEvent::description() const
 209 {
 210     return "InOrderCPU event";
 211 }
 212
 213 void
 214 InOrderCPU::CPUEvent::scheduleEvent(Cycles delay)
 215 {
 216     assert(!scheduled() || squashed());
 217     cpu->reschedule(this, cpu->clockEdge(delay), true);
 218 }
 219
 220 void
 221 InOrderCPU::CPUEvent::unscheduleEvent()
 222 {
 223     if (scheduled())
 224         squash();
 225 }
 226
 227 InOrderCPU::InOrderCPU(Params *params)
 228     : BaseCPU(params),
 229       cpu_id(params->cpu_id),
 230       coreType("default"),
 231       _status(Idle),
 232       tickEvent(this),
 233       stageWidth(params->stageWidth),
 234       resPool(new ResourcePool(this, params)),
 235       isa(numThreads, NULL),
 236       timeBuffer(2 , 2),
 237       dataPort(resPool->getDataUnit(), ".dcache_port"),
 238       instPort(resPool->getInstUnit(), ".icache_port"),
 239       removeInstsThisCycle(false),
 240       activityRec(params->name, NumStages, 10, params->activity),
 241       system(params->system),
 242 #ifdef DEBUG
 243       cpuEventNum(0),
 244       resReqCount(0),
 245 #endif // DEBUG
 246       drainCount(0),
 247       stageTracing(params->stageTracing),
 248       lastRunningCycle(0),
 249       instsPerSwitch(0)
 250 {
 251     cpu_params = params;
 252
 253     // Resize for Multithreading CPUs
 254     thread.resize(numThreads);
 255
 256     ThreadID active_threads = params->workload.size();
 257     if (FullSystem) {
 258         active_threads = 1;
 259     } else {
 260         active_threads = params->workload.size();
 261
 262         if (active_threads > MaxThreads) {
 263             panic("Workload Size too large. Increase the 'MaxThreads'"
 264                   "in your InOrder implementation or "
 265                   "edit your workload size.");
 266         }
 267
 268
 269         if (active_threads > 1) {
 270             threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 271
 272             if (threadModel == SMT) {
 273                 DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 274             } else if (threadModel == SwitchOnCacheMiss) {
 275                 DPRINTF(InOrderCPU, "Setting Thread Model to "
 276                         "Switch On Cache Miss\n");
 277             }
 278
 279         } else {
 280             threadModel = Single;
 281         }
 282     }
 283
 284     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 285         isa[tid] = params->isa[tid];
 286         pc[tid].set(0);
 287         lastCommittedPC[tid].set(0);
 288
 289         if (FullSystem) {
 290             // SMT is not supported in FS mode yet.
 291             assert(numThreads == 1);
 292             thread[tid] = new Thread(this, 0, NULL);
 293         } else {
 294             if (tid < (ThreadID)params->workload.size()) {
 295                 DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 296                         tid, params->workload[tid]->progName());
 297                 thread[tid] =
 298                     new Thread(this, tid, params->workload[tid]);
 299             } else {
 300                 //Allocate Empty thread so M5 can use later
 301                 //when scheduling threads to CPU
 302                 Process* dummy_proc = params->workload[0];
 303                 thread[tid] = new Thread(this, tid, dummy_proc);
 304             }
 305
 306             // Eventually set this with parameters...
 307             asid[tid] = tid;
 308         }
 309
 310         // Setup the TC that will serve as the interface to the threads/CPU.
 311         InOrderThreadContext *tc = new InOrderThreadContext;
 312         tc->cpu = this;
 313         tc->thread = thread[tid];
 314
 315         // Setup quiesce event.
 316         this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
 317
 318         // Give the thread the TC.
 319         thread[tid]->tc = tc;
 320         thread[tid]->setFuncExeInst(0);
 321         globalSeqNum[tid] = 1;
 322
 323         // Add the TC to the CPU's list of TC's.
 324         this->threadContexts.push_back(tc);
 325     }
 326
 327     // Initialize TimeBuffer Stage Queues
 328     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 329         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 330         stageQueue[stNum]->id(stNum);
 331     }
 332
 333
 334     // Set Up Pipeline Stages
 335     for (int stNum=0; stNum < NumStages; stNum++) {
 336         if (stNum == 0)
 337             pipelineStage[stNum] = new FirstStage(params, stNum);
 338         else
 339             pipelineStage[stNum] = new PipelineStage(params, stNum);
 340
 341         pipelineStage[stNum]->setCPU(this);
 342         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 343         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 344
 345         // Take Care of 1st/Nth stages
 346         if (stNum > 0)
 347             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 348         if (stNum < NumStages - 1)
 349             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 350     }
 351
 352     // Initialize thread specific variables
 353     for (ThreadID tid = 0; tid < numThreads; tid++) {
 354         archRegDepMap[tid].setCPU(this);
 355
 356         nonSpecInstActive[tid] = false;
 357         nonSpecSeqNum[tid] = 0;
 358
 359         squashSeqNum[tid] = MaxAddr;
 360         lastSquashCycle[tid] = 0;
 361
 362         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 363         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 364         isa[tid]->clear();
 365
 366         // Define dummy instructions and resource requests to be used.
 367         dummyInst[tid] = new InOrderDynInst(this,
 368                                             thread[tid],
 369                                             0,
 370                                             tid,
 371                                             asid[tid]);
 372
 373         dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
 374
 375
 376         if (FullSystem) {
 377             // Use this dummy inst to force squashing behind every instruction
 378             // in pipeline
 379             dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
 380             dummyTrapInst[tid]->seqNum = 0;
 381             dummyTrapInst[tid]->squashSeqNum = 0;
 382             dummyTrapInst[tid]->setTid(tid);
 383         }
 384
 385         trapPending[tid] = false;
 386
 387     }
 388
 389     // InOrderCPU always requires an interrupt controller.
 390     if (!params->switched_out && !interrupts) {
 391         fatal("InOrderCPU %s has no interrupt controller.\n"
 392               "Ensure createInterruptController() is called.\n", name());
 393     }
 394
 395     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 396     dummyReqInst->setSquashed();
 397     dummyReqInst->resetInstCount();
 398
 399     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 400     dummyBufferInst->setSquashed();
 401     dummyBufferInst->resetInstCount();
 402
 403     endOfSkedIt = skedCache.end();
 404     frontEndSked = createFrontEndSked();
 405     faultSked = createFaultSked();
 406
 407     lastRunningCycle = curCycle();
 408
 409     lockAddr = 0;
 410     lockFlag = false;
 411
 412     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 413     scheduleTickEvent(Cycles(0));
 414 }
 415
 416 InOrderCPU::~InOrderCPU()
 417 {
 418     delete resPool;
 419
 420     SkedCacheIt sked_it = skedCache.begin();
 421     SkedCacheIt sked_end = skedCache.end();
 422
 423     while (sked_it != sked_end) {
 424         delete (*sked_it).second;
 425         sked_it++;
 426     }
 427     skedCache.clear();
 428 }
 429
 430 m5::hash_map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
 431
 432 RSkedPtr
 433 InOrderCPU::createFrontEndSked()
 434 {
 435     RSkedPtr res_sked = new ResourceSked();
 436     int stage_num = 0;
 437     StageScheduler F(res_sked, stage_num++);
 438     StageScheduler D(res_sked, stage_num++);
 439
 440     // FETCH
 441     F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
 442     F.needs(ICache, FetchUnit::InitiateFetch);
 443
 444     // DECODE
 445     D.needs(ICache, FetchUnit::CompleteFetch);
 446     D.needs(Decode, DecodeUnit::DecodeInst);
 447     D.needs(BPred, BranchPredictor::PredictBranch);
 448     D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
 449
 450
 451     DPRINTF(SkedCache, "Resource Sked created for instruction Front End\n");
 452
 453     return res_sked;
 454 }
 455
 456 RSkedPtr
 457 InOrderCPU::createFaultSked()
 458 {
 459     RSkedPtr res_sked = new ResourceSked();
 460     StageScheduler W(res_sked, NumStages - 1);
 461     W.needs(Grad, GraduationUnit::CheckFault);
 462     DPRINTF(SkedCache, "Resource Sked created for instruction Faults\n");
 463     return res_sked;
 464 }
 465
 466 RSkedPtr
 467 InOrderCPU::createBackEndSked(DynInstPtr inst)
 468 {
 469     RSkedPtr res_sked = lookupSked(inst);
 470     if (res_sked != NULL) {
 471         DPRINTF(SkedCache, "Found %s in sked cache.\n",
 472                 inst->instName());
 473         return res_sked;
 474     } else {
 475         res_sked = new ResourceSked();
 476     }
 477
 478     int stage_num = ThePipeline::BackEndStartStage;
 479     StageScheduler X(res_sked, stage_num++);
 480     StageScheduler M(res_sked, stage_num++);
 481     StageScheduler W(res_sked, stage_num++);
 482
 483     if (!inst->staticInst) {
 484         warn_once("Static Instruction Object Not Set. Can't Create"
 485                   " Back End Schedule");
 486         return NULL;
 487     }
 488
 489     // EXECUTE
 490     X.needs(RegManager, UseDefUnit::MarkDestRegs);
 491     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 492         if (!idx || !inst->isStore()) {
 493             X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
 494         }
 495     }
 496
 497     //@todo: schedule non-spec insts to operate on this cycle
 498     // as long as all previous insts are done
 499     if ( inst->isNonSpeculative() ) {
 500         // skip execution of non speculative insts until later
 501     } else if ( inst->isMemRef() ) {
 502         if ( inst->isLoad() ) {
 503             X.needs(AGEN, AGENUnit::GenerateAddr);
 504         }
 505     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 506         X.needs(MDU, MultDivUnit::StartMultDiv);
 507     } else {
 508         X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 509     }
 510
 511     // MEMORY
 512     if (!inst->isNonSpeculative()) {
 513         if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 514             M.needs(MDU, MultDivUnit::EndMultDiv);
 515         }
 516
 517         if ( inst->isLoad() ) {
 518             M.needs(DCache, CacheUnit::InitiateReadData);
 519             if (inst->splitInst)
 520                 M.needs(DCache, CacheUnit::InitSecondSplitRead);
 521         } else if ( inst->isStore() ) {
 522             for (int i = 1; i < inst->numSrcRegs(); i++ ) {
 523                 M.needs(RegManager, UseDefUnit::ReadSrcReg, i);
 524             }
 525             M.needs(AGEN, AGENUnit::GenerateAddr);
 526             M.needs(DCache, CacheUnit::InitiateWriteData);
 527             if (inst->splitInst)
 528                 M.needs(DCache, CacheUnit::InitSecondSplitWrite);
 529         }
 530     }
 531
 532     // WRITEBACK
 533     if (!inst->isNonSpeculative()) {
 534         if ( inst->isLoad() ) {
 535             W.needs(DCache, CacheUnit::CompleteReadData);
 536             if (inst->splitInst)
 537                 W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
 538         } else if ( inst->isStore() ) {
 539             W.needs(DCache, CacheUnit::CompleteWriteData);
 540             if (inst->splitInst)
 541                 W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
 542         }
 543     } else {
 544         // Finally, Execute Speculative Data
 545         if (inst->isMemRef()) {
 546             if (inst->isLoad()) {
 547                 W.needs(AGEN, AGENUnit::GenerateAddr);
 548                 W.needs(DCache, CacheUnit::InitiateReadData);
 549                 if (inst->splitInst)
 550                     W.needs(DCache, CacheUnit::InitSecondSplitRead);
 551                 W.needs(DCache, CacheUnit::CompleteReadData);
 552                 if (inst->splitInst)
 553                     W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
 554             } else if (inst->isStore()) {
 555                 if ( inst->numSrcRegs() >= 2 ) {
 556                     W.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 557                 }
 558                 W.needs(AGEN, AGENUnit::GenerateAddr);
 559                 W.needs(DCache, CacheUnit::InitiateWriteData);
 560                 if (inst->splitInst)
 561                     W.needs(DCache, CacheUnit::InitSecondSplitWrite);
 562                 W.needs(DCache, CacheUnit::CompleteWriteData);
 563                 if (inst->splitInst)
 564                     W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
 565             }
 566         } else {
 567             W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 568         }
 569     }
 570
 571     W.needs(Grad, GraduationUnit::CheckFault);
 572
 573     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 574         W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
 575     }
 576
 577     if (inst->isControl())
 578         W.needs(BPred, BranchPredictor::UpdatePredictor);
 579
 580     W.needs(Grad, GraduationUnit::GraduateInst);
 581
 582     // Insert Back Schedule into our cache of
 583     // resource schedules
 584     addToSkedCache(inst, res_sked);
 585
 586     DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
 587             inst->instName(), inst->getMachInst());
 588     res_sked->print();
 589
 590     return res_sked;
 591 }
 592
 593 void
 594 InOrderCPU::regStats()
 595 {
 596     /* Register the Resource Pool's stats here.*/
 597     resPool->regStats();
 598
 599     /* Register for each Pipeline Stage */
 600     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 601         pipelineStage[stage_num]->regStats();
 602     }
 603
 604     /* Register any of the InOrderCPU's stats here.*/
 605     instsPerCtxtSwitch
 606         .name(name() + ".instsPerContextSwitch")
 607         .desc("Instructions Committed Per Context Switch")
 608         .prereq(instsPerCtxtSwitch);
 609
 610     numCtxtSwitches
 611         .name(name() + ".contextSwitches")
 612         .desc("Number of context switches");
 613
 614     comLoads
 615         .name(name() + ".comLoads")
 616         .desc("Number of Load instructions committed");
 617
 618     comStores
 619         .name(name() + ".comStores")
 620         .desc("Number of Store instructions committed");
 621
 622     comBranches
 623         .name(name() + ".comBranches")
 624         .desc("Number of Branches instructions committed");
 625
 626     comNops
 627         .name(name() + ".comNops")
 628         .desc("Number of Nop instructions committed");
 629
 630     comNonSpec
 631         .name(name() + ".comNonSpec")
 632         .desc("Number of Non-Speculative instructions committed");
 633
 634     comInts
 635         .name(name() + ".comInts")
 636         .desc("Number of Integer instructions committed");
 637
 638     comFloats
 639         .name(name() + ".comFloats")
 640         .desc("Number of Floating Point instructions committed");
 641
 642     timesIdled
 643         .name(name() + ".timesIdled")
 644         .desc("Number of times that the entire CPU went into an idle state and"
 645               " unscheduled itself")
 646         .prereq(timesIdled);
 647
 648     idleCycles
 649         .name(name() + ".idleCycles")
 650         .desc("Number of cycles cpu's stages were not processed");
 651
 652     runCycles
 653         .name(name() + ".runCycles")
 654         .desc("Number of cycles cpu stages are processed.");
 655
 656     activity
 657         .name(name() + ".activity")
 658         .desc("Percentage of cycles cpu is active")
 659         .precision(6);
 660     activity = (runCycles / numCycles) * 100;
 661
 662     threadCycles
 663         .init(numThreads)
 664         .name(name() + ".threadCycles")
 665         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 666
 667     smtCycles
 668         .name(name() + ".smtCycles")
 669         .desc("Total number of cycles that the CPU was in SMT-mode");
 670
 671     committedInsts
 672         .init(numThreads)
 673         .name(name() + ".committedInsts")
 674         .desc("Number of Instructions committed (Per-Thread)");
 675
 676     committedOps
 677         .init(numThreads)
 678         .name(name() + ".committedOps")
 679         .desc("Number of Ops committed (Per-Thread)");
 680
 681     smtCommittedInsts
 682         .init(numThreads)
 683         .name(name() + ".smtCommittedInsts")
 684         .desc("Number of SMT Instructions committed (Per-Thread)");
 685
 686     totalCommittedInsts
 687         .name(name() + ".committedInsts_total")
 688         .desc("Number of Instructions committed (Total)");
 689
 690     cpi
 691         .name(name() + ".cpi")
 692         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 693         .precision(6);
 694     cpi = numCycles / committedInsts;
 695
 696     smtCpi
 697         .name(name() + ".smt_cpi")
 698         .desc("CPI: Total SMT-CPI")
 699         .precision(6);
 700     smtCpi = smtCycles / smtCommittedInsts;
 701
 702     totalCpi
 703         .name(name() + ".cpi_total")
 704         .desc("CPI: Total CPI of All Threads")
 705         .precision(6);
 706     totalCpi = numCycles / totalCommittedInsts;
 707
 708     ipc
 709         .name(name() + ".ipc")
 710         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 711         .precision(6);
 712     ipc =  committedInsts / numCycles;
 713
 714     smtIpc
 715         .name(name() + ".smt_ipc")
 716         .desc("IPC: Total SMT-IPC")
 717         .precision(6);
 718     smtIpc = smtCommittedInsts / smtCycles;
 719
 720     totalIpc
 721         .name(name() + ".ipc_total")
 722         .desc("IPC: Total IPC of All Threads")
 723         .precision(6);
 724         totalIpc =  totalCommittedInsts / numCycles;
 725
 726     BaseCPU::regStats();
 727 }
 728
 729
 730 void
 731 InOrderCPU::tick()
 732 {
 733     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 734
 735     ++numCycles;
 736
 737     checkForInterrupts();
 738
 739     bool pipes_idle = true;
 740     //Tick each of the stages
 741     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 742         pipelineStage[stNum]->tick();
 743
 744         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 745     }
 746
 747     if (pipes_idle)
 748         idleCycles++;
 749     else
 750         runCycles++;
 751
 752     // Now advance the time buffers one tick
 753     timeBuffer.advance();
 754     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 755         stageQueue[sqNum]->advance();
 756     }
 757     activityRec.advance();
 758
 759     // Any squashed events, or insts then remove them now
 760     cleanUpRemovedEvents();
 761     cleanUpRemovedInsts();
 762
 763     // Re-schedule CPU for this cycle
 764     if (!tickEvent.scheduled()) {
 765         if (_status == SwitchedOut) {
 766             // increment stat
 767             lastRunningCycle = curCycle();
 768         } else if (!activityRec.active()) {
 769             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 770             lastRunningCycle = curCycle();
 771             timesIdled++;
 772         } else {
 773             //Tick next_tick = curTick() + cycles(1);
 774             //tickEvent.schedule(next_tick);
 775             schedule(&tickEvent, clockEdge(Cycles(1)));
 776             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 777                     clockEdge(Cycles(1)));
 778         }
 779     }
 780
 781     tickThreadStats();
 782     updateThreadPriority();
 783 }
 784
 785
 786 void
 787 InOrderCPU::init()
 788 {
 789     BaseCPU::init();
 790
 791     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 792         // Set noSquashFromTC so that the CPU doesn't squash when initially
 793         // setting up registers.
 794         thread[tid]->noSquashFromTC = true;
 795         // Initialise the ThreadContext's memory proxies
 796         thread[tid]->initMemProxies(thread[tid]->getTC());
 797     }
 798
 799     if (FullSystem && !params()->switched_out) {
 800         for (ThreadID tid = 0; tid < numThreads; tid++) {
 801             ThreadContext *src_tc = threadContexts[tid];
 802             TheISA::initCPU(src_tc, src_tc->contextId());
 803         }
 804     }
 805
 806     // Clear noSquashFromTC.
 807     for (ThreadID tid = 0; tid < numThreads; ++tid)
 808         thread[tid]->noSquashFromTC = false;
 809
 810     // Call Initializiation Routine for Resource Pool
 811     resPool->init();
 812 }
 813
 814 void
 815 InOrderCPU::verifyMemoryMode() const
 816 {
 817     if (!system->isTimingMode()) {
 818         fatal("The in-order CPU requires the memory system to be in "
 819               "'timing' mode.\n");
 820     }
 821 }
 822
 823 Fault
 824 InOrderCPU::hwrei(ThreadID tid)
 825 {
 826 #if THE_ISA == ALPHA_ISA
 827     // Need to clear the lock flag upon returning from an interrupt.
 828     setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
 829
 830     thread[tid]->kernelStats->hwrei();
 831     // FIXME: XXX check for interrupts? XXX
 832 #endif
 833
 834     return NoFault;
 835 }
 836
 837
 838 bool
 839 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 840 {
 841 #if THE_ISA == ALPHA_ISA
 842     if (this->thread[tid]->kernelStats)
 843         this->thread[tid]->kernelStats->callpal(palFunc,
 844                                                 this->threadContexts[tid]);
 845
 846     switch (palFunc) {
 847       case PAL::halt:
 848         halt();
 849         if (--System::numSystemsRunning == 0)
 850             exitSimLoop("all cpus halted");
 851         break;
 852
 853       case PAL::bpt:
 854       case PAL::bugchk:
 855         if (this->system->breakpoint())
 856             return false;
 857         break;
 858     }
 859 #endif
 860     return true;
 861 }
 862
 863 void
 864 InOrderCPU::checkForInterrupts()
 865 {
 866     for (int i = 0; i < threadContexts.size(); i++) {
 867         ThreadContext *tc = threadContexts[i];
 868
 869         if (interrupts->checkInterrupts(tc)) {
 870             Fault interrupt = interrupts->getInterrupt(tc);
 871
 872             if (interrupt != NoFault) {
 873                 DPRINTF(Interrupt, "Processing Intterupt for [tid:%i].\n",
 874                         tc->threadId());
 875
 876                 ThreadID tid = tc->threadId();
 877                 interrupts->updateIntrInfo(tc);
 878
 879                 // Squash from Last Stage in Pipeline
 880                 unsigned last_stage = NumStages - 1;
 881                 dummyTrapInst[tid]->squashingStage = last_stage;
 882                 pipelineStage[last_stage]->setupSquash(dummyTrapInst[tid],
 883                                                        tid);
 884
 885                 // By default, setupSquash will always squash from stage + 1
 886                 pipelineStage[BackEndStartStage - 1]->setupSquash(dummyTrapInst[tid],
 887                                                                   tid);
 888
 889                 // Schedule Squash Through-out Resource Pool
 890                 resPool->scheduleEvent(
 891                     (InOrderCPU::CPUEventType)ResourcePool::SquashAll,
 892                     dummyTrapInst[tid], Cycles(0));
 893
 894                 // Finally, Setup Trap to happen at end of cycle
 895                 trapContext(interrupt, tid, dummyTrapInst[tid]);
 896             }
 897         }
 898     }
 899 }
 900
 901 Fault
 902 InOrderCPU::getInterrupts()
 903 {
 904     // Check if there are any outstanding interrupts
 905     return interrupts->getInterrupt(threadContexts[0]);
 906 }
 907
 908 void
 909 InOrderCPU::processInterrupts(Fault interrupt)
 910 {
 911     // Check for interrupts here.  For now can copy the code that
 912     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 913     // is the one that handles the interrupts.
 914     // @todo: Possibly consolidate the interrupt checking code.
 915     // @todo: Allow other threads to handle interrupts.
 916
 917     assert(interrupt != NoFault);
 918     interrupts->updateIntrInfo(threadContexts[0]);
 919
 920     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 921
 922     // Note: Context ID ok here? Impl. of FS mode needs to revisit this
 923     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 924 }
 925
 926 void
 927 InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
 928                         Cycles delay)
 929 {
 930     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 931     trapPending[tid] = true;
 932 }
 933
 934 void
 935 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 936 {
 937     fault->invoke(tcBase(tid), inst->staticInst);
 938     removePipelineStalls(tid);
 939 }
 940
 941 void
 942 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid,
 943                                Cycles delay)
 944 {
 945     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 946 }
 947
 948
 949 void
 950 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 951                                 ThreadID tid)
 952 {
 953     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 954
 955     // Squash all instructions in each stage including
 956     // instruction that caused the squash (seq_num - 1)
 957     // NOTE: The stage bandwidth needs to be cleared so thats why
 958     //       the stalling instruction is squashed as well. The stalled
 959     //       instruction is previously placed in another intermediate buffer
 960     //       while it's stall is being handled.
 961     InstSeqNum squash_seq_num = seq_num - 1;
 962
 963     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 964         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 965     }
 966 }
 967
 968 void
 969 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 970                              ThreadID tid, DynInstPtr inst,
 971                              Cycles delay, CPUEventPri event_pri)
 972 {
 973     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 974                                        event_pri);
 975
 976     Tick sked_tick = clockEdge(delay);
 977     DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 978             eventNames[c_event], curTick() + delay, tid);
 979     schedule(cpu_event, sked_tick);
 980
 981     // Broadcast event to the Resource Pool
 982     // Need to reset tid just in case this is a dummy instruction
 983     inst->setTid(tid);
 984     // @todo: Is this really right? Should the delay not be passed on?
 985     resPool->scheduleEvent(c_event, inst, Cycles(0), 0, tid);
 986 }
 987
 988 bool
 989 InOrderCPU::isThreadActive(ThreadID tid)
 990 {
 991   list<ThreadID>::iterator isActive =
 992       std::find(activeThreads.begin(), activeThreads.end(), tid);
 993
 994     return (isActive != activeThreads.end());
 995 }
 996
 997 bool
 998 InOrderCPU::isThreadReady(ThreadID tid)
 999 {
1000   list<ThreadID>::iterator isReady =
1001       std::find(readyThreads.begin(), readyThreads.end(), tid);
1002
1003     return (isReady != readyThreads.end());
1004 }
1005
1006 bool
1007 InOrderCPU::isThreadSuspended(ThreadID tid)
1008 {
1009   list<ThreadID>::iterator isSuspended =
1010       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
1011
1012     return (isSuspended != suspendedThreads.end());
1013 }
1014
1015 void
1016 InOrderCPU::activateNextReadyThread()
1017 {
1018     if (readyThreads.size() >= 1) {
1019         ThreadID ready_tid = readyThreads.front();
1020
1021         // Activate in Pipeline
1022         activateThread(ready_tid);
1023
1024         // Activate in Resource Pool
1025         resPool->activateThread(ready_tid);
1026
1027         list<ThreadID>::iterator ready_it =
1028             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
1029         readyThreads.erase(ready_it);
1030     } else {
1031         DPRINTF(InOrderCPU,
1032                 "Attempting to activate new thread, but No Ready Threads to"
1033                 "activate.\n");
1034         DPRINTF(InOrderCPU,
1035                 "Unable to switch to next active thread.\n");
1036     }
1037 }
1038
1039 void
1040 InOrderCPU::activateThread(ThreadID tid)
1041 {
1042     if (isThreadSuspended(tid)) {
1043         DPRINTF(InOrderCPU,
1044                 "Removing [tid:%i] from suspended threads list.\n", tid);
1045
1046         list<ThreadID>::iterator susp_it =
1047             std::find(suspendedThreads.begin(), suspendedThreads.end(),
1048                       tid);
1049         suspendedThreads.erase(susp_it);
1050     }
1051
1052     if (threadModel == SwitchOnCacheMiss &&
1053         numActiveThreads() == 1) {
1054         DPRINTF(InOrderCPU,
1055                 "Ignoring activation of [tid:%i], since [tid:%i] is "
1056                 "already running.\n", tid, activeThreadId());
1057
1058         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
1059                 tid);
1060
1061         readyThreads.push_back(tid);
1062
1063     } else if (!isThreadActive(tid)) {
1064         DPRINTF(InOrderCPU,
1065                 "Adding [tid:%i] to active threads list.\n", tid);
1066         activeThreads.push_back(tid);
1067
1068         activateThreadInPipeline(tid);
1069
1070         thread[tid]->lastActivate = curTick();
1071
1072         tcBase(tid)->setStatus(ThreadContext::Active);
1073
1074         wakeCPU();
1075
1076         numCtxtSwitches++;
1077     }
1078 }
1079
1080 void
1081 InOrderCPU::activateThreadInPipeline(ThreadID tid)
1082 {
1083     for (int stNum=0; stNum < NumStages; stNum++) {
1084         pipelineStage[stNum]->activateThread(tid);
1085     }
1086 }
1087
1088 void
1089 InOrderCPU::deactivateContext(ThreadID tid, Cycles delay)
1090 {
1091     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
1092
1093     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
1094
1095     // Be sure to signal that there's some activity so the CPU doesn't
1096     // deschedule itself.
1097     activityRec.activity();
1098
1099     _status = Running;
1100 }
1101
1102 void
1103 InOrderCPU::deactivateThread(ThreadID tid)
1104 {
1105     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
1106
1107     if (isThreadActive(tid)) {
1108         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
1109                 tid);
1110         list<ThreadID>::iterator thread_it =
1111             std::find(activeThreads.begin(), activeThreads.end(), tid);
1112
1113         removePipelineStalls(*thread_it);
1114
1115         activeThreads.erase(thread_it);
1116
1117         // Ideally, this should be triggered from the
1118         // suspendContext/Thread functions
1119         tcBase(tid)->setStatus(ThreadContext::Suspended);
1120     }
1121
1122     assert(!isThreadActive(tid));
1123 }
1124
1125 void
1126 InOrderCPU::removePipelineStalls(ThreadID tid)
1127 {
1128     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
1129             tid);
1130
1131     for (int stNum = 0; stNum < NumStages ; stNum++) {
1132         pipelineStage[stNum]->removeStalls(tid);
1133     }
1134
1135 }
1136
1137 void
1138 InOrderCPU::updateThreadPriority()
1139 {
1140     if (activeThreads.size() > 1)
1141     {
1142         //DEFAULT TO ROUND ROBIN SCHEME
1143         //e.g. Move highest priority to end of thread list
1144         list<ThreadID>::iterator list_begin = activeThreads.begin();
1145
1146         unsigned high_thread = *list_begin;
1147
1148         activeThreads.erase(list_begin);
1149
1150         activeThreads.push_back(high_thread);
1151     }
1152 }
1153
1154 inline void
1155 InOrderCPU::tickThreadStats()
1156 {
1157     /** Keep track of cycles that each thread is active */
1158     list<ThreadID>::iterator thread_it = activeThreads.begin();
1159     while (thread_it != activeThreads.end()) {
1160         threadCycles[*thread_it]++;
1161         thread_it++;
1162     }
1163
1164     // Keep track of cycles where SMT is active
1165     if (activeThreads.size() > 1) {
1166         smtCycles++;
1167     }
1168 }
1169
1170 void
1171 InOrderCPU::activateContext(ThreadID tid, Cycles delay)
1172 {
1173     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
1174
1175
1176     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
1177
1178     // Be sure to signal that there's some activity so the CPU doesn't
1179     // deschedule itself.
1180     activityRec.activity();
1181
1182     _status = Running;
1183 }
1184
1185 void
1186 InOrderCPU::activateNextReadyContext(Cycles delay)
1187 {
1188     DPRINTF(InOrderCPU,"Activating next ready thread\n");
1189
1190     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
1191                      delay, ActivateNextReadyThread_Pri);
1192
1193     // Be sure to signal that there's some activity so the CPU doesn't
1194     // deschedule itself.
1195     activityRec.activity();
1196
1197     _status = Running;
1198 }
1199
1200 void
1201 InOrderCPU::haltContext(ThreadID tid)
1202 {
1203     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
1204
1205     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid]);
1206
1207     activityRec.activity();
1208 }
1209
1210 void
1211 InOrderCPU::haltThread(ThreadID tid)
1212 {
1213     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
1214     deactivateThread(tid);
1215     squashThreadInPipeline(tid);
1216     haltedThreads.push_back(tid);
1217
1218     tcBase(tid)->setStatus(ThreadContext::Halted);
1219
1220     if (threadModel == SwitchOnCacheMiss) {
1221         activateNextReadyContext();
1222     }
1223 }
1224
1225 void
1226 InOrderCPU::suspendContext(ThreadID tid)
1227 {
1228     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid]);
1229 }
1230
1231 void
1232 InOrderCPU::suspendThread(ThreadID tid)
1233 {
1234     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
1235             tid);
1236     deactivateThread(tid);
1237     suspendedThreads.push_back(tid);
1238     thread[tid]->lastSuspend = curTick();
1239
1240     tcBase(tid)->setStatus(ThreadContext::Suspended);
1241 }
1242
1243 void
1244 InOrderCPU::squashThreadInPipeline(ThreadID tid)
1245 {
1246     //Squash all instructions in each stage
1247     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
1248         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
1249     }
1250 }
1251
1252 PipelineStage*
1253 InOrderCPU::getPipeStage(int stage_num)
1254 {
1255     return pipelineStage[stage_num];
1256 }
1257
1258
1259 RegIndex
1260 InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
1261 {
1262     RegIndex rel_idx;
1263
1264     switch (regIdxToClass(reg_idx, &rel_idx)) {
1265       case IntRegClass:
1266         reg_type = IntType;
1267         return isa[tid]->flattenIntIndex(rel_idx);
1268
1269       case FloatRegClass:
1270         reg_type = FloatType;
1271         return isa[tid]->flattenFloatIndex(rel_idx);
1272
1273       case MiscRegClass:
1274         reg_type = MiscType;
1275         return rel_idx;
1276
1277       default:
1278         panic("register %d out of range\n", reg_idx);
1279     }
1280 }
1281
1282 uint64_t
1283 InOrderCPU::readIntReg(RegIndex reg_idx, ThreadID tid)
1284 {
1285     DPRINTF(IntRegs, "[tid:%i]: Reading Int. Reg %i as %x\n",
1286             tid, reg_idx, intRegs[tid][reg_idx]);
1287
1288     return intRegs[tid][reg_idx];
1289 }
1290
1291 FloatReg
1292 InOrderCPU::readFloatReg(RegIndex reg_idx, ThreadID tid)
1293 {
1294     DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1295             tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
1296
1297     return floatRegs.f[tid][reg_idx];
1298 }
1299
1300 FloatRegBits
1301 InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
1302 {
1303     DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1304             tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
1305
1306     return floatRegs.i[tid][reg_idx];
1307 }
1308
1309 void
1310 InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid)
1311 {
1312     if (reg_idx == TheISA::ZeroReg) {
1313         DPRINTF(IntRegs, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1314                 "(Int. Reg %i) to %x\n", tid, reg_idx, val);
1315         return;
1316     } else {
1317         DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
1318                 tid, reg_idx, val);
1319
1320         intRegs[tid][reg_idx] = val;
1321     }
1322 }
1323
1324
1325 void
1326 InOrderCPU::setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid)
1327 {
1328     floatRegs.f[tid][reg_idx] = val;
1329     DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
1330             "%x, %08f\n",
1331             tid, reg_idx,
1332             floatRegs.i[tid][reg_idx],
1333             floatRegs.f[tid][reg_idx]);
1334 }
1335
1336
1337 void
1338 InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid)
1339 {
1340     floatRegs.i[tid][reg_idx] = val;
1341     DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
1342             "%x, %08f\n",
1343             tid, reg_idx,
1344             floatRegs.i[tid][reg_idx],
1345             floatRegs.f[tid][reg_idx]);
1346 }
1347
1348 uint64_t
1349 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1350 {
1351     // If Default value is set, then retrieve target thread
1352     if (tid == InvalidThreadID) {
1353         tid = TheISA::getTargetThread(tcBase(tid));
1354     }
1355
1356     RegIndex rel_idx;
1357
1358     switch (regIdxToClass(reg_idx, &rel_idx)) {
1359       case IntRegClass:
1360         // Integer Register File
1361         return readIntReg(rel_idx, tid);
1362
1363       case FloatRegClass:
1364         // Float Register File
1365         return readFloatRegBits(rel_idx, tid);
1366
1367       case MiscRegClass:
1368         return readMiscReg(rel_idx, tid);  // Misc. Register File
1369
1370       default:
1371         panic("register %d out of range\n", reg_idx);
1372     }
1373 }
1374
1375 void
1376 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1377                               ThreadID tid)
1378 {
1379     // If Default value is set, then retrieve target thread
1380     if (tid == InvalidThreadID) {
1381         tid = TheISA::getTargetThread(tcBase(tid));
1382     }
1383
1384     RegIndex rel_idx;
1385
1386     switch (regIdxToClass(reg_idx, &rel_idx)) {
1387       case IntRegClass:
1388         setIntReg(rel_idx, val, tid);
1389         break;
1390
1391       case FloatRegClass:
1392         setFloatRegBits(rel_idx, val, tid);
1393         break;
1394
1395       case MiscRegClass:
1396         setMiscReg(rel_idx, val, tid); // Misc. Register File
1397         break;
1398     }
1399 }
1400
1401 MiscReg
1402 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1403 {
1404     return isa[tid]->readMiscRegNoEffect(misc_reg);
1405 }
1406
1407 MiscReg
1408 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1409 {
1410     return isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1411 }
1412
1413 void
1414 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1415 {
1416     isa[tid]->setMiscRegNoEffect(misc_reg, val);
1417 }
1418
1419 void
1420 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1421 {
1422     isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1423 }
1424
1425
1426 InOrderCPU::ListIt
1427 InOrderCPU::addInst(DynInstPtr inst)
1428 {
1429     ThreadID tid = inst->readTid();
1430
1431     instList[tid].push_back(inst);
1432
1433     return --(instList[tid].end());
1434 }
1435
1436 InOrderCPU::ListIt
1437 InOrderCPU::findInst(InstSeqNum seq_num, ThreadID tid)
1438 {
1439     ListIt it = instList[tid].begin();
1440     ListIt end = instList[tid].end();
1441
1442     while (it != end) {
1443         if ((*it)->seqNum == seq_num)
1444             return it;
1445         else if ((*it)->seqNum > seq_num)
1446             break;
1447
1448         it++;
1449     }
1450
1451     return instList[tid].end();
1452 }
1453
1454 void
1455 InOrderCPU::updateContextSwitchStats()
1456 {
1457     // Set Average Stat Here, then reset to 0
1458     instsPerCtxtSwitch = instsPerSwitch;
1459     instsPerSwitch = 0;
1460 }
1461
1462
1463 void
1464 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1465 {
1466     // Set the nextPC to be fetched if this is the last instruction
1467     // committed
1468     // ========
1469     // This contributes to the precise state of the CPU
1470     // which can be used when restoring a thread to the CPU after after any
1471     // type of context switching activity (fork, exception, etc.)
1472     TheISA::PCState comm_pc = inst->pcState();
1473     lastCommittedPC[tid] = comm_pc;
1474     TheISA::advancePC(comm_pc, inst->staticInst);
1475     pcState(comm_pc, tid);
1476
1477     //@todo: may be unnecessary with new-ISA-specific branch handling code
1478     if (inst->isControl()) {
1479         thread[tid]->lastGradIsBranch = true;
1480         thread[tid]->lastBranchPC = inst->pcState();
1481         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1482     } else {
1483         thread[tid]->lastGradIsBranch = false;
1484     }
1485
1486
1487     // Finalize Trace Data For Instruction
1488     if (inst->traceData) {
1489         //inst->traceData->setCycle(curTick());
1490         inst->traceData->setFetchSeq(inst->seqNum);
1491         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1492         inst->traceData->dump();
1493         delete inst->traceData;
1494         inst->traceData = NULL;
1495     }
1496
1497     // Increment active thread's instruction count
1498     instsPerSwitch++;
1499
1500     // Increment thread-state's instruction count
1501     thread[tid]->numInst++;
1502     thread[tid]->numOp++;
1503
1504     // Increment thread-state's instruction stats
1505     thread[tid]->numInsts++;
1506     thread[tid]->numOps++;
1507
1508     // Count committed insts per thread stats
1509     if (!inst->isMicroop() || inst->isLastMicroop()) {
1510         committedInsts[tid]++;
1511
1512         // Count total insts committed stat
1513         totalCommittedInsts++;
1514     }
1515
1516     committedOps[tid]++;
1517
1518     // Count SMT-committed insts per thread stat
1519     if (numActiveThreads() > 1) {
1520         if (!inst->isMicroop() || inst->isLastMicroop())
1521             smtCommittedInsts[tid]++;
1522     }
1523
1524     // Instruction-Mix Stats
1525     if (inst->isLoad()) {
1526         comLoads++;
1527     } else if (inst->isStore()) {
1528         comStores++;
1529     } else if (inst->isControl()) {
1530         comBranches++;
1531     } else if (inst->isNop()) {
1532         comNops++;
1533     } else if (inst->isNonSpeculative()) {
1534         comNonSpec++;
1535     } else if (inst->isInteger()) {
1536         comInts++;
1537     } else if (inst->isFloating()) {
1538         comFloats++;
1539     }
1540
1541     // Check for instruction-count-based events.
1542     comInstEventQueue[tid]->serviceEvents(thread[tid]->numOp);
1543
1544     // Finally, remove instruction from CPU
1545     removeInst(inst);
1546 }
1547
1548 // currently unused function, but substitute repetitive code w/this function
1549 // call
1550 void
1551 InOrderCPU::addToRemoveList(DynInstPtr inst)
1552 {
1553     removeInstsThisCycle = true;
1554     if (!inst->isRemoveList()) {
1555         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1556                 "[sn:%lli] to remove list\n",
1557                 inst->threadNumber, inst->pcState(), inst->seqNum);
1558         inst->setRemoveList();
1559         removeList.push(inst->getInstListIt());
1560     }  else {
1561         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1562                 "[sn:%lli], already remove list\n",
1563                 inst->threadNumber, inst->pcState(), inst->seqNum);
1564     }
1565
1566 }
1567
1568 void
1569 InOrderCPU::removeInst(DynInstPtr inst)
1570 {
1571     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1572             "[sn:%lli]\n",
1573             inst->threadNumber, inst->pcState(), inst->seqNum);
1574
1575     removeInstsThisCycle = true;
1576
1577     // Remove the instruction.
1578     if (!inst->isRemoveList()) {
1579         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1580                 "[sn:%lli] to remove list\n",
1581                 inst->threadNumber, inst->pcState(), inst->seqNum);
1582         inst->setRemoveList();
1583         removeList.push(inst->getInstListIt());
1584     } else {
1585         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1586                 "[sn:%lli], already on remove list\n",
1587                 inst->threadNumber, inst->pcState(), inst->seqNum);
1588     }
1589
1590 }
1591
1592 void
1593 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1594 {
1595     //assert(!instList[tid].empty());
1596
1597     removeInstsThisCycle = true;
1598
1599     ListIt inst_iter = instList[tid].end();
1600
1601     inst_iter--;
1602
1603     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1604             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1605             tid, seq_num, (*inst_iter)->seqNum);
1606
1607     while ((*inst_iter)->seqNum > seq_num) {
1608
1609         bool break_loop = (inst_iter == instList[tid].begin());
1610
1611         squashInstIt(inst_iter, tid);
1612
1613         inst_iter--;
1614
1615         if (break_loop)
1616             break;
1617     }
1618 }
1619
1620
1621 inline void
1622 InOrderCPU::squashInstIt(const ListIt inst_it, ThreadID tid)
1623 {
1624     DynInstPtr inst = (*inst_it);
1625     if (inst->threadNumber == tid) {
1626         DPRINTF(InOrderCPU, "Squashing instruction, "
1627                 "[tid:%i] [sn:%lli] PC %s\n",
1628                 inst->threadNumber,
1629                 inst->seqNum,
1630                 inst->pcState());
1631
1632         inst->setSquashed();
1633         archRegDepMap[tid].remove(inst);
1634
1635         if (!inst->isRemoveList()) {
1636             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1637                     "[sn:%lli] to remove list\n",
1638                     inst->threadNumber, inst->pcState(),
1639                     inst->seqNum);
1640             inst->setRemoveList();
1641             removeList.push(inst_it);
1642         } else {
1643             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1644                     " PC %s [sn:%lli], already on remove list\n",
1645                     inst->threadNumber, inst->pcState(),
1646                     inst->seqNum);
1647         }
1648
1649     }
1650
1651 }
1652
1653
1654 void
1655 InOrderCPU::cleanUpRemovedInsts()
1656 {
1657     while (!removeList.empty()) {
1658         DPRINTF(InOrderCPU, "Removing instruction, "
1659                 "[tid:%i] [sn:%lli] PC %s\n",
1660                 (*removeList.front())->threadNumber,
1661                 (*removeList.front())->seqNum,
1662                (*removeList.front())->pcState());
1663
1664         DynInstPtr inst = *removeList.front();
1665         ThreadID tid = inst->threadNumber;
1666
1667         // Remove From Register Dependency Map, If Necessary
1668         // archRegDepMap[tid].remove(inst);
1669
1670         // Clear if Non-Speculative
1671         if (inst->staticInst &&
1672             inst->seqNum == nonSpecSeqNum[tid] &&
1673             nonSpecInstActive[tid] == true) {
1674             nonSpecInstActive[tid] = false;
1675         }
1676
1677         inst->onInstList = false;
1678
1679         instList[tid].erase(removeList.front());
1680
1681         removeList.pop();
1682     }
1683
1684     removeInstsThisCycle = false;
1685 }
1686
1687 void
1688 InOrderCPU::cleanUpRemovedEvents()
1689 {
1690     while (!cpuEventRemoveList.empty()) {
1691         Event *cpu_event = cpuEventRemoveList.front();
1692         cpuEventRemoveList.pop();
1693         delete cpu_event;
1694     }
1695 }
1696
1697
1698 void
1699 InOrderCPU::dumpInsts()
1700 {
1701     int num = 0;
1702
1703     ListIt inst_list_it = instList[0].begin();
1704
1705     cprintf("Dumping Instruction List\n");
1706
1707     while (inst_list_it != instList[0].end()) {
1708         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1709                 "Squashed:%i\n\n",
1710                 num, (*inst_list_it)->pcState(),
1711                 (*inst_list_it)->threadNumber,
1712                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1713                 (*inst_list_it)->isSquashed());
1714         inst_list_it++;
1715         ++num;
1716     }
1717 }
1718
1719 void
1720 InOrderCPU::wakeCPU()
1721 {
1722     if (/*activityRec.active() || */tickEvent.scheduled()) {
1723         DPRINTF(Activity, "CPU already running.\n");
1724         return;
1725     }
1726
1727     DPRINTF(Activity, "Waking up CPU\n");
1728
1729     Tick extra_cycles = curCycle() - lastRunningCycle;
1730     if (extra_cycles != 0)
1731         --extra_cycles;
1732
1733     idleCycles += extra_cycles;
1734     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1735         pipelineStage[stage_num]->idleCycles += extra_cycles;
1736     }
1737
1738     numCycles += extra_cycles;
1739
1740     schedule(&tickEvent, clockEdge());
1741 }
1742
1743 // Lots of copied full system code...place into BaseCPU class?
1744 void
1745 InOrderCPU::wakeup()
1746 {
1747     if (thread[0]->status() != ThreadContext::Suspended)
1748         return;
1749
1750     wakeCPU();
1751
1752     DPRINTF(Quiesce, "Suspended Processor woken\n");
1753     threadContexts[0]->activate();
1754 }
1755
1756 void
1757 InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
1758                            Cycles delay)
1759 {
1760     // Syscall must be non-speculative, so squash from last stage
1761     unsigned squash_stage = NumStages - 1;
1762     inst->setSquashInfo(squash_stage);
1763
1764     // Squash In Pipeline Stage
1765     pipelineStage[squash_stage]->setupSquash(inst, tid);
1766
1767     // Schedule Squash Through-out Resource Pool
1768     resPool->scheduleEvent(
1769         (InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst,
1770         Cycles(0));
1771     scheduleCpuEvent(Syscall, fault, tid, inst, delay, Syscall_Pri);
1772 }
1773
1774 void
1775 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1776 {
1777     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1778
1779     DPRINTF(Activity,"Activity: syscall() called.\n");
1780
1781     // Temporarily increase this by one to account for the syscall
1782     // instruction.
1783     ++(this->thread[tid]->funcExeInst);
1784
1785     // Execute the actual syscall.
1786     this->thread[tid]->syscall(callnum);
1787
1788     // Decrease funcExeInst by one as the normal commit will handle
1789     // incrementing it.
1790     --(this->thread[tid]->funcExeInst);
1791
1792     // Clear Non-Speculative Block Variable
1793     nonSpecInstActive[tid] = false;
1794 }
1795
1796 TheISA::TLB*
1797 InOrderCPU::getITBPtr()
1798 {
1799     CacheUnit *itb_res = resPool->getInstUnit();
1800     return itb_res->tlb();
1801 }
1802
1803
1804 TheISA::TLB*
1805 InOrderCPU::getDTBPtr()
1806 {
1807     return resPool->getDataUnit()->tlb();
1808 }
1809
1810 TheISA::Decoder *
1811 InOrderCPU::getDecoderPtr(unsigned tid)
1812 {
1813     return resPool->getInstUnit()->decoder[tid];
1814 }
1815
1816 Fault
1817 InOrderCPU::read(DynInstPtr inst, Addr addr,
1818                  uint8_t *data, unsigned size, unsigned flags)
1819 {
1820     return resPool->getDataUnit()->read(inst, addr, data, size, flags);
1821 }
1822
1823 Fault
1824 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1825                   Addr addr, unsigned flags, uint64_t *write_res)
1826 {
1827     return resPool->getDataUnit()->write(inst, data, size, addr, flags,
1828                                          write_res);
1829 }