2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "arch/utility.hh"
35 #include "base/bigint.hh"
36 #include "config/full_system.hh"
37 #include "config/the_isa.hh"
38 #include "cpu/inorder/resources/resource_list.hh"
39 #include "cpu/inorder/cpu.hh"
40 #include "cpu/inorder/first_stage.hh"
41 #include "cpu/inorder/inorder_dyn_inst.hh"
42 #include "cpu/inorder/pipeline_traits.hh"
43 #include "cpu/inorder/resource_pool.hh"
44 #include "cpu/inorder/thread_context.hh"
45 #include "cpu/inorder/thread_state.hh"
46 #include "cpu/activity.hh"
47 #include "cpu/base.hh"
48 #include "cpu/exetrace.hh"
49 #include "cpu/simple_thread.hh"
50 #include "cpu/thread_context.hh"
51 #include "debug/Activity.hh"
52 #include "debug/InOrderCPU.hh"
53 #include "debug/RefCount.hh"
54 #include "debug/SkedCache.hh"
55 #include "mem/translating_port.hh"
56 #include "params/InOrderCPU.hh"
57 #include "sim/process.hh"
58 #include "sim/stat_control.hh"
61 #include "cpu/quiesce_event.hh"
62 #include "sim/system.hh"
65 #if THE_ISA == ALPHA_ISA
66 #include "arch/alpha/osfpal.hh"
70 using namespace TheISA
;
71 using namespace ThePipeline
;
73 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
74 : Event(CPU_Tick_Pri
), cpu(c
)
79 InOrderCPU::TickEvent::process()
86 InOrderCPU::TickEvent::description()
88 return "InOrderCPU tick event";
91 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
92 Fault fault
, ThreadID _tid
, DynInstPtr inst
,
93 unsigned event_pri_offset
)
94 : Event(Event::Priority((unsigned int)CPU_Tick_Pri
+ event_pri_offset
)),
97 setEvent(e_type
, fault
, _tid
, inst
);
101 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
104 "ActivateNextReadyThread",
110 "SquashFromMemStall",
115 InOrderCPU::CPUEvent::process()
117 switch (cpuEventType
)
120 cpu
->activateThread(tid
);
123 case ActivateNextReadyThread
:
124 cpu
->activateNextReadyThread();
127 case DeactivateThread
:
128 cpu
->deactivateThread(tid
);
132 cpu
->haltThread(tid
);
136 cpu
->suspendThread(tid
);
139 case SquashFromMemStall
:
140 cpu
->squashDueToMemStall(inst
->squashingStage
, inst
->seqNum
, tid
);
144 DPRINTF(InOrderCPU
, "Trapping CPU\n");
145 cpu
->trapCPU(fault
, tid
, inst
);
149 fatal("Unrecognized Event Type %s", eventNames
[cpuEventType
]);
152 cpu
->cpuEventRemoveList
.push(this);
158 InOrderCPU::CPUEvent::description()
160 return "InOrderCPU event";
164 InOrderCPU::CPUEvent::scheduleEvent(int delay
)
166 assert(!scheduled() || squashed());
167 cpu
->reschedule(this, cpu
->nextCycle(curTick() + cpu
->ticks(delay
)), true);
171 InOrderCPU::CPUEvent::unscheduleEvent()
177 InOrderCPU::InOrderCPU(Params
*params
)
179 cpu_id(params
->cpu_id
),
183 stageWidth(params
->stageWidth
),
185 removeInstsThisCycle(false),
186 activityRec(params
->name
, NumStages
, 10, params
->activity
),
188 system(params
->system
),
189 physmem(system
->physmem
),
190 #endif // FULL_SYSTEM
196 deferRegistration(false/*params->deferRegistration*/),
197 stageTracing(params
->stageTracing
),
200 ThreadID active_threads
;
203 resPool
= new ResourcePool(this, params
);
205 // Resize for Multithreading CPUs
206 thread
.resize(numThreads
);
211 active_threads
= params
->workload
.size();
213 if (active_threads
> MaxThreads
) {
214 panic("Workload Size too large. Increase the 'MaxThreads'"
215 "in your InOrder implementation or "
216 "edit your workload size.");
220 if (active_threads
> 1) {
221 threadModel
= (InOrderCPU::ThreadModel
) params
->threadModel
;
223 if (threadModel
== SMT
) {
224 DPRINTF(InOrderCPU
, "Setting Thread Model to SMT.\n");
225 } else if (threadModel
== SwitchOnCacheMiss
) {
226 DPRINTF(InOrderCPU
, "Setting Thread Model to "
227 "Switch On Cache Miss\n");
231 threadModel
= Single
;
238 // Bind the fetch & data ports from the resource pool.
239 fetchPortIdx
= resPool
->getPortIdx(params
->fetchMemPort
);
240 if (fetchPortIdx
== 0) {
241 fatal("Unable to find port to fetch instructions from.\n");
244 dataPortIdx
= resPool
->getPortIdx(params
->dataMemPort
);
245 if (dataPortIdx
== 0) {
246 fatal("Unable to find port for data.\n");
249 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
251 // SMT is not supported in FS mode yet.
252 assert(numThreads
== 1);
253 thread
[tid
] = new Thread(this, 0);
255 if (tid
< (ThreadID
)params
->workload
.size()) {
256 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
257 tid
, params
->workload
[tid
]->prog_fname
);
259 new Thread(this, tid
, params
->workload
[tid
]);
261 //Allocate Empty thread so M5 can use later
262 //when scheduling threads to CPU
263 Process
* dummy_proc
= params
->workload
[0];
264 thread
[tid
] = new Thread(this, tid
, dummy_proc
);
267 // Eventually set this with parameters...
271 // Setup the TC that will serve as the interface to the threads/CPU.
272 InOrderThreadContext
*tc
= new InOrderThreadContext
;
274 tc
->thread
= thread
[tid
];
276 // Give the thread the TC.
277 thread
[tid
]->tc
= tc
;
278 thread
[tid
]->setFuncExeInst(0);
279 globalSeqNum
[tid
] = 1;
281 // Add the TC to the CPU's list of TC's.
282 this->threadContexts
.push_back(tc
);
285 // Initialize TimeBuffer Stage Queues
286 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
287 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
288 stageQueue
[stNum
]->id(stNum
);
292 // Set Up Pipeline Stages
293 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
295 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
297 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
299 pipelineStage
[stNum
]->setCPU(this);
300 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
301 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
303 // Take Care of 1st/Nth stages
305 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
306 if (stNum
< NumStages
- 1)
307 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
310 // Initialize thread specific variables
311 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
312 archRegDepMap
[tid
].setCPU(this);
314 nonSpecInstActive
[tid
] = false;
315 nonSpecSeqNum
[tid
] = 0;
317 squashSeqNum
[tid
] = MaxAddr
;
318 lastSquashCycle
[tid
] = 0;
320 memset(intRegs
[tid
], 0, sizeof(intRegs
[tid
]));
321 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
324 // Define dummy instructions and resource requests to be used.
325 dummyInst
[tid
] = new InOrderDynInst(this,
331 dummyReq
[tid
] = new ResourceRequest(resPool
->getResource(0));
334 dummyReqInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
335 dummyReqInst
->setSquashed();
336 dummyReqInst
->resetInstCount();
338 dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
339 dummyBufferInst
->setSquashed();
340 dummyBufferInst
->resetInstCount();
342 endOfSkedIt
= skedCache
.end();
343 frontEndSked
= createFrontEndSked();
345 lastRunningCycle
= curTick();
347 // Reset CPU to reset state.
349 Fault resetFault
= new ResetFault();
350 resetFault
->invoke(tcBase());
354 // Schedule First Tick Event, CPU will reschedule itself from here on out.
355 scheduleTickEvent(0);
358 InOrderCPU::~InOrderCPU()
362 SkedCacheIt sked_it
= skedCache
.begin();
363 SkedCacheIt sked_end
= skedCache
.end();
365 while (sked_it
!= sked_end
) {
366 delete (*sked_it
).second
;
372 m5::hash_map
<InOrderCPU::SkedID
, ThePipeline::RSkedPtr
> InOrderCPU::skedCache
;
375 InOrderCPU::createFrontEndSked()
377 RSkedPtr res_sked
= new ResourceSked();
379 StageScheduler
F(res_sked
, stage_num
++);
380 StageScheduler
D(res_sked
, stage_num
++);
383 F
.needs(FetchSeq
, FetchSeqUnit::AssignNextPC
);
384 F
.needs(ICache
, FetchUnit::InitiateFetch
);
387 D
.needs(ICache
, FetchUnit::CompleteFetch
);
388 D
.needs(Decode
, DecodeUnit::DecodeInst
);
389 D
.needs(BPred
, BranchPredictor::PredictBranch
);
390 D
.needs(FetchSeq
, FetchSeqUnit::UpdateTargetPC
);
393 DPRINTF(SkedCache
, "Resource Sked created for instruction \"front_end\"\n");
399 InOrderCPU::createBackEndSked(DynInstPtr inst
)
401 RSkedPtr res_sked
= lookupSked(inst
);
402 if (res_sked
!= NULL
) {
403 DPRINTF(SkedCache
, "Found %s in sked cache.\n",
407 res_sked
= new ResourceSked();
410 int stage_num
= ThePipeline::BackEndStartStage
;
411 StageScheduler
X(res_sked
, stage_num
++);
412 StageScheduler
M(res_sked
, stage_num
++);
413 StageScheduler
W(res_sked
, stage_num
++);
415 if (!inst
->staticInst
) {
416 warn_once("Static Instruction Object Not Set. Can't Create"
417 " Back End Schedule");
422 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
423 if (!idx
|| !inst
->isStore()) {
424 X
.needs(RegManager
, UseDefUnit::ReadSrcReg
, idx
);
428 //@todo: schedule non-spec insts to operate on this cycle
429 // as long as all previous insts are done
430 if ( inst
->isNonSpeculative() ) {
431 // skip execution of non speculative insts until later
432 } else if ( inst
->isMemRef() ) {
433 if ( inst
->isLoad() ) {
434 X
.needs(AGEN
, AGENUnit::GenerateAddr
);
436 } else if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
437 X
.needs(MDU
, MultDivUnit::StartMultDiv
);
439 X
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
443 if (!inst
->isNonSpeculative()) {
444 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
445 M
.needs(MDU
, MultDivUnit::EndMultDiv
);
448 if ( inst
->isLoad() ) {
449 M
.needs(DCache
, CacheUnit::InitiateReadData
);
451 M
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
452 } else if ( inst
->isStore() ) {
453 if ( inst
->numSrcRegs() >= 2 ) {
454 M
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
456 M
.needs(AGEN
, AGENUnit::GenerateAddr
);
457 M
.needs(DCache
, CacheUnit::InitiateWriteData
);
459 M
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
464 if (!inst
->isNonSpeculative()) {
465 if ( inst
->isLoad() ) {
466 W
.needs(DCache
, CacheUnit::CompleteReadData
);
468 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
469 } else if ( inst
->isStore() ) {
470 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
472 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
475 // Finally, Execute Speculative Data
476 if (inst
->isMemRef()) {
477 if (inst
->isLoad()) {
478 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
479 W
.needs(DCache
, CacheUnit::InitiateReadData
);
481 W
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
482 W
.needs(DCache
, CacheUnit::CompleteReadData
);
484 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
485 } else if (inst
->isStore()) {
486 if ( inst
->numSrcRegs() >= 2 ) {
487 W
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
489 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
490 W
.needs(DCache
, CacheUnit::InitiateWriteData
);
492 W
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
493 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
495 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
498 W
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
502 W
.needs(Grad
, GraduationUnit::GraduateInst
);
504 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
505 W
.needs(RegManager
, UseDefUnit::WriteDestReg
, idx
);
508 // Insert Back Schedule into our cache of
509 // resource schedules
510 addToSkedCache(inst
, res_sked
);
512 DPRINTF(SkedCache
, "Back End Sked Created for instruction: %s (%08p)\n",
513 inst
->instName(), inst
->getMachInst());
520 InOrderCPU::regStats()
522 /* Register the Resource Pool's stats here.*/
525 /* Register for each Pipeline Stage */
526 for (int stage_num
=0; stage_num
< ThePipeline::NumStages
; stage_num
++) {
527 pipelineStage
[stage_num
]->regStats();
530 /* Register any of the InOrderCPU's stats here.*/
532 .name(name() + ".instsPerContextSwitch")
533 .desc("Instructions Committed Per Context Switch")
534 .prereq(instsPerCtxtSwitch
);
537 .name(name() + ".contextSwitches")
538 .desc("Number of context switches");
541 .name(name() + ".comLoads")
542 .desc("Number of Load instructions committed");
545 .name(name() + ".comStores")
546 .desc("Number of Store instructions committed");
549 .name(name() + ".comBranches")
550 .desc("Number of Branches instructions committed");
553 .name(name() + ".comNops")
554 .desc("Number of Nop instructions committed");
557 .name(name() + ".comNonSpec")
558 .desc("Number of Non-Speculative instructions committed");
561 .name(name() + ".comInts")
562 .desc("Number of Integer instructions committed");
565 .name(name() + ".comFloats")
566 .desc("Number of Floating Point instructions committed");
569 .name(name() + ".timesIdled")
570 .desc("Number of times that the entire CPU went into an idle state and"
571 " unscheduled itself")
575 .name(name() + ".idleCycles")
576 .desc("Number of cycles cpu's stages were not processed");
579 .name(name() + ".runCycles")
580 .desc("Number of cycles cpu stages are processed.");
583 .name(name() + ".activity")
584 .desc("Percentage of cycles cpu is active")
586 activity
= (runCycles
/ numCycles
) * 100;
590 .name(name() + ".threadCycles")
591 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
594 .name(name() + ".smtCycles")
595 .desc("Total number of cycles that the CPU was in SMT-mode");
599 .name(name() + ".committedInsts")
600 .desc("Number of Instructions Simulated (Per-Thread)");
604 .name(name() + ".smtCommittedInsts")
605 .desc("Number of SMT Instructions Simulated (Per-Thread)");
608 .name(name() + ".committedInsts_total")
609 .desc("Number of Instructions Simulated (Total)");
612 .name(name() + ".cpi")
613 .desc("CPI: Cycles Per Instruction (Per-Thread)")
615 cpi
= numCycles
/ committedInsts
;
618 .name(name() + ".smt_cpi")
619 .desc("CPI: Total SMT-CPI")
621 smtCpi
= smtCycles
/ smtCommittedInsts
;
624 .name(name() + ".cpi_total")
625 .desc("CPI: Total CPI of All Threads")
627 totalCpi
= numCycles
/ totalCommittedInsts
;
630 .name(name() + ".ipc")
631 .desc("IPC: Instructions Per Cycle (Per-Thread)")
633 ipc
= committedInsts
/ numCycles
;
636 .name(name() + ".smt_ipc")
637 .desc("IPC: Total SMT-IPC")
639 smtIpc
= smtCommittedInsts
/ smtCycles
;
642 .name(name() + ".ipc_total")
643 .desc("IPC: Total IPC of All Threads")
645 totalIpc
= totalCommittedInsts
/ numCycles
;
654 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
658 bool pipes_idle
= true;
660 //Tick each of the stages
661 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
662 pipelineStage
[stNum
]->tick();
664 pipes_idle
= pipes_idle
&& pipelineStage
[stNum
]->idle
;
672 // Now advance the time buffers one tick
673 timeBuffer
.advance();
674 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
675 stageQueue
[sqNum
]->advance();
677 activityRec
.advance();
679 // Any squashed events, or insts then remove them now
680 cleanUpRemovedEvents();
681 cleanUpRemovedInsts();
683 // Re-schedule CPU for this cycle
684 if (!tickEvent
.scheduled()) {
685 if (_status
== SwitchedOut
) {
687 lastRunningCycle
= curTick();
688 } else if (!activityRec
.active()) {
689 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
690 lastRunningCycle
= curTick();
693 //Tick next_tick = curTick() + cycles(1);
694 //tickEvent.schedule(next_tick);
695 schedule(&tickEvent
, nextCycle(curTick() + 1));
696 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n",
697 nextCycle(curTick() + 1));
702 updateThreadPriority();
709 if (!deferRegistration
) {
710 registerThreadContexts();
713 // Set inSyscall so that the CPU doesn't squash when initially
714 // setting up registers.
715 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
716 thread
[tid
]->inSyscall
= true;
719 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
720 ThreadContext
*src_tc
= threadContexts
[tid
];
721 TheISA::initCPU(src_tc
, src_tc
->contextId());
726 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
727 thread
[tid
]->inSyscall
= false;
729 // Call Initializiation Routine for Resource Pool
734 InOrderCPU::getPort(const std::string
&if_name
, int idx
)
736 return resPool
->getPort(if_name
, idx
);
741 InOrderCPU::hwrei(ThreadID tid
)
743 panic("hwrei: Unimplemented");
750 InOrderCPU::simPalCheck(int palFunc
, ThreadID tid
)
752 panic("simPalCheck: Unimplemented");
759 InOrderCPU::getInterrupts()
761 // Check if there are any outstanding interrupts
762 return interrupts
->getInterrupt(threadContexts
[0]);
767 InOrderCPU::processInterrupts(Fault interrupt
)
769 // Check for interrupts here. For now can copy the code that
770 // exists within isa_fullsys_traits.hh. Also assume that thread 0
771 // is the one that handles the interrupts.
772 // @todo: Possibly consolidate the interrupt checking code.
773 // @todo: Allow other threads to handle interrupts.
775 assert(interrupt
!= NoFault
);
776 interrupts
->updateIntrInfo(threadContexts
[0]);
778 DPRINTF(InOrderCPU
, "Interrupt %s being handled\n", interrupt
->name());
780 // Note: Context ID ok here? Impl. of FS mode needs to revisit this
781 trap(interrupt
, threadContexts
[0]->contextId(), dummyBufferInst
);
786 InOrderCPU::updateMemPorts()
788 // Update all ThreadContext's memory ports (Functional/Virtual
790 ThreadID size
= thread
.size();
791 for (ThreadID i
= 0; i
< size
; ++i
)
792 thread
[i
]->connectMemPorts(thread
[i
]->getTC());
797 InOrderCPU::trap(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
799 //@ Squash Pipeline during TRAP
800 scheduleCpuEvent(Trap
, fault
, tid
, inst
, delay
);
804 InOrderCPU::trapCPU(Fault fault
, ThreadID tid
, DynInstPtr inst
)
806 fault
->invoke(tcBase(tid
), inst
->staticInst
);
810 InOrderCPU::squashFromMemStall(DynInstPtr inst
, ThreadID tid
, int delay
)
812 scheduleCpuEvent(SquashFromMemStall
, NoFault
, tid
, inst
, delay
);
817 InOrderCPU::squashDueToMemStall(int stage_num
, InstSeqNum seq_num
,
820 DPRINTF(InOrderCPU
, "Squashing Pipeline Stages Due to Memory Stall...\n");
822 // Squash all instructions in each stage including
823 // instruction that caused the squash (seq_num - 1)
824 // NOTE: The stage bandwidth needs to be cleared so thats why
825 // the stalling instruction is squashed as well. The stalled
826 // instruction is previously placed in another intermediate buffer
827 // while it's stall is being handled.
828 InstSeqNum squash_seq_num
= seq_num
- 1;
830 for (int stNum
=stage_num
; stNum
>= 0 ; stNum
--) {
831 pipelineStage
[stNum
]->squashDueToMemStall(squash_seq_num
, tid
);
836 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
837 ThreadID tid
, DynInstPtr inst
,
838 unsigned delay
, unsigned event_pri_offset
)
840 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, inst
,
843 Tick sked_tick
= nextCycle(curTick() + ticks(delay
));
845 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
846 eventNames
[c_event
], curTick() + delay
, tid
);
847 schedule(cpu_event
, sked_tick
);
849 cpu_event
->process();
850 cpuEventRemoveList
.push(cpu_event
);
853 // Broadcast event to the Resource Pool
854 // Need to reset tid just in case this is a dummy instruction
856 resPool
->scheduleEvent(c_event
, inst
, 0, 0, tid
);
860 InOrderCPU::isThreadActive(ThreadID tid
)
862 list
<ThreadID
>::iterator isActive
=
863 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
865 return (isActive
!= activeThreads
.end());
869 InOrderCPU::isThreadReady(ThreadID tid
)
871 list
<ThreadID
>::iterator isReady
=
872 std::find(readyThreads
.begin(), readyThreads
.end(), tid
);
874 return (isReady
!= readyThreads
.end());
878 InOrderCPU::isThreadSuspended(ThreadID tid
)
880 list
<ThreadID
>::iterator isSuspended
=
881 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
883 return (isSuspended
!= suspendedThreads
.end());
887 InOrderCPU::activateNextReadyThread()
889 if (readyThreads
.size() >= 1) {
890 ThreadID ready_tid
= readyThreads
.front();
892 // Activate in Pipeline
893 activateThread(ready_tid
);
895 // Activate in Resource Pool
896 resPool
->activateAll(ready_tid
);
898 list
<ThreadID
>::iterator ready_it
=
899 std::find(readyThreads
.begin(), readyThreads
.end(), ready_tid
);
900 readyThreads
.erase(ready_it
);
903 "Attempting to activate new thread, but No Ready Threads to"
906 "Unable to switch to next active thread.\n");
911 InOrderCPU::activateThread(ThreadID tid
)
913 if (isThreadSuspended(tid
)) {
915 "Removing [tid:%i] from suspended threads list.\n", tid
);
917 list
<ThreadID
>::iterator susp_it
=
918 std::find(suspendedThreads
.begin(), suspendedThreads
.end(),
920 suspendedThreads
.erase(susp_it
);
923 if (threadModel
== SwitchOnCacheMiss
&&
924 numActiveThreads() == 1) {
926 "Ignoring activation of [tid:%i], since [tid:%i] is "
927 "already running.\n", tid
, activeThreadId());
929 DPRINTF(InOrderCPU
,"Placing [tid:%i] on ready threads list\n",
932 readyThreads
.push_back(tid
);
934 } else if (!isThreadActive(tid
)) {
936 "Adding [tid:%i] to active threads list.\n", tid
);
937 activeThreads
.push_back(tid
);
939 activateThreadInPipeline(tid
);
941 thread
[tid
]->lastActivate
= curTick();
943 tcBase(tid
)->setStatus(ThreadContext::Active
);
952 InOrderCPU::activateThreadInPipeline(ThreadID tid
)
954 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
955 pipelineStage
[stNum
]->activateThread(tid
);
960 InOrderCPU::deactivateContext(ThreadID tid
, int delay
)
962 DPRINTF(InOrderCPU
,"[tid:%i]: Deactivating ...\n", tid
);
964 scheduleCpuEvent(DeactivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
966 // Be sure to signal that there's some activity so the CPU doesn't
967 // deschedule itself.
968 activityRec
.activity();
974 InOrderCPU::deactivateThread(ThreadID tid
)
976 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
978 if (isThreadActive(tid
)) {
979 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
981 list
<ThreadID
>::iterator thread_it
=
982 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
984 removePipelineStalls(*thread_it
);
986 activeThreads
.erase(thread_it
);
988 // Ideally, this should be triggered from the
989 // suspendContext/Thread functions
990 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
993 assert(!isThreadActive(tid
));
997 InOrderCPU::removePipelineStalls(ThreadID tid
)
999 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
1002 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
1003 pipelineStage
[stNum
]->removeStalls(tid
);
1009 InOrderCPU::updateThreadPriority()
1011 if (activeThreads
.size() > 1)
1013 //DEFAULT TO ROUND ROBIN SCHEME
1014 //e.g. Move highest priority to end of thread list
1015 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
1016 list
<ThreadID
>::iterator list_end
= activeThreads
.end();
1018 unsigned high_thread
= *list_begin
;
1020 activeThreads
.erase(list_begin
);
1022 activeThreads
.push_back(high_thread
);
1027 InOrderCPU::tickThreadStats()
1029 /** Keep track of cycles that each thread is active */
1030 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
1031 while (thread_it
!= activeThreads
.end()) {
1032 threadCycles
[*thread_it
]++;
1036 // Keep track of cycles where SMT is active
1037 if (activeThreads
.size() > 1) {
1043 InOrderCPU::activateContext(ThreadID tid
, int delay
)
1045 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
1048 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1050 // Be sure to signal that there's some activity so the CPU doesn't
1051 // deschedule itself.
1052 activityRec
.activity();
1058 InOrderCPU::activateNextReadyContext(int delay
)
1060 DPRINTF(InOrderCPU
,"Activating next ready thread\n");
1062 // NOTE: Add 5 to the event priority so that we always activate
1063 // threads after we've finished deactivating, squashing,etc.
1065 scheduleCpuEvent(ActivateNextReadyThread
, NoFault
, 0/*tid*/, dummyInst
[0],
1068 // Be sure to signal that there's some activity so the CPU doesn't
1069 // deschedule itself.
1070 activityRec
.activity();
1076 InOrderCPU::haltContext(ThreadID tid
, int delay
)
1078 DPRINTF(InOrderCPU
, "[tid:%i]: Calling Halt Context...\n", tid
);
1080 scheduleCpuEvent(HaltThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1082 activityRec
.activity();
1086 InOrderCPU::haltThread(ThreadID tid
)
1088 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Halted Threads List...\n", tid
);
1089 deactivateThread(tid
);
1090 squashThreadInPipeline(tid
);
1091 haltedThreads
.push_back(tid
);
1093 tcBase(tid
)->setStatus(ThreadContext::Halted
);
1095 if (threadModel
== SwitchOnCacheMiss
) {
1096 activateNextReadyContext();
1101 InOrderCPU::suspendContext(ThreadID tid
, int delay
)
1103 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1107 InOrderCPU::suspendThread(ThreadID tid
)
1109 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Suspended Threads List...\n",
1111 deactivateThread(tid
);
1112 suspendedThreads
.push_back(tid
);
1113 thread
[tid
]->lastSuspend
= curTick();
1115 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1119 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
1121 //Squash all instructions in each stage
1122 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
1123 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
1128 InOrderCPU::getPipeStage(int stage_num
)
1130 return pipelineStage
[stage_num
];
1134 InOrderCPU::flattenRegIdx(RegIndex reg_idx
, RegType
®_type
, ThreadID tid
)
1136 if (reg_idx
< FP_Base_DepTag
) {
1138 return isa
[tid
].flattenIntIndex(reg_idx
);
1139 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1140 reg_type
= FloatType
;
1141 reg_idx
-= FP_Base_DepTag
;
1142 return isa
[tid
].flattenFloatIndex(reg_idx
);
1144 reg_type
= MiscType
;
1145 return reg_idx
- TheISA::Ctrl_Base_DepTag
;
1150 InOrderCPU::readIntReg(RegIndex reg_idx
, ThreadID tid
)
1152 DPRINTF(IntRegs
, "[tid:%i]: Reading Int. Reg %i as %x\n",
1153 tid
, reg_idx
, intRegs
[tid
][reg_idx
]);
1155 return intRegs
[tid
][reg_idx
];
1159 InOrderCPU::readFloatReg(RegIndex reg_idx
, ThreadID tid
)
1161 return floatRegs
.f
[tid
][reg_idx
];
1165 InOrderCPU::readFloatRegBits(RegIndex reg_idx
, ThreadID tid
)
1167 return floatRegs
.i
[tid
][reg_idx
];
1171 InOrderCPU::setIntReg(RegIndex reg_idx
, uint64_t val
, ThreadID tid
)
1173 if (reg_idx
== TheISA::ZeroReg
) {
1174 DPRINTF(IntRegs
, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1175 "(Int. Reg %i) to %x\n", tid
, reg_idx
, val
);
1178 DPRINTF(IntRegs
, "[tid:%i]: Setting Int. Reg %i to %x\n",
1181 intRegs
[tid
][reg_idx
] = val
;
1187 InOrderCPU::setFloatReg(RegIndex reg_idx
, FloatReg val
, ThreadID tid
)
1189 floatRegs
.f
[tid
][reg_idx
] = val
;
1194 InOrderCPU::setFloatRegBits(RegIndex reg_idx
, FloatRegBits val
, ThreadID tid
)
1196 floatRegs
.i
[tid
][reg_idx
] = val
;
1200 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
1202 // If Default value is set, then retrieve target thread
1203 if (tid
== InvalidThreadID
) {
1204 tid
= TheISA::getTargetThread(tcBase(tid
));
1207 if (reg_idx
< FP_Base_DepTag
) {
1208 // Integer Register File
1209 return readIntReg(reg_idx
, tid
);
1210 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1211 // Float Register File
1212 reg_idx
-= FP_Base_DepTag
;
1213 return readFloatRegBits(reg_idx
, tid
);
1215 reg_idx
-= Ctrl_Base_DepTag
;
1216 return readMiscReg(reg_idx
, tid
); // Misc. Register File
1220 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
1223 // If Default value is set, then retrieve target thread
1224 if (tid
== InvalidThreadID
) {
1225 tid
= TheISA::getTargetThread(tcBase(tid
));
1228 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
1229 setIntReg(reg_idx
, val
, tid
);
1230 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
1231 reg_idx
-= FP_Base_DepTag
;
1232 setFloatRegBits(reg_idx
, val
, tid
);
1234 reg_idx
-= Ctrl_Base_DepTag
;
1235 setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
1240 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1242 return isa
[tid
].readMiscRegNoEffect(misc_reg
);
1246 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
1248 return isa
[tid
].readMiscReg(misc_reg
, tcBase(tid
));
1252 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1254 isa
[tid
].setMiscRegNoEffect(misc_reg
, val
);
1258 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1260 isa
[tid
].setMiscReg(misc_reg
, val
, tcBase(tid
));
1265 InOrderCPU::addInst(DynInstPtr inst
)
1267 ThreadID tid
= inst
->readTid();
1269 instList
[tid
].push_back(inst
);
1271 return --(instList
[tid
].end());
1275 InOrderCPU::updateContextSwitchStats()
1277 // Set Average Stat Here, then reset to 0
1278 instsPerCtxtSwitch
= instsPerSwitch
;
1284 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1286 // Set the CPU's PCs - This contributes to the precise state of the CPU
1287 // which can be used when restoring a thread to the CPU after after any
1288 // type of context switching activity (fork, exception, etc.)
1289 pcState(inst
->pcState(), tid
);
1291 if (inst
->isControl()) {
1292 thread
[tid
]->lastGradIsBranch
= true;
1293 thread
[tid
]->lastBranchPC
= inst
->pcState();
1294 TheISA::advancePC(thread
[tid
]->lastBranchPC
, inst
->staticInst
);
1296 thread
[tid
]->lastGradIsBranch
= false;
1300 // Finalize Trace Data For Instruction
1301 if (inst
->traceData
) {
1302 //inst->traceData->setCycle(curTick());
1303 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1304 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1305 inst
->traceData
->dump();
1306 delete inst
->traceData
;
1307 inst
->traceData
= NULL
;
1310 // Increment active thread's instruction count
1313 // Increment thread-state's instruction count
1314 thread
[tid
]->numInst
++;
1316 // Increment thread-state's instruction stats
1317 thread
[tid
]->numInsts
++;
1319 // Count committed insts per thread stats
1320 committedInsts
[tid
]++;
1322 // Count total insts committed stat
1323 totalCommittedInsts
++;
1325 // Count SMT-committed insts per thread stat
1326 if (numActiveThreads() > 1) {
1327 smtCommittedInsts
[tid
]++;
1330 // Instruction-Mix Stats
1331 if (inst
->isLoad()) {
1333 } else if (inst
->isStore()) {
1335 } else if (inst
->isControl()) {
1337 } else if (inst
->isNop()) {
1339 } else if (inst
->isNonSpeculative()) {
1341 } else if (inst
->isInteger()) {
1343 } else if (inst
->isFloating()) {
1347 // Check for instruction-count-based events.
1348 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numInst
);
1350 // Broadcast to other resources an instruction
1351 // has been completed
1352 resPool
->scheduleEvent((CPUEventType
)ResourcePool::InstGraduated
, inst
,
1355 // Finally, remove instruction from CPU
1359 // currently unused function, but substitute repetitive code w/this function
1362 InOrderCPU::addToRemoveList(DynInstPtr inst
)
1364 removeInstsThisCycle
= true;
1365 if (!inst
->isRemoveList()) {
1366 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1367 "[sn:%lli] to remove list\n",
1368 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1369 inst
->setRemoveList();
1370 removeList
.push(inst
->getInstListIt());
1372 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1373 "[sn:%lli], already remove list\n",
1374 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1380 InOrderCPU::removeInst(DynInstPtr inst
)
1382 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %s "
1384 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1386 removeInstsThisCycle
= true;
1388 // Remove the instruction.
1389 if (!inst
->isRemoveList()) {
1390 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1391 "[sn:%lli] to remove list\n",
1392 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1393 inst
->setRemoveList();
1394 removeList
.push(inst
->getInstListIt());
1396 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1397 "[sn:%lli], already on remove list\n",
1398 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1404 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1406 //assert(!instList[tid].empty());
1408 removeInstsThisCycle
= true;
1410 ListIt inst_iter
= instList
[tid
].end();
1414 DPRINTF(InOrderCPU
, "Squashing instructions from CPU instruction "
1415 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1416 tid
, seq_num
, (*inst_iter
)->seqNum
);
1418 while ((*inst_iter
)->seqNum
> seq_num
) {
1420 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1422 squashInstIt(inst_iter
, tid
);
1433 InOrderCPU::squashInstIt(const ListIt
&instIt
, ThreadID tid
)
1435 if ((*instIt
)->threadNumber
== tid
) {
1436 DPRINTF(InOrderCPU
, "Squashing instruction, "
1437 "[tid:%i] [sn:%lli] PC %s\n",
1438 (*instIt
)->threadNumber
,
1440 (*instIt
)->pcState());
1442 (*instIt
)->setSquashed();
1444 if (!(*instIt
)->isRemoveList()) {
1445 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1446 "[sn:%lli] to remove list\n",
1447 (*instIt
)->threadNumber
, (*instIt
)->pcState(),
1449 (*instIt
)->setRemoveList();
1450 removeList
.push(instIt
);
1452 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i]"
1453 " PC %s [sn:%lli], already on remove list\n",
1454 (*instIt
)->threadNumber
, (*instIt
)->pcState(),
1464 InOrderCPU::cleanUpRemovedInsts()
1466 while (!removeList
.empty()) {
1467 DPRINTF(InOrderCPU
, "Removing instruction, "
1468 "[tid:%i] [sn:%lli] PC %s\n",
1469 (*removeList
.front())->threadNumber
,
1470 (*removeList
.front())->seqNum
,
1471 (*removeList
.front())->pcState());
1473 DynInstPtr inst
= *removeList
.front();
1474 ThreadID tid
= inst
->threadNumber
;
1476 // Remove From Register Dependency Map, If Necessary
1477 archRegDepMap
[tid
].remove(inst
);
1479 // Clear if Non-Speculative
1480 if (inst
->staticInst
&&
1481 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1482 nonSpecInstActive
[tid
] == true) {
1483 nonSpecInstActive
[tid
] = false;
1486 inst
->onInstList
= false;
1488 instList
[tid
].erase(removeList
.front());
1493 removeInstsThisCycle
= false;
1497 InOrderCPU::cleanUpRemovedEvents()
1499 while (!cpuEventRemoveList
.empty()) {
1500 Event
*cpu_event
= cpuEventRemoveList
.front();
1501 cpuEventRemoveList
.pop();
1508 InOrderCPU::dumpInsts()
1512 ListIt inst_list_it
= instList
[0].begin();
1514 cprintf("Dumping Instruction List\n");
1516 while (inst_list_it
!= instList
[0].end()) {
1517 cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1519 num
, (*inst_list_it
)->pcState(),
1520 (*inst_list_it
)->threadNumber
,
1521 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1522 (*inst_list_it
)->isSquashed());
1529 InOrderCPU::wakeCPU()
1531 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1532 DPRINTF(Activity
, "CPU already running.\n");
1536 DPRINTF(Activity
, "Waking up CPU\n");
1538 Tick extra_cycles
= tickToCycles((curTick() - 1) - lastRunningCycle
);
1540 idleCycles
+= extra_cycles
;
1541 for (int stage_num
= 0; stage_num
< NumStages
; stage_num
++) {
1542 pipelineStage
[stage_num
]->idleCycles
+= extra_cycles
;
1545 numCycles
+= extra_cycles
;
1547 schedule(&tickEvent
, nextCycle(curTick()));
1553 InOrderCPU::wakeup()
1555 if (thread
[0]->status() != ThreadContext::Suspended
)
1560 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1561 threadContexts
[0]->activate();
1567 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1569 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1571 DPRINTF(Activity
,"Activity: syscall() called.\n");
1573 // Temporarily increase this by one to account for the syscall
1575 ++(this->thread
[tid
]->funcExeInst
);
1577 // Execute the actual syscall.
1578 this->thread
[tid
]->syscall(callnum
);
1580 // Decrease funcExeInst by one as the normal commit will handle
1582 --(this->thread
[tid
]->funcExeInst
);
1584 // Clear Non-Speculative Block Variable
1585 nonSpecInstActive
[tid
] = false;
1590 InOrderCPU::getITBPtr()
1592 CacheUnit
*itb_res
=
1593 dynamic_cast<CacheUnit
*>(resPool
->getResource(fetchPortIdx
));
1594 return itb_res
->tlb();
1599 InOrderCPU::getDTBPtr()
1601 CacheUnit
*dtb_res
=
1602 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1603 return dtb_res
->tlb();
1607 InOrderCPU::read(DynInstPtr inst
, Addr addr
,
1608 uint8_t *data
, unsigned size
, unsigned flags
)
1610 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1611 // you want to run w/out caches?
1612 CacheUnit
*cache_res
=
1613 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1615 return cache_res
->read(inst
, addr
, data
, size
, flags
);
1619 InOrderCPU::write(DynInstPtr inst
, uint8_t *data
, unsigned size
,
1620 Addr addr
, unsigned flags
, uint64_t *write_res
)
1622 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1623 // you want to run w/out caches?
1624 CacheUnit
*cache_res
=
1625 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1626 return cache_res
->write(inst
, data
, size
, addr
, flags
, write_res
);