src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <algorithm>
  33
  34 #include "arch/utility.hh"
  35 #include "config/full_system.hh"
  36 #include "config/the_isa.hh"
  37 #include "cpu/activity.hh"
  38 #include "cpu/base.hh"
  39 #include "cpu/exetrace.hh"
  40 #include "cpu/inorder/cpu.hh"
  41 #include "cpu/inorder/first_stage.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource_pool.hh"
  45 #include "cpu/inorder/resources/resource_list.hh"
  46 #include "cpu/inorder/thread_context.hh"
  47 #include "cpu/inorder/thread_state.hh"
  48 #include "cpu/simple_thread.hh"
  49 #include "cpu/thread_context.hh"
  50 #include "mem/translating_port.hh"
  51 #include "params/InOrderCPU.hh"
  52 #include "sim/process.hh"
  53 #include "sim/stat_control.hh"
  54
  55 #if FULL_SYSTEM
  56 #include "cpu/quiesce_event.hh"
  57 #include "sim/system.hh"
  58 #endif
  59
  60 #if THE_ISA == ALPHA_ISA
  61 #include "arch/alpha/osfpal.hh"
  62 #endif
  63
  64 using namespace std;
  65 using namespace TheISA;
  66 using namespace ThePipeline;
  67
  68 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
  69   : Event(CPU_Tick_Pri), cpu(c)
  70 { }
  71
  72
  73 void
  74 InOrderCPU::TickEvent::process()
  75 {
  76     cpu->tick();
  77 }
  78
  79
  80 const char *
  81 InOrderCPU::TickEvent::description()
  82 {
  83     return "InOrderCPU tick event";
  84 }
  85
  86 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
  87                                Fault fault, ThreadID _tid, DynInstPtr inst,
  88                                unsigned event_pri_offset)
  89     : Event(Event::Priority((unsigned int)CPU_Tick_Pri + event_pri_offset)),
  90       cpu(_cpu)
  91 {
  92     setEvent(e_type, fault, _tid, inst);
  93 }
  94
  95
  96 std::string InOrderCPU::eventNames[NumCPUEvents] =
  97 {
  98     "ActivateThread",
  99     "ActivateNextReadyThread",
 100     "DeactivateThread",
 101     "DeallocateThread",
 102     "SuspendThread",
 103     "Trap",
 104     "InstGraduated",
 105     "SquashFromMemStall",
 106     "UpdatePCs"
 107 };
 108
 109 void
 110 InOrderCPU::CPUEvent::process()
 111 {
 112     switch (cpuEventType)
 113     {
 114       case ActivateThread:
 115         cpu->activateThread(tid);
 116         break;
 117
 118       case ActivateNextReadyThread:
 119         cpu->activateNextReadyThread();
 120         break;
 121
 122       case DeactivateThread:
 123         cpu->deactivateThread(tid);
 124         break;
 125
 126       case DeallocateThread:
 127         cpu->deallocateThread(tid);
 128         break;
 129
 130       case SuspendThread:
 131         cpu->suspendThread(tid);
 132         break;
 133
 134       case SquashFromMemStall:
 135         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 136         break;
 137
 138       case Trap:
 139         cpu->trapCPU(fault, tid);
 140         break;
 141
 142       default:
 143         fatal("Unrecognized Event Type %d", cpuEventType);
 144
 145     }
 146
 147     cpu->cpuEventRemoveList.push(this);
 148 }
 149
 150
 151
 152 const char *
 153 InOrderCPU::CPUEvent::description()
 154 {
 155     return "InOrderCPU event";
 156 }
 157
 158 void
 159 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 160 {
 161     if (squashed())
 162       mainEventQueue.reschedule(this,curTick + cpu->ticks(delay));
 163     else if (!scheduled())
 164       mainEventQueue.schedule(this,curTick + cpu->ticks(delay));
 165 }
 166
 167 void
 168 InOrderCPU::CPUEvent::unscheduleEvent()
 169 {
 170     if (scheduled())
 171         squash();
 172 }
 173
 174 InOrderCPU::InOrderCPU(Params *params)
 175     : BaseCPU(params),
 176       cpu_id(params->cpu_id),
 177       coreType("default"),
 178       _status(Idle),
 179       tickEvent(this),
 180       timeBuffer(2 , 2),
 181       removeInstsThisCycle(false),
 182       activityRec(params->name, NumStages, 10, params->activity),
 183 #if FULL_SYSTEM
 184       system(params->system),
 185       physmem(system->physmem),
 186 #endif // FULL_SYSTEM
 187 #ifdef DEBUG
 188       cpuEventNum(0),
 189       resReqCount(0),
 190 #endif // DEBUG
 191       switchCount(0),
 192       deferRegistration(false/*params->deferRegistration*/),
 193       stageTracing(params->stageTracing)
 194 {
 195     ThreadID active_threads;
 196     cpu_params = params;
 197
 198     resPool = new ResourcePool(this, params);
 199
 200     // Resize for Multithreading CPUs
 201     thread.resize(numThreads);
 202
 203 #if FULL_SYSTEM
 204     active_threads = 1;
 205 #else
 206     active_threads = params->workload.size();
 207
 208     if (active_threads > MaxThreads) {
 209         panic("Workload Size too large. Increase the 'MaxThreads'"
 210               "in your InOrder implementation or "
 211               "edit your workload size.");
 212     }
 213
 214     if (active_threads > 1) {
 215         threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 216
 217         if (threadModel == SMT) {
 218             DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 219         } else if (threadModel == SwitchOnCacheMiss) {
 220             DPRINTF(InOrderCPU, "Setting Thread Model to "
 221                     "Switch On Cache Miss\n");
 222         }
 223
 224     } else {
 225         threadModel = Single;
 226     }
 227
 228
 229
 230 #endif
 231
 232     // Bind the fetch & data ports from the resource pool.
 233     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
 234     if (fetchPortIdx == 0) {
 235         fatal("Unable to find port to fetch instructions from.\n");
 236     }
 237
 238     dataPortIdx = resPool->getPortIdx(params->dataMemPort);
 239     if (dataPortIdx == 0) {
 240         fatal("Unable to find port for data.\n");
 241     }
 242
 243     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 244 #if FULL_SYSTEM
 245         // SMT is not supported in FS mode yet.
 246         assert(numThreads == 1);
 247         thread[tid] = new Thread(this, 0);
 248 #else
 249         if (tid < (ThreadID)params->workload.size()) {
 250             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 251                     tid, params->workload[tid]->prog_fname);
 252             thread[tid] =
 253                 new Thread(this, tid, params->workload[tid]);
 254         } else {
 255             //Allocate Empty thread so M5 can use later
 256             //when scheduling threads to CPU
 257             Process* dummy_proc = params->workload[0];
 258             thread[tid] = new Thread(this, tid, dummy_proc);
 259         }
 260 #endif
 261
 262         // Setup the TC that will serve as the interface to the threads/CPU.
 263         InOrderThreadContext *tc = new InOrderThreadContext;
 264         tc->cpu = this;
 265         tc->thread = thread[tid];
 266
 267         // Give the thread the TC.
 268         thread[tid]->tc = tc;
 269         thread[tid]->setFuncExeInst(0);
 270         globalSeqNum[tid] = 1;
 271
 272         // Add the TC to the CPU's list of TC's.
 273         this->threadContexts.push_back(tc);
 274     }
 275
 276     // Initialize TimeBuffer Stage Queues
 277     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 278         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 279         stageQueue[stNum]->id(stNum);
 280     }
 281
 282
 283     // Set Up Pipeline Stages
 284     for (int stNum=0; stNum < NumStages; stNum++) {
 285         if (stNum == 0)
 286             pipelineStage[stNum] = new FirstStage(params, stNum);
 287         else
 288             pipelineStage[stNum] = new PipelineStage(params, stNum);
 289
 290         pipelineStage[stNum]->setCPU(this);
 291         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 292         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 293
 294         // Take Care of 1st/Nth stages
 295         if (stNum > 0)
 296             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 297         if (stNum < NumStages - 1)
 298             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 299     }
 300
 301     // Initialize thread specific variables
 302     for (ThreadID tid = 0; tid < numThreads; tid++) {
 303         archRegDepMap[tid].setCPU(this);
 304
 305         nonSpecInstActive[tid] = false;
 306         nonSpecSeqNum[tid] = 0;
 307
 308         squashSeqNum[tid] = MaxAddr;
 309         lastSquashCycle[tid] = 0;
 310
 311         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 312         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 313         isa[tid].clear();
 314
 315         isa[tid].expandForMultithreading(numThreads, 1/*numVirtProcs*/);
 316     }
 317
 318     lastRunningCycle = curTick;
 319
 320     // Define dummy instructions and resource requests to be used.
 321     dummyInst = new InOrderDynInst(this, NULL, 0, 0);
 322     dummyReq = new ResourceRequest(resPool->getResource(0), NULL, 0, 0, 0, 0);
 323
 324     // Reset CPU to reset state.
 325 #if FULL_SYSTEM
 326     Fault resetFault = new ResetFault();
 327     resetFault->invoke(tcBase());
 328 #else
 329     reset();
 330 #endif
 331
 332     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 333     scheduleTickEvent(0);
 334 }
 335
 336
 337 void
 338 InOrderCPU::regStats()
 339 {
 340     /* Register the Resource Pool's stats here.*/
 341     resPool->regStats();
 342
 343 #ifdef DEBUG
 344     maxResReqCount
 345         .name(name() + ".maxResReqCount")
 346         .desc("Maximum number of live resource requests in CPU")
 347         .prereq(maxResReqCount);
 348 #endif
 349
 350     /* Register any of the InOrderCPU's stats here.*/
 351     timesIdled
 352         .name(name() + ".timesIdled")
 353         .desc("Number of times that the entire CPU went into an idle state and"
 354               " unscheduled itself")
 355         .prereq(timesIdled);
 356
 357     idleCycles
 358         .name(name() + ".idleCycles")
 359         .desc("Total number of cycles that the CPU has spent unscheduled due "
 360               "to idling")
 361         .prereq(idleCycles);
 362
 363     threadCycles
 364         .init(numThreads)
 365         .name(name() + ".threadCycles")
 366         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 367
 368     smtCycles
 369         .name(name() + ".smtCycles")
 370         .desc("Total number of cycles that the CPU was in SMT-mode");
 371
 372     committedInsts
 373         .init(numThreads)
 374         .name(name() + ".committedInsts")
 375         .desc("Number of Instructions Simulated (Per-Thread)");
 376
 377     smtCommittedInsts
 378         .init(numThreads)
 379         .name(name() + ".smtCommittedInsts")
 380         .desc("Number of SMT Instructions Simulated (Per-Thread)");
 381
 382     totalCommittedInsts
 383         .name(name() + ".committedInsts_total")
 384         .desc("Number of Instructions Simulated (Total)");
 385
 386     cpi
 387         .name(name() + ".cpi")
 388         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 389         .precision(6);
 390     cpi = threadCycles / committedInsts;
 391
 392     smtCpi
 393         .name(name() + ".smt_cpi")
 394         .desc("CPI: Total SMT-CPI")
 395         .precision(6);
 396     smtCpi = smtCycles / smtCommittedInsts;
 397
 398     totalCpi
 399         .name(name() + ".cpi_total")
 400         .desc("CPI: Total CPI of All Threads")
 401         .precision(6);
 402     totalCpi = numCycles / totalCommittedInsts;
 403
 404     ipc
 405         .name(name() + ".ipc")
 406         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 407         .precision(6);
 408     ipc =  committedInsts / threadCycles;
 409
 410     smtIpc
 411         .name(name() + ".smt_ipc")
 412         .desc("IPC: Total SMT-IPC")
 413         .precision(6);
 414     smtIpc = smtCommittedInsts / smtCycles;
 415
 416     totalIpc
 417         .name(name() + ".ipc_total")
 418         .desc("IPC: Total IPC of All Threads")
 419         .precision(6);
 420         totalIpc =  totalCommittedInsts / numCycles;
 421
 422     BaseCPU::regStats();
 423 }
 424
 425
 426 void
 427 InOrderCPU::tick()
 428 {
 429     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 430
 431     ++numCycles;
 432
 433     //Tick each of the stages
 434     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 435         pipelineStage[stNum]->tick();
 436     }
 437
 438     // Now advance the time buffers one tick
 439     timeBuffer.advance();
 440     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 441         stageQueue[sqNum]->advance();
 442     }
 443     activityRec.advance();
 444
 445     // Any squashed requests, events, or insts then remove them now
 446     cleanUpRemovedReqs();
 447     cleanUpRemovedEvents();
 448     cleanUpRemovedInsts();
 449
 450     // Re-schedule CPU for this cycle
 451     if (!tickEvent.scheduled()) {
 452         if (_status == SwitchedOut) {
 453             // increment stat
 454             lastRunningCycle = curTick;
 455         } else if (!activityRec.active()) {
 456             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 457             lastRunningCycle = curTick;
 458             timesIdled++;
 459         } else {
 460             //Tick next_tick = curTick + cycles(1);
 461             //tickEvent.schedule(next_tick);
 462             mainEventQueue.schedule(&tickEvent, nextCycle(curTick + 1));
 463             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 464                     nextCycle(curTick + 1));
 465         }
 466     }
 467
 468     tickThreadStats();
 469     updateThreadPriority();
 470 }
 471
 472
 473 void
 474 InOrderCPU::init()
 475 {
 476     if (!deferRegistration) {
 477         registerThreadContexts();
 478     }
 479
 480     // Set inSyscall so that the CPU doesn't squash when initially
 481     // setting up registers.
 482     for (ThreadID tid = 0; tid < numThreads; ++tid)
 483         thread[tid]->inSyscall = true;
 484
 485 #if FULL_SYSTEM
 486     for (ThreadID tid = 0; tid < numThreads; tid++) {
 487         ThreadContext *src_tc = threadContexts[tid];
 488         TheISA::initCPU(src_tc, src_tc->contextId());
 489     }
 490 #endif
 491
 492     // Clear inSyscall.
 493     for (ThreadID tid = 0; tid < numThreads; ++tid)
 494         thread[tid]->inSyscall = false;
 495
 496     // Call Initializiation Routine for Resource Pool
 497     resPool->init();
 498 }
 499
 500 void
 501 InOrderCPU::reset()
 502 {
 503     for (int i = 0; i < numThreads; i++) {
 504         isa[i].reset(coreType, numThreads,
 505                      1/*numVirtProcs*/, dynamic_cast<BaseCPU*>(this));
 506     }
 507 }
 508
 509 Port*
 510 InOrderCPU::getPort(const std::string &if_name, int idx)
 511 {
 512     return resPool->getPort(if_name, idx);
 513 }
 514
 515 #if FULL_SYSTEM
 516 Fault
 517 InOrderCPU::hwrei(ThreadID tid)
 518 {
 519     panic("hwrei: Unimplemented");
 520
 521     return NoFault;
 522 }
 523
 524
 525 bool
 526 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 527 {
 528     panic("simPalCheck: Unimplemented");
 529
 530     return true;
 531 }
 532
 533
 534 Fault
 535 InOrderCPU::getInterrupts()
 536 {
 537     // Check if there are any outstanding interrupts
 538     return this->interrupts->getInterrupt(this->threadContexts[0]);
 539 }
 540
 541
 542 void
 543 InOrderCPU::processInterrupts(Fault interrupt)
 544 {
 545     // Check for interrupts here.  For now can copy the code that
 546     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 547     // is the one that handles the interrupts.
 548     // @todo: Possibly consolidate the interrupt checking code.
 549     // @todo: Allow other threads to handle interrupts.
 550
 551     assert(interrupt != NoFault);
 552     this->interrupts->updateIntrInfo(this->threadContexts[0]);
 553
 554     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 555     this->trap(interrupt, 0);
 556 }
 557
 558
 559 void
 560 InOrderCPU::updateMemPorts()
 561 {
 562     // Update all ThreadContext's memory ports (Functional/Virtual
 563     // Ports)
 564     ThreadID size = thread.size();
 565     for (ThreadID i = 0; i < size; ++i)
 566         thread[i]->connectMemPorts(thread[i]->getTC());
 567 }
 568 #endif
 569
 570 void
 571 InOrderCPU::trap(Fault fault, ThreadID tid, int delay)
 572 {
 573     //@ Squash Pipeline during TRAP
 574     scheduleCpuEvent(Trap, fault, tid, dummyInst, delay);
 575 }
 576
 577 void
 578 InOrderCPU::trapCPU(Fault fault, ThreadID tid)
 579 {
 580     fault->invoke(tcBase(tid));
 581 }
 582
 583 void
 584 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 585 {
 586     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 587 }
 588
 589
 590 void
 591 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid)
 592 {
 593     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 594
 595     // Squash all instructions in each stage including
 596     // instruction that caused the squash (seq_num - 1)
 597     // NOTE: The stage bandwidth needs to be cleared so thats why
 598     //       the stalling instruction is squashed as well. The stalled
 599     //       instruction is previously placed in another intermediate buffer
 600     //       while it's stall is being handled.
 601     InstSeqNum squash_seq_num = seq_num - 1;
 602
 603     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 604         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 605     }
 606 }
 607
 608 void
 609 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 610                              ThreadID tid, DynInstPtr inst,
 611                              unsigned delay, unsigned event_pri_offset)
 612 {
 613     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 614                                        event_pri_offset);
 615
 616     if (delay >= 0) {
 617         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 618                 eventNames[c_event], curTick + delay, tid);
 619         mainEventQueue.schedule(cpu_event,curTick + delay);
 620     } else {
 621         cpu_event->process();
 622         cpuEventRemoveList.push(cpu_event);
 623     }
 624
 625     // Broadcast event to the Resource Pool
 626     // Need to reset tid just in case this is a dummy instruction
 627     inst->setTid(tid);
 628     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 629 }
 630
 631 bool
 632 InOrderCPU::isThreadActive(ThreadID tid)
 633 {
 634   list<ThreadID>::iterator isActive =
 635       std::find(activeThreads.begin(), activeThreads.end(), tid);
 636
 637     return (isActive != activeThreads.end());
 638 }
 639
 640 bool
 641 InOrderCPU::isThreadReady(ThreadID tid)
 642 {
 643   list<ThreadID>::iterator isReady =
 644       std::find(readyThreads.begin(), readyThreads.end(), tid);
 645
 646     return (isReady != readyThreads.end());
 647 }
 648
 649 bool
 650 InOrderCPU::isThreadSuspended(ThreadID tid)
 651 {
 652   list<ThreadID>::iterator isSuspended =
 653       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
 654
 655     return (isSuspended != suspendedThreads.end());
 656 }
 657
 658 void
 659 InOrderCPU::activateNextReadyThread()
 660 {
 661     if (readyThreads.size() >= 1) {
 662         ThreadID ready_tid = readyThreads.front();
 663
 664         // Activate in Pipeline
 665         activateThread(ready_tid);
 666
 667         // Activate in Resource Pool
 668         resPool->activateAll(ready_tid);
 669
 670         list<ThreadID>::iterator ready_it =
 671             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
 672         readyThreads.erase(ready_it);
 673     } else {
 674         DPRINTF(InOrderCPU,
 675                 "Attempting to activate new thread, but No Ready Threads to"
 676                 "activate.\n");
 677     }
 678 }
 679
 680 void
 681 InOrderCPU::activateThread(ThreadID tid)
 682 {
 683     if (isThreadSuspended(tid)) {
 684         DPRINTF(InOrderCPU,
 685                 "Removing [tid:%i] from suspended threads list.\n", tid);
 686
 687         list<ThreadID>::iterator susp_it =
 688             std::find(suspendedThreads.begin(), suspendedThreads.end(),
 689                       tid);
 690         suspendedThreads.erase(susp_it);
 691     }
 692
 693     if (threadModel == SwitchOnCacheMiss &&
 694         numActiveThreads() == 1) {
 695         DPRINTF(InOrderCPU,
 696                 "Ignoring activation of [tid:%i], since [tid:%i] is "
 697                 "already running.\n", tid, activeThreadId());
 698
 699         DPRINTF(InOrderCPU,"Placing [tid:%i] ready threads list\n",
 700                 tid);
 701
 702         readyThreads.push_back(tid);
 703
 704     } else if (!isThreadActive(tid)) {
 705         DPRINTF(InOrderCPU,
 706                 "Adding [tid:%i] to active threads list.\n", tid);
 707         activeThreads.push_back(tid);
 708
 709         wakeCPU();
 710     }
 711 }
 712
 713 void
 714 InOrderCPU::deactivateContext(ThreadID tid, int delay)
 715 {
 716     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
 717
 718     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst, delay);
 719
 720     // Be sure to signal that there's some activity so the CPU doesn't
 721     // deschedule itself.
 722     activityRec.activity();
 723
 724     _status = Running;
 725 }
 726
 727 void
 728 InOrderCPU::deactivateThread(ThreadID tid)
 729 {
 730     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
 731
 732     if (isThreadActive(tid)) {
 733         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
 734                 tid);
 735         list<ThreadID>::iterator thread_it =
 736             std::find(activeThreads.begin(), activeThreads.end(), tid);
 737
 738         removePipelineStalls(*thread_it);
 739
 740         //@TODO: change stage status' to Idle?
 741
 742         activeThreads.erase(thread_it);
 743     }
 744
 745     assert(!isThreadActive(tid));
 746 }
 747
 748 void
 749 InOrderCPU::deallocateContext(ThreadID tid, int delay)
 750 {
 751     DPRINTF(InOrderCPU,"[tid:%i]: Deallocating ...\n", tid);
 752
 753     scheduleCpuEvent(DeallocateThread, NoFault, tid, dummyInst, delay);
 754
 755     // Be sure to signal that there's some activity so the CPU doesn't
 756     // deschedule itself.
 757     activityRec.activity();
 758
 759     _status = Running;
 760 }
 761
 762 void
 763 InOrderCPU::deallocateThread(ThreadID tid)
 764 {
 765     DPRINTF(InOrderCPU, "[tid:%i]: Calling deallocate thread.\n", tid);
 766
 767     if (isThreadActive(tid)) {
 768         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
 769                 tid);
 770         list<ThreadID>::iterator thread_it =
 771             std::find(activeThreads.begin(), activeThreads.end(), tid);
 772
 773         removePipelineStalls(*thread_it);
 774
 775         activeThreads.erase(thread_it);
 776     }
 777
 778     // TODO: "Un"Load/Unmap register file state
 779
 780 }
 781
 782 void
 783 InOrderCPU::removePipelineStalls(ThreadID tid)
 784 {
 785     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
 786             tid);
 787
 788     for (int stNum = 0; stNum < NumStages ; stNum++) {
 789         pipelineStage[stNum]->removeStalls(tid);
 790     }
 791
 792 }
 793
 794 void
 795 InOrderCPU::updateThreadPriority()
 796 {
 797     if (activeThreads.size() > 1)
 798     {
 799         //DEFAULT TO ROUND ROBIN SCHEME
 800         //e.g. Move highest priority to end of thread list
 801         list<ThreadID>::iterator list_begin = activeThreads.begin();
 802         list<ThreadID>::iterator list_end   = activeThreads.end();
 803
 804         unsigned high_thread = *list_begin;
 805
 806         activeThreads.erase(list_begin);
 807
 808         activeThreads.push_back(high_thread);
 809     }
 810 }
 811
 812 inline void
 813 InOrderCPU::tickThreadStats()
 814 {
 815     /** Keep track of cycles that each thread is active */
 816     list<ThreadID>::iterator thread_it = activeThreads.begin();
 817     while (thread_it != activeThreads.end()) {
 818         threadCycles[*thread_it]++;
 819         thread_it++;
 820     }
 821
 822     // Keep track of cycles where SMT is active
 823     if (activeThreads.size() > 1) {
 824         smtCycles++;
 825     }
 826 }
 827
 828 void
 829 InOrderCPU::activateContext(ThreadID tid, int delay)
 830 {
 831     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
 832
 833     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst, delay);
 834
 835     // Be sure to signal that there's some activity so the CPU doesn't
 836     // deschedule itself.
 837     activityRec.activity();
 838
 839     _status = Running;
 840 }
 841
 842 void
 843 InOrderCPU::activateNextReadyContext(int delay)
 844 {
 845     DPRINTF(InOrderCPU,"Activating next ready thread\n");
 846
 847     // NOTE: Add 5 to the event priority so that we always activate
 848     // threads after we've finished deactivating, squashing,etc.
 849     // other threads
 850     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst,
 851                      delay, 5);
 852
 853     // Be sure to signal that there's some activity so the CPU doesn't
 854     // deschedule itself.
 855     activityRec.activity();
 856
 857     _status = Running;
 858 }
 859
 860 void
 861 InOrderCPU::haltContext(ThreadID tid, int delay)
 862 {
 863     suspendContext(tid, delay);
 864 }
 865
 866 void
 867 InOrderCPU::suspendContext(ThreadID tid, int delay)
 868 {
 869     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst, delay);
 870     //_status = Idle;
 871 }
 872
 873 void
 874 InOrderCPU::suspendThread(ThreadID tid)
 875 {
 876     DPRINTF(InOrderCPU, "[tid: %i]: Placing on Suspended Threads List...\n", tid);
 877     deactivateThread(tid);
 878     suspendedThreads.push_back(tid);
 879 }
 880
 881 void
 882 InOrderCPU::squashThreadInPipeline(ThreadID tid)
 883 {
 884     //Squash all instructions in each stage
 885     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 886         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
 887     }
 888 }
 889
 890 PipelineStage*
 891 InOrderCPU::getPipeStage(int stage_num)
 892 {
 893     return pipelineStage[stage_num];
 894 }
 895
 896 uint64_t
 897 InOrderCPU::readPC(ThreadID tid)
 898 {
 899     return PC[tid];
 900 }
 901
 902
 903 void
 904 InOrderCPU::setPC(Addr new_PC, ThreadID tid)
 905 {
 906     PC[tid] = new_PC;
 907 }
 908
 909
 910 uint64_t
 911 InOrderCPU::readNextPC(ThreadID tid)
 912 {
 913     return nextPC[tid];
 914 }
 915
 916
 917 void
 918 InOrderCPU::setNextPC(uint64_t new_NPC, ThreadID tid)
 919 {
 920     nextPC[tid] = new_NPC;
 921 }
 922
 923
 924 uint64_t
 925 InOrderCPU::readNextNPC(ThreadID tid)
 926 {
 927     return nextNPC[tid];
 928 }
 929
 930
 931 void
 932 InOrderCPU::setNextNPC(uint64_t new_NNPC, ThreadID tid)
 933 {
 934     nextNPC[tid] = new_NNPC;
 935 }
 936
 937 uint64_t
 938 InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
 939 {
 940     return intRegs[tid][reg_idx];
 941 }
 942
 943 FloatReg
 944 InOrderCPU::readFloatReg(int reg_idx, ThreadID tid)
 945 {
 946     return floatRegs.f[tid][reg_idx];
 947 }
 948
 949 FloatRegBits
 950 InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
 951 {;
 952     return floatRegs.i[tid][reg_idx];
 953 }
 954
 955 void
 956 InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
 957 {
 958     intRegs[tid][reg_idx] = val;
 959 }
 960
 961
 962 void
 963 InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid)
 964 {
 965     floatRegs.f[tid][reg_idx] = val;
 966 }
 967
 968
 969 void
 970 InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid)
 971 {
 972     floatRegs.i[tid][reg_idx] = val;
 973 }
 974
 975 uint64_t
 976 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
 977 {
 978     // If Default value is set, then retrieve target thread
 979     if (tid == InvalidThreadID) {
 980         tid = TheISA::getTargetThread(tcBase(tid));
 981     }
 982
 983     if (reg_idx < FP_Base_DepTag) {
 984         // Integer Register File
 985         return readIntReg(reg_idx, tid);
 986     } else if (reg_idx < Ctrl_Base_DepTag) {
 987         // Float Register File
 988         reg_idx -= FP_Base_DepTag;
 989         return readFloatRegBits(reg_idx, tid);
 990     } else {
 991         reg_idx -= Ctrl_Base_DepTag;
 992         return readMiscReg(reg_idx, tid);  // Misc. Register File
 993     }
 994 }
 995 void
 996 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
 997                               ThreadID tid)
 998 {
 999     // If Default value is set, then retrieve target thread
1000     if (tid == InvalidThreadID) {
1001         tid = TheISA::getTargetThread(tcBase(tid));
1002     }
1003
1004     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1005         setIntReg(reg_idx, val, tid);
1006     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1007         reg_idx -= FP_Base_DepTag;
1008         setFloatRegBits(reg_idx, val, tid);
1009     } else {
1010         reg_idx -= Ctrl_Base_DepTag;
1011         setMiscReg(reg_idx, val, tid); // Misc. Register File
1012     }
1013 }
1014
1015 MiscReg
1016 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1017 {
1018     return isa[tid].readMiscRegNoEffect(misc_reg);
1019 }
1020
1021 MiscReg
1022 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1023 {
1024     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1025 }
1026
1027 void
1028 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1029 {
1030     isa[tid].setMiscRegNoEffect(misc_reg, val);
1031 }
1032
1033 void
1034 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1035 {
1036     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1037 }
1038
1039
1040 InOrderCPU::ListIt
1041 InOrderCPU::addInst(DynInstPtr &inst)
1042 {
1043     ThreadID tid = inst->readTid();
1044
1045     instList[tid].push_back(inst);
1046
1047     return --(instList[tid].end());
1048 }
1049
1050 void
1051 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1052 {
1053     // Set the CPU's PCs - This contributes to the precise state of the CPU
1054     // which can be used when restoring a thread to the CPU after a fork or
1055     // after an exception
1056     // =================
1057     // @TODO: Set-Up Grad-Info/Committed-Info to let ThreadState know if
1058     // it's a branch or not
1059     setPC(inst->readPC(), tid);
1060     setNextPC(inst->readNextPC(), tid);
1061     setNextNPC(inst->readNextNPC(), tid);
1062
1063     // Finalize Trace Data For Instruction
1064     if (inst->traceData) {
1065         //inst->traceData->setCycle(curTick);
1066         inst->traceData->setFetchSeq(inst->seqNum);
1067         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1068         inst->traceData->dump();
1069         delete inst->traceData;
1070         inst->traceData = NULL;
1071     }
1072
1073     // Set Last Graduated Instruction In Thread State
1074     //thread[tid]->lastGradInst = inst;
1075
1076     // Increment thread-state's instruction count
1077     thread[tid]->numInst++;
1078
1079     // Increment thread-state's instruction stats
1080     thread[tid]->numInsts++;
1081
1082     // Count committed insts per thread stats
1083     committedInsts[tid]++;
1084
1085     // Count total insts committed stat
1086     totalCommittedInsts++;
1087
1088     // Count SMT-committed insts per thread stat
1089     if (numActiveThreads() > 1) {
1090         smtCommittedInsts[tid]++;
1091     }
1092
1093     // Check for instruction-count-based events.
1094     comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1095
1096     // Broadcast to other resources an instruction
1097     // has been completed
1098     resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
1099                            tid);
1100
1101     // Finally, remove instruction from CPU
1102     removeInst(inst);
1103 }
1104
1105 void
1106 InOrderCPU::addToRemoveList(DynInstPtr &inst)
1107 {
1108     removeInstsThisCycle = true;
1109
1110     removeList.push(inst->getInstListIt());
1111 }
1112
1113 void
1114 InOrderCPU::removeInst(DynInstPtr &inst)
1115 {
1116     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %#x "
1117             "[sn:%lli]\n",
1118             inst->threadNumber, inst->readPC(), inst->seqNum);
1119
1120     removeInstsThisCycle = true;
1121
1122     // Remove the instruction.
1123     removeList.push(inst->getInstListIt());
1124 }
1125
1126 void
1127 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1128 {
1129     //assert(!instList[tid].empty());
1130
1131     removeInstsThisCycle = true;
1132
1133     ListIt inst_iter = instList[tid].end();
1134
1135     inst_iter--;
1136
1137     DPRINTF(InOrderCPU, "Deleting instructions from CPU instruction "
1138             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1139             tid, seq_num, (*inst_iter)->seqNum);
1140
1141     while ((*inst_iter)->seqNum > seq_num) {
1142
1143         bool break_loop = (inst_iter == instList[tid].begin());
1144
1145         squashInstIt(inst_iter, tid);
1146
1147         inst_iter--;
1148
1149         if (break_loop)
1150             break;
1151     }
1152 }
1153
1154
1155 inline void
1156 InOrderCPU::squashInstIt(const ListIt &instIt, ThreadID tid)
1157 {
1158     if ((*instIt)->threadNumber == tid) {
1159         DPRINTF(InOrderCPU, "Squashing instruction, "
1160                 "[tid:%i] [sn:%lli] PC %#x\n",
1161                 (*instIt)->threadNumber,
1162                 (*instIt)->seqNum,
1163                 (*instIt)->readPC());
1164
1165         (*instIt)->setSquashed();
1166
1167         removeList.push(instIt);
1168     }
1169 }
1170
1171
1172 void
1173 InOrderCPU::cleanUpRemovedInsts()
1174 {
1175     while (!removeList.empty()) {
1176         DPRINTF(InOrderCPU, "Removing instruction, "
1177                 "[tid:%i] [sn:%lli] PC %#x\n",
1178                 (*removeList.front())->threadNumber,
1179                 (*removeList.front())->seqNum,
1180                 (*removeList.front())->readPC());
1181
1182         DynInstPtr inst = *removeList.front();
1183         ThreadID tid = inst->threadNumber;
1184
1185         // Make Sure Resource Schedule Is Emptied Out
1186         ThePipeline::ResSchedule *inst_sched = &inst->resSched;
1187         while (!inst_sched->empty()) {
1188             ThePipeline::ScheduleEntry* sch_entry = inst_sched->top();
1189             inst_sched->pop();
1190             delete sch_entry;
1191         }
1192
1193         // Remove From Register Dependency Map, If Necessary
1194         archRegDepMap[(*removeList.front())->threadNumber].
1195             remove((*removeList.front()));
1196
1197
1198         // Clear if Non-Speculative
1199         if (inst->staticInst &&
1200               inst->seqNum == nonSpecSeqNum[tid] &&
1201                 nonSpecInstActive[tid] == true) {
1202             nonSpecInstActive[tid] = false;
1203         }
1204
1205         instList[tid].erase(removeList.front());
1206
1207         removeList.pop();
1208
1209         DPRINTF(RefCount, "pop from remove list: [sn:%i]: Refcount = %i.\n",
1210                 inst->seqNum,
1211                 0/*inst->curCount()*/);
1212
1213     }
1214
1215     removeInstsThisCycle = false;
1216 }
1217
1218 void
1219 InOrderCPU::cleanUpRemovedReqs()
1220 {
1221     while (!reqRemoveList.empty()) {
1222         ResourceRequest *res_req = reqRemoveList.front();
1223
1224         DPRINTF(RefCount, "[tid:%i]: Removing Request, "
1225                 "[sn:%lli] [slot:%i] [stage_num:%i] [res:%s] [refcount:%i].\n",
1226                 res_req->inst->threadNumber,
1227                 res_req->inst->seqNum,
1228                 res_req->getSlot(),
1229                 res_req->getStageNum(),
1230                 res_req->res->name(),
1231                 0/*res_req->inst->curCount()*/);
1232
1233         reqRemoveList.pop();
1234
1235         delete res_req;
1236
1237         DPRINTF(RefCount, "after remove request: [sn:%i]: Refcount = %i.\n",
1238                 res_req->inst->seqNum,
1239                 0/*res_req->inst->curCount()*/);
1240     }
1241 }
1242
1243 void
1244 InOrderCPU::cleanUpRemovedEvents()
1245 {
1246     while (!cpuEventRemoveList.empty()) {
1247         Event *cpu_event = cpuEventRemoveList.front();
1248         cpuEventRemoveList.pop();
1249         delete cpu_event;
1250     }
1251 }
1252
1253
1254 void
1255 InOrderCPU::dumpInsts()
1256 {
1257     int num = 0;
1258
1259     ListIt inst_list_it = instList[0].begin();
1260
1261     cprintf("Dumping Instruction List\n");
1262
1263     while (inst_list_it != instList[0].end()) {
1264         cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1265                 "Squashed:%i\n\n",
1266                 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
1267                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1268                 (*inst_list_it)->isSquashed());
1269         inst_list_it++;
1270         ++num;
1271     }
1272 }
1273
1274 void
1275 InOrderCPU::wakeCPU()
1276 {
1277     if (/*activityRec.active() || */tickEvent.scheduled()) {
1278         DPRINTF(Activity, "CPU already running.\n");
1279         return;
1280     }
1281
1282     DPRINTF(Activity, "Waking up CPU\n");
1283
1284     //@todo: figure out how to count idleCycles correctly
1285     //idleCycles += (curTick - 1) - lastRunningCycle;
1286
1287     mainEventQueue.schedule(&tickEvent, curTick);
1288 }
1289
1290 #if FULL_SYSTEM
1291
1292 void
1293 InOrderCPU::wakeup()
1294 {
1295     if (this->thread[0]->status() != ThreadContext::Suspended)
1296         return;
1297
1298     this->wakeCPU();
1299
1300     DPRINTF(Quiesce, "Suspended Processor woken\n");
1301     this->threadContexts[0]->activate();
1302 }
1303 #endif
1304
1305 #if !FULL_SYSTEM
1306 void
1307 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1308 {
1309     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1310
1311     DPRINTF(Activity,"Activity: syscall() called.\n");
1312
1313     // Temporarily increase this by one to account for the syscall
1314     // instruction.
1315     ++(this->thread[tid]->funcExeInst);
1316
1317     // Execute the actual syscall.
1318     this->thread[tid]->syscall(callnum);
1319
1320     // Decrease funcExeInst by one as the normal commit will handle
1321     // incrementing it.
1322     --(this->thread[tid]->funcExeInst);
1323
1324     // Clear Non-Speculative Block Variable
1325     nonSpecInstActive[tid] = false;
1326 }
1327 #endif
1328
1329 void
1330 InOrderCPU::prefetch(DynInstPtr inst)
1331 {
1332     Resource *mem_res = resPool->getResource(dataPortIdx);
1333     return mem_res->prefetch(inst);
1334 }
1335
1336 void
1337 InOrderCPU::writeHint(DynInstPtr inst)
1338 {
1339     Resource *mem_res = resPool->getResource(dataPortIdx);
1340     return mem_res->writeHint(inst);
1341 }
1342
1343
1344 TheISA::TLB*
1345 InOrderCPU::getITBPtr()
1346 {
1347     CacheUnit *itb_res =
1348         dynamic_cast<CacheUnit*>(resPool->getResource(fetchPortIdx));
1349     return itb_res->tlb();
1350 }
1351
1352
1353 TheISA::TLB*
1354 InOrderCPU::getDTBPtr()
1355 {
1356     CacheUnit *dtb_res =
1357         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1358     return dtb_res->tlb();
1359 }
1360
1361 template <class T>
1362 Fault
1363 InOrderCPU::read(DynInstPtr inst, Addr addr, T &data, unsigned flags)
1364 {
1365     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1366     //       you want to run w/out caches?
1367     CacheUnit *cache_res =
1368         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1369
1370     return cache_res->read(inst, addr, data, flags);
1371 }
1372
1373 #ifndef DOXYGEN_SHOULD_SKIP_THIS
1374
1375 template
1376 Fault
1377 InOrderCPU::read(DynInstPtr inst, Addr addr, Twin32_t &data, unsigned flags);
1378
1379 template
1380 Fault
1381 InOrderCPU::read(DynInstPtr inst, Addr addr, Twin64_t &data, unsigned flags);
1382
1383 template
1384 Fault
1385 InOrderCPU::read(DynInstPtr inst, Addr addr, uint64_t &data, unsigned flags);
1386
1387 template
1388 Fault
1389 InOrderCPU::read(DynInstPtr inst, Addr addr, uint32_t &data, unsigned flags);
1390
1391 template
1392 Fault
1393 InOrderCPU::read(DynInstPtr inst, Addr addr, uint16_t &data, unsigned flags);
1394
1395 template
1396 Fault
1397 InOrderCPU::read(DynInstPtr inst, Addr addr, uint8_t &data, unsigned flags);
1398
1399 #endif //DOXYGEN_SHOULD_SKIP_THIS
1400
1401 template<>
1402 Fault
1403 InOrderCPU::read(DynInstPtr inst, Addr addr, double &data, unsigned flags)
1404 {
1405     return read(inst, addr, *(uint64_t*)&data, flags);
1406 }
1407
1408 template<>
1409 Fault
1410 InOrderCPU::read(DynInstPtr inst, Addr addr, float &data, unsigned flags)
1411 {
1412     return read(inst, addr, *(uint32_t*)&data, flags);
1413 }
1414
1415
1416 template<>
1417 Fault
1418 InOrderCPU::read(DynInstPtr inst, Addr addr, int32_t &data, unsigned flags)
1419 {
1420     return read(inst, addr, (uint32_t&)data, flags);
1421 }
1422
1423 template <class T>
1424 Fault
1425 InOrderCPU::write(DynInstPtr inst, T data, Addr addr, unsigned flags,
1426                   uint64_t *write_res)
1427 {
1428     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1429     //       you want to run w/out caches?
1430     CacheUnit *cache_res =
1431         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1432     return cache_res->write(inst, data, addr, flags, write_res);
1433 }
1434
1435 #ifndef DOXYGEN_SHOULD_SKIP_THIS
1436
1437 template
1438 Fault
1439 InOrderCPU::write(DynInstPtr inst, Twin32_t data, Addr addr,
1440                        unsigned flags, uint64_t *res);
1441
1442 template
1443 Fault
1444 InOrderCPU::write(DynInstPtr inst, Twin64_t data, Addr addr,
1445                        unsigned flags, uint64_t *res);
1446
1447 template
1448 Fault
1449 InOrderCPU::write(DynInstPtr inst, uint64_t data, Addr addr,
1450                        unsigned flags, uint64_t *res);
1451
1452 template
1453 Fault
1454 InOrderCPU::write(DynInstPtr inst, uint32_t data, Addr addr,
1455                        unsigned flags, uint64_t *res);
1456
1457 template
1458 Fault
1459 InOrderCPU::write(DynInstPtr inst, uint16_t data, Addr addr,
1460                        unsigned flags, uint64_t *res);
1461
1462 template
1463 Fault
1464 InOrderCPU::write(DynInstPtr inst, uint8_t data, Addr addr,
1465                        unsigned flags, uint64_t *res);
1466
1467 #endif //DOXYGEN_SHOULD_SKIP_THIS
1468
1469 template<>
1470 Fault
1471 InOrderCPU::write(DynInstPtr inst, double data, Addr addr, unsigned flags,
1472                   uint64_t *res)
1473 {
1474     return write(inst, *(uint64_t*)&data, addr, flags, res);
1475 }
1476
1477 template<>
1478 Fault
1479 InOrderCPU::write(DynInstPtr inst, float data, Addr addr, unsigned flags,
1480                   uint64_t *res)
1481 {
1482     return write(inst, *(uint32_t*)&data, addr, flags, res);
1483 }
1484
1485
1486 template<>
1487 Fault
1488 InOrderCPU::write(DynInstPtr inst, int32_t data, Addr addr, unsigned flags,
1489                   uint64_t *res)
1490 {
1491     return write(inst, (uint32_t)data, addr, flags, res);
1492 }