src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <algorithm>
  33
  34 #include "arch/utility.hh"
  35 #include "base/bigint.hh"
  36 #include "config/full_system.hh"
  37 #include "config/the_isa.hh"
  38 #include "cpu/inorder/resources/resource_list.hh"
  39 #include "cpu/inorder/cpu.hh"
  40 #include "cpu/inorder/first_stage.hh"
  41 #include "cpu/inorder/inorder_dyn_inst.hh"
  42 #include "cpu/inorder/pipeline_traits.hh"
  43 #include "cpu/inorder/resource_pool.hh"
  44 #include "cpu/inorder/thread_context.hh"
  45 #include "cpu/inorder/thread_state.hh"
  46 #include "cpu/activity.hh"
  47 #include "cpu/base.hh"
  48 #include "cpu/exetrace.hh"
  49 #include "cpu/simple_thread.hh"
  50 #include "cpu/thread_context.hh"
  51 #include "debug/Activity.hh"
  52 #include "debug/InOrderCPU.hh"
  53 #include "debug/RefCount.hh"
  54 #include "debug/SkedCache.hh"
  55 #include "mem/translating_port.hh"
  56 #include "params/InOrderCPU.hh"
  57 #include "sim/process.hh"
  58 #include "sim/stat_control.hh"
  59
  60 #if FULL_SYSTEM
  61 #include "cpu/quiesce_event.hh"
  62 #include "sim/system.hh"
  63 #endif
  64
  65 #if THE_ISA == ALPHA_ISA
  66 #include "arch/alpha/osfpal.hh"
  67 #endif
  68
  69 using namespace std;
  70 using namespace TheISA;
  71 using namespace ThePipeline;
  72
  73 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
  74   : Event(CPU_Tick_Pri), cpu(c)
  75 { }
  76
  77
  78 void
  79 InOrderCPU::TickEvent::process()
  80 {
  81     cpu->tick();
  82 }
  83
  84
  85 const char *
  86 InOrderCPU::TickEvent::description()
  87 {
  88     return "InOrderCPU tick event";
  89 }
  90
  91 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
  92                                Fault fault, ThreadID _tid, DynInstPtr inst,
  93                                unsigned event_pri_offset)
  94     : Event(Event::Priority((unsigned int)CPU_Tick_Pri + event_pri_offset)),
  95       cpu(_cpu)
  96 {
  97     setEvent(e_type, fault, _tid, inst);
  98 }
  99
 100
 101 std::string InOrderCPU::eventNames[NumCPUEvents] =
 102 {
 103     "ActivateThread",
 104     "ActivateNextReadyThread",
 105     "DeactivateThread",
 106     "HaltThread",
 107     "SuspendThread",
 108     "Trap",
 109     "InstGraduated",
 110     "SquashFromMemStall",
 111     "UpdatePCs"
 112 };
 113
 114 void
 115 InOrderCPU::CPUEvent::process()
 116 {
 117     switch (cpuEventType)
 118     {
 119       case ActivateThread:
 120         cpu->activateThread(tid);
 121         break;
 122
 123       case ActivateNextReadyThread:
 124         cpu->activateNextReadyThread();
 125         break;
 126
 127       case DeactivateThread:
 128         cpu->deactivateThread(tid);
 129         break;
 130
 131       case HaltThread:
 132         cpu->haltThread(tid);
 133         break;
 134
 135       case SuspendThread:
 136         cpu->suspendThread(tid);
 137         break;
 138
 139       case SquashFromMemStall:
 140         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 141         break;
 142
 143       case Trap:
 144         cpu->trapCPU(fault, tid, inst);
 145         break;
 146
 147       default:
 148         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 149     }
 150
 151     cpu->cpuEventRemoveList.push(this);
 152 }
 153
 154
 155
 156 const char *
 157 InOrderCPU::CPUEvent::description()
 158 {
 159     return "InOrderCPU event";
 160 }
 161
 162 void
 163 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 164 {
 165     assert(!scheduled() || squashed());
 166     cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
 167 }
 168
 169 void
 170 InOrderCPU::CPUEvent::unscheduleEvent()
 171 {
 172     if (scheduled())
 173         squash();
 174 }
 175
 176 InOrderCPU::InOrderCPU(Params *params)
 177     : BaseCPU(params),
 178       cpu_id(params->cpu_id),
 179       coreType("default"),
 180       _status(Idle),
 181       tickEvent(this),
 182       stageWidth(params->stageWidth),
 183       timeBuffer(2 , 2),
 184       removeInstsThisCycle(false),
 185       activityRec(params->name, NumStages, 10, params->activity),
 186 #if FULL_SYSTEM
 187       system(params->system),
 188       physmem(system->physmem),
 189 #endif // FULL_SYSTEM
 190 #ifdef DEBUG
 191       cpuEventNum(0),
 192       resReqCount(0),
 193 #endif // DEBUG
 194       switchCount(0),
 195       deferRegistration(false/*params->deferRegistration*/),
 196       stageTracing(params->stageTracing),
 197       instsPerSwitch(0)
 198 {
 199     ThreadID active_threads;
 200     cpu_params = params;
 201
 202     resPool = new ResourcePool(this, params);
 203
 204     // Resize for Multithreading CPUs
 205     thread.resize(numThreads);
 206
 207 #if FULL_SYSTEM
 208     active_threads = 1;
 209 #else
 210     active_threads = params->workload.size();
 211
 212     if (active_threads > MaxThreads) {
 213         panic("Workload Size too large. Increase the 'MaxThreads'"
 214               "in your InOrder implementation or "
 215               "edit your workload size.");
 216     }
 217
 218
 219     if (active_threads > 1) {
 220         threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 221
 222         if (threadModel == SMT) {
 223             DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 224         } else if (threadModel == SwitchOnCacheMiss) {
 225             DPRINTF(InOrderCPU, "Setting Thread Model to "
 226                     "Switch On Cache Miss\n");
 227         }
 228
 229     } else {
 230         threadModel = Single;
 231     }
 232
 233
 234
 235 #endif
 236
 237     // Bind the fetch & data ports from the resource pool.
 238     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
 239     if (fetchPortIdx == 0) {
 240         fatal("Unable to find port to fetch instructions from.\n");
 241     }
 242
 243     dataPortIdx = resPool->getPortIdx(params->dataMemPort);
 244     if (dataPortIdx == 0) {
 245         fatal("Unable to find port for data.\n");
 246     }
 247
 248     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 249 #if FULL_SYSTEM
 250         // SMT is not supported in FS mode yet.
 251         assert(numThreads == 1);
 252         thread[tid] = new Thread(this, 0);
 253 #else
 254         if (tid < (ThreadID)params->workload.size()) {
 255             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 256                     tid, params->workload[tid]->prog_fname);
 257             thread[tid] =
 258                 new Thread(this, tid, params->workload[tid]);
 259         } else {
 260             //Allocate Empty thread so M5 can use later
 261             //when scheduling threads to CPU
 262             Process* dummy_proc = params->workload[0];
 263             thread[tid] = new Thread(this, tid, dummy_proc);
 264         }
 265
 266         // Eventually set this with parameters...
 267         asid[tid] = tid;
 268 #endif
 269
 270         // Setup the TC that will serve as the interface to the threads/CPU.
 271         InOrderThreadContext *tc = new InOrderThreadContext;
 272         tc->cpu = this;
 273         tc->thread = thread[tid];
 274
 275         // Give the thread the TC.
 276         thread[tid]->tc = tc;
 277         thread[tid]->setFuncExeInst(0);
 278         globalSeqNum[tid] = 1;
 279
 280         // Add the TC to the CPU's list of TC's.
 281         this->threadContexts.push_back(tc);
 282     }
 283
 284     // Initialize TimeBuffer Stage Queues
 285     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 286         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 287         stageQueue[stNum]->id(stNum);
 288     }
 289
 290
 291     // Set Up Pipeline Stages
 292     for (int stNum=0; stNum < NumStages; stNum++) {
 293         if (stNum == 0)
 294             pipelineStage[stNum] = new FirstStage(params, stNum);
 295         else
 296             pipelineStage[stNum] = new PipelineStage(params, stNum);
 297
 298         pipelineStage[stNum]->setCPU(this);
 299         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 300         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 301
 302         // Take Care of 1st/Nth stages
 303         if (stNum > 0)
 304             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 305         if (stNum < NumStages - 1)
 306             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 307     }
 308
 309     // Initialize thread specific variables
 310     for (ThreadID tid = 0; tid < numThreads; tid++) {
 311         archRegDepMap[tid].setCPU(this);
 312
 313         nonSpecInstActive[tid] = false;
 314         nonSpecSeqNum[tid] = 0;
 315
 316         squashSeqNum[tid] = MaxAddr;
 317         lastSquashCycle[tid] = 0;
 318
 319         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 320         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 321         isa[tid].clear();
 322
 323         // Define dummy instructions and resource requests to be used.
 324         dummyInst[tid] = new InOrderDynInst(this,
 325                                             thread[tid],
 326                                             0,
 327                                             tid,
 328                                             asid[tid]);
 329
 330         dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
 331     }
 332
 333     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 334     dummyReqInst->setSquashed();
 335     dummyReqInst->resetInstCount();
 336
 337     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 338     dummyBufferInst->setSquashed();
 339     dummyBufferInst->resetInstCount();
 340
 341     endOfSkedIt = skedCache.end();
 342     frontEndSked = createFrontEndSked();
 343
 344     lastRunningCycle = curTick();
 345
 346     // Reset CPU to reset state.
 347 #if FULL_SYSTEM
 348     Fault resetFault = new ResetFault();
 349     resetFault->invoke(tcBase());
 350 #endif
 351
 352
 353     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 354     scheduleTickEvent(0);
 355 }
 356
 357 InOrderCPU::~InOrderCPU()
 358 {
 359     delete resPool;
 360
 361     std::map<SkedID, ThePipeline::RSkedPtr>::iterator sked_it =
 362         skedCache.begin();
 363     std::map<SkedID, ThePipeline::RSkedPtr>::iterator sked_end =
 364         skedCache.end();
 365
 366     while (sked_it != sked_end) {
 367         delete (*sked_it).second;
 368         sked_it++;
 369     }
 370     skedCache.clear();
 371 }
 372
 373 std::map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
 374
 375 RSkedPtr
 376 InOrderCPU::createFrontEndSked()
 377 {
 378     RSkedPtr res_sked = new ResourceSked();
 379     int stage_num = 0;
 380     StageScheduler F(res_sked, stage_num++);
 381     StageScheduler D(res_sked, stage_num++);
 382
 383     // FETCH
 384     F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
 385     F.needs(ICache, FetchUnit::InitiateFetch);
 386
 387     // DECODE
 388     D.needs(ICache, FetchUnit::CompleteFetch);
 389     D.needs(Decode, DecodeUnit::DecodeInst);
 390     D.needs(BPred, BranchPredictor::PredictBranch);
 391     D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
 392
 393
 394     DPRINTF(SkedCache, "Resource Sked created for instruction \"front_end\"\n");
 395
 396     return res_sked;
 397 }
 398
 399 RSkedPtr
 400 InOrderCPU::createBackEndSked(DynInstPtr inst)
 401 {
 402     RSkedPtr res_sked = lookupSked(inst);
 403     if (res_sked != NULL) {
 404         DPRINTF(SkedCache, "Found %s in sked cache.\n",
 405                 inst->instName());
 406         return res_sked;
 407     } else {
 408         res_sked = new ResourceSked();
 409     }
 410
 411     int stage_num = ThePipeline::BackEndStartStage;
 412     StageScheduler X(res_sked, stage_num++);
 413     StageScheduler M(res_sked, stage_num++);
 414     StageScheduler W(res_sked, stage_num++);
 415
 416     if (!inst->staticInst) {
 417         warn_once("Static Instruction Object Not Set. Can't Create"
 418                   " Back End Schedule");
 419         return NULL;
 420     }
 421
 422     // EXECUTE
 423     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 424         if (!idx || !inst->isStore()) {
 425             X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
 426         }
 427     }
 428
 429     if ( inst->isNonSpeculative() ) {
 430         // skip execution of non speculative insts until later
 431     } else if ( inst->isMemRef() ) {
 432         if ( inst->isLoad() ) {
 433             X.needs(AGEN, AGENUnit::GenerateAddr);
 434         }
 435     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 436         X.needs(MDU, MultDivUnit::StartMultDiv);
 437     } else {
 438         X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 439     }
 440
 441     if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 442         X.needs(MDU, MultDivUnit::EndMultDiv);
 443     }
 444
 445     // MEMORY
 446     if ( inst->isLoad() ) {
 447         M.needs(DCache, CacheUnit::InitiateReadData);
 448     } else if ( inst->isStore() ) {
 449         if ( inst->numSrcRegs() >= 2 ) {
 450             M.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 451         }
 452         M.needs(AGEN, AGENUnit::GenerateAddr);
 453         M.needs(DCache, CacheUnit::InitiateWriteData);
 454     }
 455
 456
 457     // WRITEBACK
 458     if ( inst->isLoad() ) {
 459         W.needs(DCache, CacheUnit::CompleteReadData);
 460     } else if ( inst->isStore() ) {
 461         W.needs(DCache, CacheUnit::CompleteWriteData);
 462     }
 463
 464     if ( inst->isNonSpeculative() ) {
 465         if ( inst->isMemRef() ) fatal("Non-Speculative Memory Instruction");
 466         W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 467     }
 468
 469     W.needs(Grad, GraduationUnit::GraduateInst);
 470
 471     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 472         W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
 473     }
 474
 475     // Insert Back Schedule into our cache of
 476     // resource schedules
 477     addToSkedCache(inst, res_sked);
 478
 479     DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
 480             inst->instName(), inst->getMachInst());
 481     res_sked->print();
 482
 483     return res_sked;
 484 }
 485
 486 void
 487 InOrderCPU::regStats()
 488 {
 489     /* Register the Resource Pool's stats here.*/
 490     resPool->regStats();
 491
 492     /* Register for each Pipeline Stage */
 493     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 494         pipelineStage[stage_num]->regStats();
 495     }
 496
 497     /* Register any of the InOrderCPU's stats here.*/
 498     instsPerCtxtSwitch
 499         .name(name() + ".instsPerContextSwitch")
 500         .desc("Instructions Committed Per Context Switch")
 501         .prereq(instsPerCtxtSwitch);
 502
 503     numCtxtSwitches
 504         .name(name() + ".contextSwitches")
 505         .desc("Number of context switches");
 506
 507     comLoads
 508         .name(name() + ".comLoads")
 509         .desc("Number of Load instructions committed");
 510
 511     comStores
 512         .name(name() + ".comStores")
 513         .desc("Number of Store instructions committed");
 514
 515     comBranches
 516         .name(name() + ".comBranches")
 517         .desc("Number of Branches instructions committed");
 518
 519     comNops
 520         .name(name() + ".comNops")
 521         .desc("Number of Nop instructions committed");
 522
 523     comNonSpec
 524         .name(name() + ".comNonSpec")
 525         .desc("Number of Non-Speculative instructions committed");
 526
 527     comInts
 528         .name(name() + ".comInts")
 529         .desc("Number of Integer instructions committed");
 530
 531     comFloats
 532         .name(name() + ".comFloats")
 533         .desc("Number of Floating Point instructions committed");
 534
 535     timesIdled
 536         .name(name() + ".timesIdled")
 537         .desc("Number of times that the entire CPU went into an idle state and"
 538               " unscheduled itself")
 539         .prereq(timesIdled);
 540
 541     idleCycles
 542         .name(name() + ".idleCycles")
 543         .desc("Number of cycles cpu's stages were not processed");
 544
 545     runCycles
 546         .name(name() + ".runCycles")
 547         .desc("Number of cycles cpu stages are processed.");
 548
 549     activity
 550         .name(name() + ".activity")
 551         .desc("Percentage of cycles cpu is active")
 552         .precision(6);
 553     activity = (runCycles / numCycles) * 100;
 554
 555     threadCycles
 556         .init(numThreads)
 557         .name(name() + ".threadCycles")
 558         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 559
 560     smtCycles
 561         .name(name() + ".smtCycles")
 562         .desc("Total number of cycles that the CPU was in SMT-mode");
 563
 564     committedInsts
 565         .init(numThreads)
 566         .name(name() + ".committedInsts")
 567         .desc("Number of Instructions Simulated (Per-Thread)");
 568
 569     smtCommittedInsts
 570         .init(numThreads)
 571         .name(name() + ".smtCommittedInsts")
 572         .desc("Number of SMT Instructions Simulated (Per-Thread)");
 573
 574     totalCommittedInsts
 575         .name(name() + ".committedInsts_total")
 576         .desc("Number of Instructions Simulated (Total)");
 577
 578     cpi
 579         .name(name() + ".cpi")
 580         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 581         .precision(6);
 582     cpi = numCycles / committedInsts;
 583
 584     smtCpi
 585         .name(name() + ".smt_cpi")
 586         .desc("CPI: Total SMT-CPI")
 587         .precision(6);
 588     smtCpi = smtCycles / smtCommittedInsts;
 589
 590     totalCpi
 591         .name(name() + ".cpi_total")
 592         .desc("CPI: Total CPI of All Threads")
 593         .precision(6);
 594     totalCpi = numCycles / totalCommittedInsts;
 595
 596     ipc
 597         .name(name() + ".ipc")
 598         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 599         .precision(6);
 600     ipc =  committedInsts / numCycles;
 601
 602     smtIpc
 603         .name(name() + ".smt_ipc")
 604         .desc("IPC: Total SMT-IPC")
 605         .precision(6);
 606     smtIpc = smtCommittedInsts / smtCycles;
 607
 608     totalIpc
 609         .name(name() + ".ipc_total")
 610         .desc("IPC: Total IPC of All Threads")
 611         .precision(6);
 612         totalIpc =  totalCommittedInsts / numCycles;
 613
 614     BaseCPU::regStats();
 615 }
 616
 617
 618 void
 619 InOrderCPU::tick()
 620 {
 621     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 622
 623     ++numCycles;
 624
 625     bool pipes_idle = true;
 626
 627     //Tick each of the stages
 628     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 629         pipelineStage[stNum]->tick();
 630
 631         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 632     }
 633
 634     if (pipes_idle)
 635         idleCycles++;
 636     else
 637         runCycles++;
 638
 639     // Now advance the time buffers one tick
 640     timeBuffer.advance();
 641     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 642         stageQueue[sqNum]->advance();
 643     }
 644     activityRec.advance();
 645
 646     // Any squashed events, or insts then remove them now
 647     cleanUpRemovedEvents();
 648     cleanUpRemovedInsts();
 649
 650     // Re-schedule CPU for this cycle
 651     if (!tickEvent.scheduled()) {
 652         if (_status == SwitchedOut) {
 653             // increment stat
 654             lastRunningCycle = curTick();
 655         } else if (!activityRec.active()) {
 656             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 657             lastRunningCycle = curTick();
 658             timesIdled++;
 659         } else {
 660             //Tick next_tick = curTick() + cycles(1);
 661             //tickEvent.schedule(next_tick);
 662             schedule(&tickEvent, nextCycle(curTick() + 1));
 663             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 664                     nextCycle(curTick() + 1));
 665         }
 666     }
 667
 668     tickThreadStats();
 669     updateThreadPriority();
 670 }
 671
 672
 673 void
 674 InOrderCPU::init()
 675 {
 676     if (!deferRegistration) {
 677         registerThreadContexts();
 678     }
 679
 680     // Set inSyscall so that the CPU doesn't squash when initially
 681     // setting up registers.
 682     for (ThreadID tid = 0; tid < numThreads; ++tid)
 683         thread[tid]->inSyscall = true;
 684
 685 #if FULL_SYSTEM
 686     for (ThreadID tid = 0; tid < numThreads; tid++) {
 687         ThreadContext *src_tc = threadContexts[tid];
 688         TheISA::initCPU(src_tc, src_tc->contextId());
 689     }
 690 #endif
 691
 692     // Clear inSyscall.
 693     for (ThreadID tid = 0; tid < numThreads; ++tid)
 694         thread[tid]->inSyscall = false;
 695
 696     // Call Initializiation Routine for Resource Pool
 697     resPool->init();
 698 }
 699
 700 Port*
 701 InOrderCPU::getPort(const std::string &if_name, int idx)
 702 {
 703     return resPool->getPort(if_name, idx);
 704 }
 705
 706 #if FULL_SYSTEM
 707 Fault
 708 InOrderCPU::hwrei(ThreadID tid)
 709 {
 710     panic("hwrei: Unimplemented");
 711
 712     return NoFault;
 713 }
 714
 715
 716 bool
 717 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 718 {
 719     panic("simPalCheck: Unimplemented");
 720
 721     return true;
 722 }
 723
 724
 725 Fault
 726 InOrderCPU::getInterrupts()
 727 {
 728     // Check if there are any outstanding interrupts
 729     return interrupts->getInterrupt(threadContexts[0]);
 730 }
 731
 732
 733 void
 734 InOrderCPU::processInterrupts(Fault interrupt)
 735 {
 736     // Check for interrupts here.  For now can copy the code that
 737     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 738     // is the one that handles the interrupts.
 739     // @todo: Possibly consolidate the interrupt checking code.
 740     // @todo: Allow other threads to handle interrupts.
 741
 742     assert(interrupt != NoFault);
 743     interrupts->updateIntrInfo(threadContexts[0]);
 744
 745     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 746
 747     // Note: Context ID ok here? Impl. of FS mode needs to revisit this
 748     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 749 }
 750
 751
 752 void
 753 InOrderCPU::updateMemPorts()
 754 {
 755     // Update all ThreadContext's memory ports (Functional/Virtual
 756     // Ports)
 757     ThreadID size = thread.size();
 758     for (ThreadID i = 0; i < size; ++i)
 759         thread[i]->connectMemPorts(thread[i]->getTC());
 760 }
 761 #endif
 762
 763 void
 764 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 765 {
 766     //@ Squash Pipeline during TRAP
 767     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 768 }
 769
 770 void
 771 InOrderCPU::trapCPU(Fault fault, ThreadID tid, DynInstPtr inst)
 772 {
 773     fault->invoke(tcBase(tid), inst->staticInst);
 774 }
 775
 776 void
 777 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 778 {
 779     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 780 }
 781
 782
 783 void
 784 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 785                                 ThreadID tid)
 786 {
 787     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 788
 789     // Squash all instructions in each stage including
 790     // instruction that caused the squash (seq_num - 1)
 791     // NOTE: The stage bandwidth needs to be cleared so thats why
 792     //       the stalling instruction is squashed as well. The stalled
 793     //       instruction is previously placed in another intermediate buffer
 794     //       while it's stall is being handled.
 795     InstSeqNum squash_seq_num = seq_num - 1;
 796
 797     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 798         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 799     }
 800 }
 801
 802 void
 803 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 804                              ThreadID tid, DynInstPtr inst,
 805                              unsigned delay, unsigned event_pri_offset)
 806 {
 807     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 808                                        event_pri_offset);
 809
 810     Tick sked_tick = nextCycle(curTick() + ticks(delay));
 811     if (delay >= 0) {
 812         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 813                 eventNames[c_event], curTick() + delay, tid);
 814         schedule(cpu_event, sked_tick);
 815     } else {
 816         cpu_event->process();
 817         cpuEventRemoveList.push(cpu_event);
 818     }
 819
 820     // Broadcast event to the Resource Pool
 821     // Need to reset tid just in case this is a dummy instruction
 822     inst->setTid(tid);
 823     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 824 }
 825
 826 bool
 827 InOrderCPU::isThreadActive(ThreadID tid)
 828 {
 829   list<ThreadID>::iterator isActive =
 830       std::find(activeThreads.begin(), activeThreads.end(), tid);
 831
 832     return (isActive != activeThreads.end());
 833 }
 834
 835 bool
 836 InOrderCPU::isThreadReady(ThreadID tid)
 837 {
 838   list<ThreadID>::iterator isReady =
 839       std::find(readyThreads.begin(), readyThreads.end(), tid);
 840
 841     return (isReady != readyThreads.end());
 842 }
 843
 844 bool
 845 InOrderCPU::isThreadSuspended(ThreadID tid)
 846 {
 847   list<ThreadID>::iterator isSuspended =
 848       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
 849
 850     return (isSuspended != suspendedThreads.end());
 851 }
 852
 853 void
 854 InOrderCPU::activateNextReadyThread()
 855 {
 856     if (readyThreads.size() >= 1) {
 857         ThreadID ready_tid = readyThreads.front();
 858
 859         // Activate in Pipeline
 860         activateThread(ready_tid);
 861
 862         // Activate in Resource Pool
 863         resPool->activateAll(ready_tid);
 864
 865         list<ThreadID>::iterator ready_it =
 866             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
 867         readyThreads.erase(ready_it);
 868     } else {
 869         DPRINTF(InOrderCPU,
 870                 "Attempting to activate new thread, but No Ready Threads to"
 871                 "activate.\n");
 872         DPRINTF(InOrderCPU,
 873                 "Unable to switch to next active thread.\n");
 874     }
 875 }
 876
 877 void
 878 InOrderCPU::activateThread(ThreadID tid)
 879 {
 880     if (isThreadSuspended(tid)) {
 881         DPRINTF(InOrderCPU,
 882                 "Removing [tid:%i] from suspended threads list.\n", tid);
 883
 884         list<ThreadID>::iterator susp_it =
 885             std::find(suspendedThreads.begin(), suspendedThreads.end(),
 886                       tid);
 887         suspendedThreads.erase(susp_it);
 888     }
 889
 890     if (threadModel == SwitchOnCacheMiss &&
 891         numActiveThreads() == 1) {
 892         DPRINTF(InOrderCPU,
 893                 "Ignoring activation of [tid:%i], since [tid:%i] is "
 894                 "already running.\n", tid, activeThreadId());
 895
 896         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
 897                 tid);
 898
 899         readyThreads.push_back(tid);
 900
 901     } else if (!isThreadActive(tid)) {
 902         DPRINTF(InOrderCPU,
 903                 "Adding [tid:%i] to active threads list.\n", tid);
 904         activeThreads.push_back(tid);
 905
 906         activateThreadInPipeline(tid);
 907
 908         thread[tid]->lastActivate = curTick();
 909
 910         tcBase(tid)->setStatus(ThreadContext::Active);
 911
 912         wakeCPU();
 913
 914         numCtxtSwitches++;
 915     }
 916 }
 917
 918 void
 919 InOrderCPU::activateThreadInPipeline(ThreadID tid)
 920 {
 921     for (int stNum=0; stNum < NumStages; stNum++) {
 922         pipelineStage[stNum]->activateThread(tid);
 923     }
 924 }
 925
 926 void
 927 InOrderCPU::deactivateContext(ThreadID tid, int delay)
 928 {
 929     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
 930
 931     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
 932
 933     // Be sure to signal that there's some activity so the CPU doesn't
 934     // deschedule itself.
 935     activityRec.activity();
 936
 937     _status = Running;
 938 }
 939
 940 void
 941 InOrderCPU::deactivateThread(ThreadID tid)
 942 {
 943     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
 944
 945     if (isThreadActive(tid)) {
 946         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
 947                 tid);
 948         list<ThreadID>::iterator thread_it =
 949             std::find(activeThreads.begin(), activeThreads.end(), tid);
 950
 951         removePipelineStalls(*thread_it);
 952
 953         activeThreads.erase(thread_it);
 954
 955         // Ideally, this should be triggered from the
 956         // suspendContext/Thread functions
 957         tcBase(tid)->setStatus(ThreadContext::Suspended);
 958     }
 959
 960     assert(!isThreadActive(tid));
 961 }
 962
 963 void
 964 InOrderCPU::removePipelineStalls(ThreadID tid)
 965 {
 966     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
 967             tid);
 968
 969     for (int stNum = 0; stNum < NumStages ; stNum++) {
 970         pipelineStage[stNum]->removeStalls(tid);
 971     }
 972
 973 }
 974
 975 void
 976 InOrderCPU::updateThreadPriority()
 977 {
 978     if (activeThreads.size() > 1)
 979     {
 980         //DEFAULT TO ROUND ROBIN SCHEME
 981         //e.g. Move highest priority to end of thread list
 982         list<ThreadID>::iterator list_begin = activeThreads.begin();
 983         list<ThreadID>::iterator list_end   = activeThreads.end();
 984
 985         unsigned high_thread = *list_begin;
 986
 987         activeThreads.erase(list_begin);
 988
 989         activeThreads.push_back(high_thread);
 990     }
 991 }
 992
 993 inline void
 994 InOrderCPU::tickThreadStats()
 995 {
 996     /** Keep track of cycles that each thread is active */
 997     list<ThreadID>::iterator thread_it = activeThreads.begin();
 998     while (thread_it != activeThreads.end()) {
 999         threadCycles[*thread_it]++;
1000         thread_it++;
1001     }
1002
1003     // Keep track of cycles where SMT is active
1004     if (activeThreads.size() > 1) {
1005         smtCycles++;
1006     }
1007 }
1008
1009 void
1010 InOrderCPU::activateContext(ThreadID tid, int delay)
1011 {
1012     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
1013
1014
1015     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
1016
1017     // Be sure to signal that there's some activity so the CPU doesn't
1018     // deschedule itself.
1019     activityRec.activity();
1020
1021     _status = Running;
1022 }
1023
1024 void
1025 InOrderCPU::activateNextReadyContext(int delay)
1026 {
1027     DPRINTF(InOrderCPU,"Activating next ready thread\n");
1028
1029     // NOTE: Add 5 to the event priority so that we always activate
1030     // threads after we've finished deactivating, squashing,etc.
1031     // other threads
1032     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
1033                      delay, 5);
1034
1035     // Be sure to signal that there's some activity so the CPU doesn't
1036     // deschedule itself.
1037     activityRec.activity();
1038
1039     _status = Running;
1040 }
1041
1042 void
1043 InOrderCPU::haltContext(ThreadID tid, int delay)
1044 {
1045     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
1046
1047     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
1048
1049     activityRec.activity();
1050 }
1051
1052 void
1053 InOrderCPU::haltThread(ThreadID tid)
1054 {
1055     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
1056     deactivateThread(tid);
1057     squashThreadInPipeline(tid);
1058     haltedThreads.push_back(tid);
1059
1060     tcBase(tid)->setStatus(ThreadContext::Halted);
1061
1062     if (threadModel == SwitchOnCacheMiss) {
1063         activateNextReadyContext();
1064     }
1065 }
1066
1067 void
1068 InOrderCPU::suspendContext(ThreadID tid, int delay)
1069 {
1070     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
1071 }
1072
1073 void
1074 InOrderCPU::suspendThread(ThreadID tid)
1075 {
1076     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
1077             tid);
1078     deactivateThread(tid);
1079     suspendedThreads.push_back(tid);
1080     thread[tid]->lastSuspend = curTick();
1081
1082     tcBase(tid)->setStatus(ThreadContext::Suspended);
1083 }
1084
1085 void
1086 InOrderCPU::squashThreadInPipeline(ThreadID tid)
1087 {
1088     //Squash all instructions in each stage
1089     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
1090         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
1091     }
1092 }
1093
1094 PipelineStage*
1095 InOrderCPU::getPipeStage(int stage_num)
1096 {
1097     return pipelineStage[stage_num];
1098 }
1099
1100 uint64_t
1101 InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
1102 {
1103     return intRegs[tid][reg_idx];
1104 }
1105
1106 FloatReg
1107 InOrderCPU::readFloatReg(int reg_idx, ThreadID tid)
1108 {
1109     return floatRegs.f[tid][reg_idx];
1110 }
1111
1112 FloatRegBits
1113 InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
1114 {;
1115     return floatRegs.i[tid][reg_idx];
1116 }
1117
1118 void
1119 InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
1120 {
1121     intRegs[tid][reg_idx] = val;
1122 }
1123
1124
1125 void
1126 InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid)
1127 {
1128     floatRegs.f[tid][reg_idx] = val;
1129 }
1130
1131
1132 void
1133 InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid)
1134 {
1135     floatRegs.i[tid][reg_idx] = val;
1136 }
1137
1138 uint64_t
1139 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1140 {
1141     // If Default value is set, then retrieve target thread
1142     if (tid == InvalidThreadID) {
1143         tid = TheISA::getTargetThread(tcBase(tid));
1144     }
1145
1146     if (reg_idx < FP_Base_DepTag) {
1147         // Integer Register File
1148         return readIntReg(reg_idx, tid);
1149     } else if (reg_idx < Ctrl_Base_DepTag) {
1150         // Float Register File
1151         reg_idx -= FP_Base_DepTag;
1152         return readFloatRegBits(reg_idx, tid);
1153     } else {
1154         reg_idx -= Ctrl_Base_DepTag;
1155         return readMiscReg(reg_idx, tid);  // Misc. Register File
1156     }
1157 }
1158 void
1159 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1160                               ThreadID tid)
1161 {
1162     // If Default value is set, then retrieve target thread
1163     if (tid == InvalidThreadID) {
1164         tid = TheISA::getTargetThread(tcBase(tid));
1165     }
1166
1167     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1168         setIntReg(reg_idx, val, tid);
1169     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1170         reg_idx -= FP_Base_DepTag;
1171         setFloatRegBits(reg_idx, val, tid);
1172     } else {
1173         reg_idx -= Ctrl_Base_DepTag;
1174         setMiscReg(reg_idx, val, tid); // Misc. Register File
1175     }
1176 }
1177
1178 MiscReg
1179 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1180 {
1181     return isa[tid].readMiscRegNoEffect(misc_reg);
1182 }
1183
1184 MiscReg
1185 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1186 {
1187     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1188 }
1189
1190 void
1191 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1192 {
1193     isa[tid].setMiscRegNoEffect(misc_reg, val);
1194 }
1195
1196 void
1197 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1198 {
1199     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1200 }
1201
1202
1203 InOrderCPU::ListIt
1204 InOrderCPU::addInst(DynInstPtr &inst)
1205 {
1206     ThreadID tid = inst->readTid();
1207
1208     instList[tid].push_back(inst);
1209
1210     return --(instList[tid].end());
1211 }
1212
1213 void
1214 InOrderCPU::updateContextSwitchStats()
1215 {
1216     // Set Average Stat Here, then reset to 0
1217     instsPerCtxtSwitch = instsPerSwitch;
1218     instsPerSwitch = 0;
1219 }
1220
1221
1222 void
1223 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1224 {
1225     // Set the CPU's PCs - This contributes to the precise state of the CPU
1226     // which can be used when restoring a thread to the CPU after after any
1227     // type of context switching activity (fork, exception, etc.)
1228     pcState(inst->pcState(), tid);
1229
1230     if (inst->isControl()) {
1231         thread[tid]->lastGradIsBranch = true;
1232         thread[tid]->lastBranchPC = inst->pcState();
1233         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1234     } else {
1235         thread[tid]->lastGradIsBranch = false;
1236     }
1237
1238
1239     // Finalize Trace Data For Instruction
1240     if (inst->traceData) {
1241         //inst->traceData->setCycle(curTick());
1242         inst->traceData->setFetchSeq(inst->seqNum);
1243         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1244         inst->traceData->dump();
1245         delete inst->traceData;
1246         inst->traceData = NULL;
1247     }
1248
1249     // Increment active thread's instruction count
1250     instsPerSwitch++;
1251
1252     // Increment thread-state's instruction count
1253     thread[tid]->numInst++;
1254
1255     // Increment thread-state's instruction stats
1256     thread[tid]->numInsts++;
1257
1258     // Count committed insts per thread stats
1259     committedInsts[tid]++;
1260
1261     // Count total insts committed stat
1262     totalCommittedInsts++;
1263
1264     // Count SMT-committed insts per thread stat
1265     if (numActiveThreads() > 1) {
1266         smtCommittedInsts[tid]++;
1267     }
1268
1269     // Instruction-Mix Stats
1270     if (inst->isLoad()) {
1271         comLoads++;
1272     } else if (inst->isStore()) {
1273         comStores++;
1274     } else if (inst->isControl()) {
1275         comBranches++;
1276     } else if (inst->isNop()) {
1277         comNops++;
1278     } else if (inst->isNonSpeculative()) {
1279         comNonSpec++;
1280     } else if (inst->isInteger()) {
1281         comInts++;
1282     } else if (inst->isFloating()) {
1283         comFloats++;
1284     }
1285
1286     // Check for instruction-count-based events.
1287     comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1288
1289     // Broadcast to other resources an instruction
1290     // has been completed
1291     resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
1292                            0, 0, tid);
1293
1294     // Finally, remove instruction from CPU
1295     removeInst(inst);
1296 }
1297
1298 // currently unused function, but substitute repetitive code w/this function
1299 // call
1300 void
1301 InOrderCPU::addToRemoveList(DynInstPtr &inst)
1302 {
1303     removeInstsThisCycle = true;
1304     if (!inst->isRemoveList()) {
1305         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1306                 "[sn:%lli] to remove list\n",
1307                 inst->threadNumber, inst->pcState(), inst->seqNum);
1308         inst->setRemoveList();
1309         removeList.push(inst->getInstListIt());
1310     }  else {
1311         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1312                 "[sn:%lli], already remove list\n",
1313                 inst->threadNumber, inst->pcState(), inst->seqNum);
1314     }
1315
1316 }
1317
1318 void
1319 InOrderCPU::removeInst(DynInstPtr &inst)
1320 {
1321     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1322             "[sn:%lli]\n",
1323             inst->threadNumber, inst->pcState(), inst->seqNum);
1324
1325     removeInstsThisCycle = true;
1326
1327     // Remove the instruction.
1328     if (!inst->isRemoveList()) {
1329         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1330                 "[sn:%lli] to remove list\n",
1331                 inst->threadNumber, inst->pcState(), inst->seqNum);
1332         inst->setRemoveList();
1333         removeList.push(inst->getInstListIt());
1334     } else {
1335         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1336                 "[sn:%lli], already on remove list\n",
1337                 inst->threadNumber, inst->pcState(), inst->seqNum);
1338     }
1339
1340 }
1341
1342 void
1343 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1344 {
1345     //assert(!instList[tid].empty());
1346
1347     removeInstsThisCycle = true;
1348
1349     ListIt inst_iter = instList[tid].end();
1350
1351     inst_iter--;
1352
1353     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1354             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1355             tid, seq_num, (*inst_iter)->seqNum);
1356
1357     while ((*inst_iter)->seqNum > seq_num) {
1358
1359         bool break_loop = (inst_iter == instList[tid].begin());
1360
1361         squashInstIt(inst_iter, tid);
1362
1363         inst_iter--;
1364
1365         if (break_loop)
1366             break;
1367     }
1368 }
1369
1370
1371 inline void
1372 InOrderCPU::squashInstIt(const ListIt &instIt, ThreadID tid)
1373 {
1374     if ((*instIt)->threadNumber == tid) {
1375         DPRINTF(InOrderCPU, "Squashing instruction, "
1376                 "[tid:%i] [sn:%lli] PC %s\n",
1377                 (*instIt)->threadNumber,
1378                 (*instIt)->seqNum,
1379                 (*instIt)->pcState());
1380
1381         (*instIt)->setSquashed();
1382
1383         if (!(*instIt)->isRemoveList()) {
1384             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1385                     "[sn:%lli] to remove list\n",
1386                     (*instIt)->threadNumber, (*instIt)->pcState(),
1387                     (*instIt)->seqNum);
1388             (*instIt)->setRemoveList();
1389             removeList.push(instIt);
1390         } else {
1391             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1392                     " PC %s [sn:%lli], already on remove list\n",
1393                     (*instIt)->threadNumber, (*instIt)->pcState(),
1394                     (*instIt)->seqNum);
1395         }
1396
1397     }
1398
1399 }
1400
1401
1402 void
1403 InOrderCPU::cleanUpRemovedInsts()
1404 {
1405     while (!removeList.empty()) {
1406         DPRINTF(InOrderCPU, "Removing instruction, "
1407                 "[tid:%i] [sn:%lli] PC %s\n",
1408                 (*removeList.front())->threadNumber,
1409                 (*removeList.front())->seqNum,
1410                (*removeList.front())->pcState());
1411
1412         DynInstPtr inst = *removeList.front();
1413         ThreadID tid = inst->threadNumber;
1414
1415         // Remove From Register Dependency Map, If Necessary
1416         archRegDepMap[(*removeList.front())->threadNumber].
1417             remove((*removeList.front()));
1418
1419
1420         // Clear if Non-Speculative
1421         if (inst->staticInst &&
1422             inst->seqNum == nonSpecSeqNum[tid] &&
1423             nonSpecInstActive[tid] == true) {
1424             nonSpecInstActive[tid] = false;
1425         }
1426
1427         instList[tid].erase(removeList.front());
1428
1429         removeList.pop();
1430     }
1431
1432     removeInstsThisCycle = false;
1433 }
1434
1435 void
1436 InOrderCPU::cleanUpRemovedEvents()
1437 {
1438     while (!cpuEventRemoveList.empty()) {
1439         Event *cpu_event = cpuEventRemoveList.front();
1440         cpuEventRemoveList.pop();
1441         delete cpu_event;
1442     }
1443 }
1444
1445
1446 void
1447 InOrderCPU::dumpInsts()
1448 {
1449     int num = 0;
1450
1451     ListIt inst_list_it = instList[0].begin();
1452
1453     cprintf("Dumping Instruction List\n");
1454
1455     while (inst_list_it != instList[0].end()) {
1456         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1457                 "Squashed:%i\n\n",
1458                 num, (*inst_list_it)->pcState(),
1459                 (*inst_list_it)->threadNumber,
1460                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1461                 (*inst_list_it)->isSquashed());
1462         inst_list_it++;
1463         ++num;
1464     }
1465 }
1466
1467 void
1468 InOrderCPU::wakeCPU()
1469 {
1470     if (/*activityRec.active() || */tickEvent.scheduled()) {
1471         DPRINTF(Activity, "CPU already running.\n");
1472         return;
1473     }
1474
1475     DPRINTF(Activity, "Waking up CPU\n");
1476
1477     Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
1478
1479     idleCycles += extra_cycles;
1480     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1481         pipelineStage[stage_num]->idleCycles += extra_cycles;
1482     }
1483
1484     numCycles += extra_cycles;
1485
1486     schedule(&tickEvent, nextCycle(curTick()));
1487 }
1488
1489 #if FULL_SYSTEM
1490
1491 void
1492 InOrderCPU::wakeup()
1493 {
1494     if (thread[0]->status() != ThreadContext::Suspended)
1495         return;
1496
1497     wakeCPU();
1498
1499     DPRINTF(Quiesce, "Suspended Processor woken\n");
1500     threadContexts[0]->activate();
1501 }
1502 #endif
1503
1504 #if !FULL_SYSTEM
1505 void
1506 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1507 {
1508     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1509
1510     DPRINTF(Activity,"Activity: syscall() called.\n");
1511
1512     // Temporarily increase this by one to account for the syscall
1513     // instruction.
1514     ++(this->thread[tid]->funcExeInst);
1515
1516     // Execute the actual syscall.
1517     this->thread[tid]->syscall(callnum);
1518
1519     // Decrease funcExeInst by one as the normal commit will handle
1520     // incrementing it.
1521     --(this->thread[tid]->funcExeInst);
1522
1523     // Clear Non-Speculative Block Variable
1524     nonSpecInstActive[tid] = false;
1525 }
1526 #endif
1527
1528 TheISA::TLB*
1529 InOrderCPU::getITBPtr()
1530 {
1531     CacheUnit *itb_res =
1532         dynamic_cast<CacheUnit*>(resPool->getResource(fetchPortIdx));
1533     return itb_res->tlb();
1534 }
1535
1536
1537 TheISA::TLB*
1538 InOrderCPU::getDTBPtr()
1539 {
1540     CacheUnit *dtb_res =
1541         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1542     return dtb_res->tlb();
1543 }
1544
1545 Fault
1546 InOrderCPU::read(DynInstPtr inst, Addr addr,
1547                  uint8_t *data, unsigned size, unsigned flags)
1548 {
1549     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1550     //       you want to run w/out caches?
1551     CacheUnit *cache_res =
1552         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1553
1554     return cache_res->read(inst, addr, data, size, flags);
1555 }
1556
1557 Fault
1558 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1559                   Addr addr, unsigned flags, uint64_t *write_res)
1560 {
1561     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1562     //       you want to run w/out caches?
1563     CacheUnit *cache_res =
1564         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1565     return cache_res->write(inst, data, size, addr, flags, write_res);
1566 }