src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007 MIPS Technologies, Inc.
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Korey Sewell
  41  *
  42  */
  43
  44 #include <algorithm>
  45
  46 #include "arch/utility.hh"
  47 #include "base/bigint.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/inorder/resources/cache_unit.hh"
  50 #include "cpu/inorder/resources/resource_list.hh"
  51 #include "cpu/inorder/cpu.hh"
  52 #include "cpu/inorder/first_stage.hh"
  53 #include "cpu/inorder/inorder_dyn_inst.hh"
  54 #include "cpu/inorder/pipeline_traits.hh"
  55 #include "cpu/inorder/resource_pool.hh"
  56 #include "cpu/inorder/thread_context.hh"
  57 #include "cpu/inorder/thread_state.hh"
  58 #include "cpu/activity.hh"
  59 #include "cpu/base.hh"
  60 #include "cpu/exetrace.hh"
  61 #include "cpu/quiesce_event.hh"
  62 #include "cpu/simple_thread.hh"
  63 #include "cpu/thread_context.hh"
  64 #include "debug/Activity.hh"
  65 #include "debug/InOrderCPU.hh"
  66 #include "debug/InOrderCachePort.hh"
  67 #include "debug/Interrupt.hh"
  68 #include "debug/Quiesce.hh"
  69 #include "debug/RefCount.hh"
  70 #include "debug/SkedCache.hh"
  71 #include "params/InOrderCPU.hh"
  72 #include "sim/full_system.hh"
  73 #include "sim/process.hh"
  74 #include "sim/stat_control.hh"
  75 #include "sim/system.hh"
  76
  77 #if THE_ISA == ALPHA_ISA
  78 #include "arch/alpha/osfpal.hh"
  79 #endif
  80
  81 using namespace std;
  82 using namespace TheISA;
  83 using namespace ThePipeline;
  84
  85 InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit,
  86                                  const std::string& name) :
  87     CpuPort(_cacheUnit->name() + name, _cacheUnit->cpu),
  88     cacheUnit(_cacheUnit)
  89 { }
  90
  91 bool
  92 InOrderCPU::CachePort::recvTimingResp(Packet *pkt)
  93 {
  94     if (pkt->isError())
  95         DPRINTF(InOrderCachePort, "Got error packet back for address: %x\n",
  96                 pkt->getAddr());
  97     else
  98         cacheUnit->processCacheCompletion(pkt);
  99
 100     return true;
 101 }
 102
 103 void
 104 InOrderCPU::CachePort::recvRetry()
 105 {
 106     cacheUnit->recvRetry();
 107 }
 108
 109 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
 110   : Event(CPU_Tick_Pri), cpu(c)
 111 { }
 112
 113
 114 void
 115 InOrderCPU::TickEvent::process()
 116 {
 117     cpu->tick();
 118 }
 119
 120
 121 const char *
 122 InOrderCPU::TickEvent::description() const
 123 {
 124     return "InOrderCPU tick event";
 125 }
 126
 127 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
 128                                Fault fault, ThreadID _tid, DynInstPtr inst,
 129                                CPUEventPri event_pri)
 130     : Event(event_pri), cpu(_cpu)
 131 {
 132     setEvent(e_type, fault, _tid, inst);
 133 }
 134
 135
 136 std::string InOrderCPU::eventNames[NumCPUEvents] =
 137 {
 138     "ActivateThread",
 139     "ActivateNextReadyThread",
 140     "DeactivateThread",
 141     "HaltThread",
 142     "SuspendThread",
 143     "Trap",
 144     "Syscall",
 145     "SquashFromMemStall",
 146     "UpdatePCs"
 147 };
 148
 149 void
 150 InOrderCPU::CPUEvent::process()
 151 {
 152     switch (cpuEventType)
 153     {
 154       case ActivateThread:
 155         cpu->activateThread(tid);
 156         cpu->resPool->activateThread(tid);
 157         break;
 158
 159       case ActivateNextReadyThread:
 160         cpu->activateNextReadyThread();
 161         break;
 162
 163       case DeactivateThread:
 164         cpu->deactivateThread(tid);
 165         cpu->resPool->deactivateThread(tid);
 166         break;
 167
 168       case HaltThread:
 169         cpu->haltThread(tid);
 170         cpu->resPool->deactivateThread(tid);
 171         break;
 172
 173       case SuspendThread:
 174         cpu->suspendThread(tid);
 175         cpu->resPool->suspendThread(tid);
 176         break;
 177
 178       case SquashFromMemStall:
 179         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 180         cpu->resPool->squashDueToMemStall(inst, inst->squashingStage,
 181                                           inst->seqNum, tid);
 182         break;
 183
 184       case Trap:
 185         DPRINTF(InOrderCPU, "Trapping CPU\n");
 186         cpu->trap(fault, tid, inst);
 187         cpu->resPool->trap(fault, tid, inst);
 188         cpu->trapPending[tid] = false;
 189         break;
 190
 191       case Syscall:
 192         cpu->syscall(inst->syscallNum, tid);
 193         cpu->resPool->trap(fault, tid, inst);
 194         break;
 195
 196       default:
 197         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 198     }
 199
 200     cpu->cpuEventRemoveList.push(this);
 201 }
 202
 203
 204
 205 const char *
 206 InOrderCPU::CPUEvent::description() const
 207 {
 208     return "InOrderCPU event";
 209 }
 210
 211 void
 212 InOrderCPU::CPUEvent::scheduleEvent(Cycles delay)
 213 {
 214     assert(!scheduled() || squashed());
 215     cpu->reschedule(this, cpu->clockEdge(delay), true);
 216 }
 217
 218 void
 219 InOrderCPU::CPUEvent::unscheduleEvent()
 220 {
 221     if (scheduled())
 222         squash();
 223 }
 224
 225 InOrderCPU::InOrderCPU(Params *params)
 226     : BaseCPU(params),
 227       cpu_id(params->cpu_id),
 228       coreType("default"),
 229       _status(Idle),
 230       tickEvent(this),
 231       stageWidth(params->stageWidth),
 232       resPool(new ResourcePool(this, params)),
 233       isa(numThreads, NULL),
 234       timeBuffer(2 , 2),
 235       dataPort(resPool->getDataUnit(), ".dcache_port"),
 236       instPort(resPool->getInstUnit(), ".icache_port"),
 237       removeInstsThisCycle(false),
 238       activityRec(params->name, NumStages, 10, params->activity),
 239       system(params->system),
 240 #ifdef DEBUG
 241       cpuEventNum(0),
 242       resReqCount(0),
 243 #endif // DEBUG
 244       drainCount(0),
 245       stageTracing(params->stageTracing),
 246       lastRunningCycle(0),
 247       instsPerSwitch(0)
 248 {
 249     cpu_params = params;
 250
 251     // Resize for Multithreading CPUs
 252     thread.resize(numThreads);
 253
 254     ThreadID active_threads = params->workload.size();
 255     if (FullSystem) {
 256         active_threads = 1;
 257     } else {
 258         active_threads = params->workload.size();
 259
 260         if (active_threads > MaxThreads) {
 261             panic("Workload Size too large. Increase the 'MaxThreads'"
 262                   "in your InOrder implementation or "
 263                   "edit your workload size.");
 264         }
 265
 266
 267         if (active_threads > 1) {
 268             threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 269
 270             if (threadModel == SMT) {
 271                 DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 272             } else if (threadModel == SwitchOnCacheMiss) {
 273                 DPRINTF(InOrderCPU, "Setting Thread Model to "
 274                         "Switch On Cache Miss\n");
 275             }
 276
 277         } else {
 278             threadModel = Single;
 279         }
 280     }
 281
 282     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 283         isa[tid] = params->isa[tid];
 284         pc[tid].set(0);
 285         lastCommittedPC[tid].set(0);
 286
 287         if (FullSystem) {
 288             // SMT is not supported in FS mode yet.
 289             assert(numThreads == 1);
 290             thread[tid] = new Thread(this, 0, NULL);
 291         } else {
 292             if (tid < (ThreadID)params->workload.size()) {
 293                 DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 294                         tid, params->workload[tid]->progName());
 295                 thread[tid] =
 296                     new Thread(this, tid, params->workload[tid]);
 297             } else {
 298                 //Allocate Empty thread so M5 can use later
 299                 //when scheduling threads to CPU
 300                 Process* dummy_proc = params->workload[0];
 301                 thread[tid] = new Thread(this, tid, dummy_proc);
 302             }
 303
 304             // Eventually set this with parameters...
 305             asid[tid] = tid;
 306         }
 307
 308         // Setup the TC that will serve as the interface to the threads/CPU.
 309         InOrderThreadContext *tc = new InOrderThreadContext;
 310         tc->cpu = this;
 311         tc->thread = thread[tid];
 312
 313         // Setup quiesce event.
 314         this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
 315
 316         // Give the thread the TC.
 317         thread[tid]->tc = tc;
 318         thread[tid]->setFuncExeInst(0);
 319         globalSeqNum[tid] = 1;
 320
 321         // Add the TC to the CPU's list of TC's.
 322         this->threadContexts.push_back(tc);
 323     }
 324
 325     // Initialize TimeBuffer Stage Queues
 326     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 327         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 328         stageQueue[stNum]->id(stNum);
 329     }
 330
 331
 332     // Set Up Pipeline Stages
 333     for (int stNum=0; stNum < NumStages; stNum++) {
 334         if (stNum == 0)
 335             pipelineStage[stNum] = new FirstStage(params, stNum);
 336         else
 337             pipelineStage[stNum] = new PipelineStage(params, stNum);
 338
 339         pipelineStage[stNum]->setCPU(this);
 340         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 341         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 342
 343         // Take Care of 1st/Nth stages
 344         if (stNum > 0)
 345             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 346         if (stNum < NumStages - 1)
 347             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 348     }
 349
 350     // Initialize thread specific variables
 351     for (ThreadID tid = 0; tid < numThreads; tid++) {
 352         archRegDepMap[tid].setCPU(this);
 353
 354         nonSpecInstActive[tid] = false;
 355         nonSpecSeqNum[tid] = 0;
 356
 357         squashSeqNum[tid] = MaxAddr;
 358         lastSquashCycle[tid] = 0;
 359
 360         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 361         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 362         isa[tid]->clear();
 363
 364         // Define dummy instructions and resource requests to be used.
 365         dummyInst[tid] = new InOrderDynInst(this,
 366                                             thread[tid],
 367                                             0,
 368                                             tid,
 369                                             asid[tid]);
 370
 371         dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
 372
 373
 374         if (FullSystem) {
 375             // Use this dummy inst to force squashing behind every instruction
 376             // in pipeline
 377             dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
 378             dummyTrapInst[tid]->seqNum = 0;
 379             dummyTrapInst[tid]->squashSeqNum = 0;
 380             dummyTrapInst[tid]->setTid(tid);
 381         }
 382
 383         trapPending[tid] = false;
 384
 385     }
 386
 387     // InOrderCPU always requires an interrupt controller.
 388     if (!params->switched_out && !interrupts) {
 389         fatal("InOrderCPU %s has no interrupt controller.\n"
 390               "Ensure createInterruptController() is called.\n", name());
 391     }
 392
 393     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 394     dummyReqInst->setSquashed();
 395     dummyReqInst->resetInstCount();
 396
 397     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 398     dummyBufferInst->setSquashed();
 399     dummyBufferInst->resetInstCount();
 400
 401     endOfSkedIt = skedCache.end();
 402     frontEndSked = createFrontEndSked();
 403     faultSked = createFaultSked();
 404
 405     lastRunningCycle = curCycle();
 406
 407     lockAddr = 0;
 408     lockFlag = false;
 409
 410     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 411     scheduleTickEvent(Cycles(0));
 412 }
 413
 414 InOrderCPU::~InOrderCPU()
 415 {
 416     delete resPool;
 417
 418     SkedCacheIt sked_it = skedCache.begin();
 419     SkedCacheIt sked_end = skedCache.end();
 420
 421     while (sked_it != sked_end) {
 422         delete (*sked_it).second;
 423         sked_it++;
 424     }
 425     skedCache.clear();
 426 }
 427
 428 m5::hash_map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
 429
 430 RSkedPtr
 431 InOrderCPU::createFrontEndSked()
 432 {
 433     RSkedPtr res_sked = new ResourceSked();
 434     int stage_num = 0;
 435     StageScheduler F(res_sked, stage_num++);
 436     StageScheduler D(res_sked, stage_num++);
 437
 438     // FETCH
 439     F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
 440     F.needs(ICache, FetchUnit::InitiateFetch);
 441
 442     // DECODE
 443     D.needs(ICache, FetchUnit::CompleteFetch);
 444     D.needs(Decode, DecodeUnit::DecodeInst);
 445     D.needs(BPred, BranchPredictor::PredictBranch);
 446     D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
 447
 448
 449     DPRINTF(SkedCache, "Resource Sked created for instruction Front End\n");
 450
 451     return res_sked;
 452 }
 453
 454 RSkedPtr
 455 InOrderCPU::createFaultSked()
 456 {
 457     RSkedPtr res_sked = new ResourceSked();
 458     StageScheduler W(res_sked, NumStages - 1);
 459     W.needs(Grad, GraduationUnit::CheckFault);
 460     DPRINTF(SkedCache, "Resource Sked created for instruction Faults\n");
 461     return res_sked;
 462 }
 463
 464 RSkedPtr
 465 InOrderCPU::createBackEndSked(DynInstPtr inst)
 466 {
 467     RSkedPtr res_sked = lookupSked(inst);
 468     if (res_sked != NULL) {
 469         DPRINTF(SkedCache, "Found %s in sked cache.\n",
 470                 inst->instName());
 471         return res_sked;
 472     } else {
 473         res_sked = new ResourceSked();
 474     }
 475
 476     int stage_num = ThePipeline::BackEndStartStage;
 477     StageScheduler X(res_sked, stage_num++);
 478     StageScheduler M(res_sked, stage_num++);
 479     StageScheduler W(res_sked, stage_num++);
 480
 481     if (!inst->staticInst) {
 482         warn_once("Static Instruction Object Not Set. Can't Create"
 483                   " Back End Schedule");
 484         return NULL;
 485     }
 486
 487     // EXECUTE
 488     X.needs(RegManager, UseDefUnit::MarkDestRegs);
 489     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 490         if (!idx || !inst->isStore()) {
 491             X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
 492         }
 493     }
 494
 495     //@todo: schedule non-spec insts to operate on this cycle
 496     // as long as all previous insts are done
 497     if ( inst->isNonSpeculative() ) {
 498         // skip execution of non speculative insts until later
 499     } else if ( inst->isMemRef() ) {
 500         if ( inst->isLoad() ) {
 501             X.needs(AGEN, AGENUnit::GenerateAddr);
 502         }
 503     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 504         X.needs(MDU, MultDivUnit::StartMultDiv);
 505     } else {
 506         X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 507     }
 508
 509     // MEMORY
 510     if (!inst->isNonSpeculative()) {
 511         if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 512             M.needs(MDU, MultDivUnit::EndMultDiv);
 513         }
 514
 515         if ( inst->isLoad() ) {
 516             M.needs(DCache, CacheUnit::InitiateReadData);
 517             if (inst->splitInst)
 518                 M.needs(DCache, CacheUnit::InitSecondSplitRead);
 519         } else if ( inst->isStore() ) {
 520             for (int i = 1; i < inst->numSrcRegs(); i++ ) {
 521                 M.needs(RegManager, UseDefUnit::ReadSrcReg, i);
 522             }
 523             M.needs(AGEN, AGENUnit::GenerateAddr);
 524             M.needs(DCache, CacheUnit::InitiateWriteData);
 525             if (inst->splitInst)
 526                 M.needs(DCache, CacheUnit::InitSecondSplitWrite);
 527         }
 528     }
 529
 530     // WRITEBACK
 531     if (!inst->isNonSpeculative()) {
 532         if ( inst->isLoad() ) {
 533             W.needs(DCache, CacheUnit::CompleteReadData);
 534             if (inst->splitInst)
 535                 W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
 536         } else if ( inst->isStore() ) {
 537             W.needs(DCache, CacheUnit::CompleteWriteData);
 538             if (inst->splitInst)
 539                 W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
 540         }
 541     } else {
 542         // Finally, Execute Speculative Data
 543         if (inst->isMemRef()) {
 544             if (inst->isLoad()) {
 545                 W.needs(AGEN, AGENUnit::GenerateAddr);
 546                 W.needs(DCache, CacheUnit::InitiateReadData);
 547                 if (inst->splitInst)
 548                     W.needs(DCache, CacheUnit::InitSecondSplitRead);
 549                 W.needs(DCache, CacheUnit::CompleteReadData);
 550                 if (inst->splitInst)
 551                     W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
 552             } else if (inst->isStore()) {
 553                 if ( inst->numSrcRegs() >= 2 ) {
 554                     W.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 555                 }
 556                 W.needs(AGEN, AGENUnit::GenerateAddr);
 557                 W.needs(DCache, CacheUnit::InitiateWriteData);
 558                 if (inst->splitInst)
 559                     W.needs(DCache, CacheUnit::InitSecondSplitWrite);
 560                 W.needs(DCache, CacheUnit::CompleteWriteData);
 561                 if (inst->splitInst)
 562                     W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
 563             }
 564         } else {
 565             W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 566         }
 567     }
 568
 569     W.needs(Grad, GraduationUnit::CheckFault);
 570
 571     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 572         W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
 573     }
 574
 575     if (inst->isControl())
 576         W.needs(BPred, BranchPredictor::UpdatePredictor);
 577
 578     W.needs(Grad, GraduationUnit::GraduateInst);
 579
 580     // Insert Back Schedule into our cache of
 581     // resource schedules
 582     addToSkedCache(inst, res_sked);
 583
 584     DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
 585             inst->instName(), inst->getMachInst());
 586     res_sked->print();
 587
 588     return res_sked;
 589 }
 590
 591 void
 592 InOrderCPU::regStats()
 593 {
 594     /* Register the Resource Pool's stats here.*/
 595     resPool->regStats();
 596
 597     /* Register for each Pipeline Stage */
 598     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 599         pipelineStage[stage_num]->regStats();
 600     }
 601
 602     /* Register any of the InOrderCPU's stats here.*/
 603     instsPerCtxtSwitch
 604         .name(name() + ".instsPerContextSwitch")
 605         .desc("Instructions Committed Per Context Switch")
 606         .prereq(instsPerCtxtSwitch);
 607
 608     numCtxtSwitches
 609         .name(name() + ".contextSwitches")
 610         .desc("Number of context switches");
 611
 612     comLoads
 613         .name(name() + ".comLoads")
 614         .desc("Number of Load instructions committed");
 615
 616     comStores
 617         .name(name() + ".comStores")
 618         .desc("Number of Store instructions committed");
 619
 620     comBranches
 621         .name(name() + ".comBranches")
 622         .desc("Number of Branches instructions committed");
 623
 624     comNops
 625         .name(name() + ".comNops")
 626         .desc("Number of Nop instructions committed");
 627
 628     comNonSpec
 629         .name(name() + ".comNonSpec")
 630         .desc("Number of Non-Speculative instructions committed");
 631
 632     comInts
 633         .name(name() + ".comInts")
 634         .desc("Number of Integer instructions committed");
 635
 636     comFloats
 637         .name(name() + ".comFloats")
 638         .desc("Number of Floating Point instructions committed");
 639
 640     timesIdled
 641         .name(name() + ".timesIdled")
 642         .desc("Number of times that the entire CPU went into an idle state and"
 643               " unscheduled itself")
 644         .prereq(timesIdled);
 645
 646     idleCycles
 647         .name(name() + ".idleCycles")
 648         .desc("Number of cycles cpu's stages were not processed");
 649
 650     runCycles
 651         .name(name() + ".runCycles")
 652         .desc("Number of cycles cpu stages are processed.");
 653
 654     activity
 655         .name(name() + ".activity")
 656         .desc("Percentage of cycles cpu is active")
 657         .precision(6);
 658     activity = (runCycles / numCycles) * 100;
 659
 660     threadCycles
 661         .init(numThreads)
 662         .name(name() + ".threadCycles")
 663         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 664
 665     smtCycles
 666         .name(name() + ".smtCycles")
 667         .desc("Total number of cycles that the CPU was in SMT-mode");
 668
 669     committedInsts
 670         .init(numThreads)
 671         .name(name() + ".committedInsts")
 672         .desc("Number of Instructions committed (Per-Thread)");
 673
 674     committedOps
 675         .init(numThreads)
 676         .name(name() + ".committedOps")
 677         .desc("Number of Ops committed (Per-Thread)");
 678
 679     smtCommittedInsts
 680         .init(numThreads)
 681         .name(name() + ".smtCommittedInsts")
 682         .desc("Number of SMT Instructions committed (Per-Thread)");
 683
 684     totalCommittedInsts
 685         .name(name() + ".committedInsts_total")
 686         .desc("Number of Instructions committed (Total)");
 687
 688     cpi
 689         .name(name() + ".cpi")
 690         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 691         .precision(6);
 692     cpi = numCycles / committedInsts;
 693
 694     smtCpi
 695         .name(name() + ".smt_cpi")
 696         .desc("CPI: Total SMT-CPI")
 697         .precision(6);
 698     smtCpi = smtCycles / smtCommittedInsts;
 699
 700     totalCpi
 701         .name(name() + ".cpi_total")
 702         .desc("CPI: Total CPI of All Threads")
 703         .precision(6);
 704     totalCpi = numCycles / totalCommittedInsts;
 705
 706     ipc
 707         .name(name() + ".ipc")
 708         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 709         .precision(6);
 710     ipc =  committedInsts / numCycles;
 711
 712     smtIpc
 713         .name(name() + ".smt_ipc")
 714         .desc("IPC: Total SMT-IPC")
 715         .precision(6);
 716     smtIpc = smtCommittedInsts / smtCycles;
 717
 718     totalIpc
 719         .name(name() + ".ipc_total")
 720         .desc("IPC: Total IPC of All Threads")
 721         .precision(6);
 722         totalIpc =  totalCommittedInsts / numCycles;
 723
 724     BaseCPU::regStats();
 725 }
 726
 727
 728 void
 729 InOrderCPU::tick()
 730 {
 731     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 732
 733     ++numCycles;
 734
 735     checkForInterrupts();
 736
 737     bool pipes_idle = true;
 738     //Tick each of the stages
 739     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 740         pipelineStage[stNum]->tick();
 741
 742         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 743     }
 744
 745     if (pipes_idle)
 746         idleCycles++;
 747     else
 748         runCycles++;
 749
 750     // Now advance the time buffers one tick
 751     timeBuffer.advance();
 752     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 753         stageQueue[sqNum]->advance();
 754     }
 755     activityRec.advance();
 756
 757     // Any squashed events, or insts then remove them now
 758     cleanUpRemovedEvents();
 759     cleanUpRemovedInsts();
 760
 761     // Re-schedule CPU for this cycle
 762     if (!tickEvent.scheduled()) {
 763         if (_status == SwitchedOut) {
 764             // increment stat
 765             lastRunningCycle = curCycle();
 766         } else if (!activityRec.active()) {
 767             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 768             lastRunningCycle = curCycle();
 769             timesIdled++;
 770         } else {
 771             //Tick next_tick = curTick() + cycles(1);
 772             //tickEvent.schedule(next_tick);
 773             schedule(&tickEvent, clockEdge(Cycles(1)));
 774             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 775                     clockEdge(Cycles(1)));
 776         }
 777     }
 778
 779     tickThreadStats();
 780     updateThreadPriority();
 781 }
 782
 783
 784 void
 785 InOrderCPU::init()
 786 {
 787     BaseCPU::init();
 788
 789     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 790         // Set noSquashFromTC so that the CPU doesn't squash when initially
 791         // setting up registers.
 792         thread[tid]->noSquashFromTC = true;
 793         // Initialise the ThreadContext's memory proxies
 794         thread[tid]->initMemProxies(thread[tid]->getTC());
 795     }
 796
 797     if (FullSystem && !params()->switched_out) {
 798         for (ThreadID tid = 0; tid < numThreads; tid++) {
 799             ThreadContext *src_tc = threadContexts[tid];
 800             TheISA::initCPU(src_tc, src_tc->contextId());
 801         }
 802     }
 803
 804     // Clear noSquashFromTC.
 805     for (ThreadID tid = 0; tid < numThreads; ++tid)
 806         thread[tid]->noSquashFromTC = false;
 807
 808     // Call Initializiation Routine for Resource Pool
 809     resPool->init();
 810 }
 811
 812 void
 813 InOrderCPU::verifyMemoryMode() const
 814 {
 815     if (!system->isTimingMode()) {
 816         fatal("The in-order CPU requires the memory system to be in "
 817               "'timing' mode.\n");
 818     }
 819 }
 820
 821 Fault
 822 InOrderCPU::hwrei(ThreadID tid)
 823 {
 824 #if THE_ISA == ALPHA_ISA
 825     // Need to clear the lock flag upon returning from an interrupt.
 826     setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
 827
 828     thread[tid]->kernelStats->hwrei();
 829     // FIXME: XXX check for interrupts? XXX
 830 #endif
 831
 832     return NoFault;
 833 }
 834
 835
 836 bool
 837 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 838 {
 839 #if THE_ISA == ALPHA_ISA
 840     if (this->thread[tid]->kernelStats)
 841         this->thread[tid]->kernelStats->callpal(palFunc,
 842                                                 this->threadContexts[tid]);
 843
 844     switch (palFunc) {
 845       case PAL::halt:
 846         halt();
 847         if (--System::numSystemsRunning == 0)
 848             exitSimLoop("all cpus halted");
 849         break;
 850
 851       case PAL::bpt:
 852       case PAL::bugchk:
 853         if (this->system->breakpoint())
 854             return false;
 855         break;
 856     }
 857 #endif
 858     return true;
 859 }
 860
 861 void
 862 InOrderCPU::checkForInterrupts()
 863 {
 864     for (int i = 0; i < threadContexts.size(); i++) {
 865         ThreadContext *tc = threadContexts[i];
 866
 867         if (interrupts->checkInterrupts(tc)) {
 868             Fault interrupt = interrupts->getInterrupt(tc);
 869
 870             if (interrupt != NoFault) {
 871                 DPRINTF(Interrupt, "Processing Intterupt for [tid:%i].\n",
 872                         tc->threadId());
 873
 874                 ThreadID tid = tc->threadId();
 875                 interrupts->updateIntrInfo(tc);
 876
 877                 // Squash from Last Stage in Pipeline
 878                 unsigned last_stage = NumStages - 1;
 879                 dummyTrapInst[tid]->squashingStage = last_stage;
 880                 pipelineStage[last_stage]->setupSquash(dummyTrapInst[tid],
 881                                                        tid);
 882
 883                 // By default, setupSquash will always squash from stage + 1
 884                 pipelineStage[BackEndStartStage - 1]->setupSquash(dummyTrapInst[tid],
 885                                                                   tid);
 886
 887                 // Schedule Squash Through-out Resource Pool
 888                 resPool->scheduleEvent(
 889                     (InOrderCPU::CPUEventType)ResourcePool::SquashAll,
 890                     dummyTrapInst[tid], Cycles(0));
 891
 892                 // Finally, Setup Trap to happen at end of cycle
 893                 trapContext(interrupt, tid, dummyTrapInst[tid]);
 894             }
 895         }
 896     }
 897 }
 898
 899 Fault
 900 InOrderCPU::getInterrupts()
 901 {
 902     // Check if there are any outstanding interrupts
 903     return interrupts->getInterrupt(threadContexts[0]);
 904 }
 905
 906 void
 907 InOrderCPU::processInterrupts(Fault interrupt)
 908 {
 909     // Check for interrupts here.  For now can copy the code that
 910     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 911     // is the one that handles the interrupts.
 912     // @todo: Possibly consolidate the interrupt checking code.
 913     // @todo: Allow other threads to handle interrupts.
 914
 915     assert(interrupt != NoFault);
 916     interrupts->updateIntrInfo(threadContexts[0]);
 917
 918     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 919
 920     // Note: Context ID ok here? Impl. of FS mode needs to revisit this
 921     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 922 }
 923
 924 void
 925 InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
 926                         Cycles delay)
 927 {
 928     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 929     trapPending[tid] = true;
 930 }
 931
 932 void
 933 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 934 {
 935     fault->invoke(tcBase(tid), inst->staticInst);
 936     removePipelineStalls(tid);
 937 }
 938
 939 void
 940 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid,
 941                                Cycles delay)
 942 {
 943     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 944 }
 945
 946
 947 void
 948 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 949                                 ThreadID tid)
 950 {
 951     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 952
 953     // Squash all instructions in each stage including
 954     // instruction that caused the squash (seq_num - 1)
 955     // NOTE: The stage bandwidth needs to be cleared so thats why
 956     //       the stalling instruction is squashed as well. The stalled
 957     //       instruction is previously placed in another intermediate buffer
 958     //       while it's stall is being handled.
 959     InstSeqNum squash_seq_num = seq_num - 1;
 960
 961     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 962         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 963     }
 964 }
 965
 966 void
 967 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 968                              ThreadID tid, DynInstPtr inst,
 969                              Cycles delay, CPUEventPri event_pri)
 970 {
 971     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 972                                        event_pri);
 973
 974     Tick sked_tick = clockEdge(delay);
 975     DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 976             eventNames[c_event], curTick() + delay, tid);
 977     schedule(cpu_event, sked_tick);
 978
 979     // Broadcast event to the Resource Pool
 980     // Need to reset tid just in case this is a dummy instruction
 981     inst->setTid(tid);
 982     // @todo: Is this really right? Should the delay not be passed on?
 983     resPool->scheduleEvent(c_event, inst, Cycles(0), 0, tid);
 984 }
 985
 986 bool
 987 InOrderCPU::isThreadActive(ThreadID tid)
 988 {
 989   list<ThreadID>::iterator isActive =
 990       std::find(activeThreads.begin(), activeThreads.end(), tid);
 991
 992     return (isActive != activeThreads.end());
 993 }
 994
 995 bool
 996 InOrderCPU::isThreadReady(ThreadID tid)
 997 {
 998   list<ThreadID>::iterator isReady =
 999       std::find(readyThreads.begin(), readyThreads.end(), tid);
1000
1001     return (isReady != readyThreads.end());
1002 }
1003
1004 bool
1005 InOrderCPU::isThreadSuspended(ThreadID tid)
1006 {
1007   list<ThreadID>::iterator isSuspended =
1008       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
1009
1010     return (isSuspended != suspendedThreads.end());
1011 }
1012
1013 void
1014 InOrderCPU::activateNextReadyThread()
1015 {
1016     if (readyThreads.size() >= 1) {
1017         ThreadID ready_tid = readyThreads.front();
1018
1019         // Activate in Pipeline
1020         activateThread(ready_tid);
1021
1022         // Activate in Resource Pool
1023         resPool->activateThread(ready_tid);
1024
1025         list<ThreadID>::iterator ready_it =
1026             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
1027         readyThreads.erase(ready_it);
1028     } else {
1029         DPRINTF(InOrderCPU,
1030                 "Attempting to activate new thread, but No Ready Threads to"
1031                 "activate.\n");
1032         DPRINTF(InOrderCPU,
1033                 "Unable to switch to next active thread.\n");
1034     }
1035 }
1036
1037 void
1038 InOrderCPU::activateThread(ThreadID tid)
1039 {
1040     if (isThreadSuspended(tid)) {
1041         DPRINTF(InOrderCPU,
1042                 "Removing [tid:%i] from suspended threads list.\n", tid);
1043
1044         list<ThreadID>::iterator susp_it =
1045             std::find(suspendedThreads.begin(), suspendedThreads.end(),
1046                       tid);
1047         suspendedThreads.erase(susp_it);
1048     }
1049
1050     if (threadModel == SwitchOnCacheMiss &&
1051         numActiveThreads() == 1) {
1052         DPRINTF(InOrderCPU,
1053                 "Ignoring activation of [tid:%i], since [tid:%i] is "
1054                 "already running.\n", tid, activeThreadId());
1055
1056         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
1057                 tid);
1058
1059         readyThreads.push_back(tid);
1060
1061     } else if (!isThreadActive(tid)) {
1062         DPRINTF(InOrderCPU,
1063                 "Adding [tid:%i] to active threads list.\n", tid);
1064         activeThreads.push_back(tid);
1065
1066         activateThreadInPipeline(tid);
1067
1068         thread[tid]->lastActivate = curTick();
1069
1070         tcBase(tid)->setStatus(ThreadContext::Active);
1071
1072         wakeCPU();
1073
1074         numCtxtSwitches++;
1075     }
1076 }
1077
1078 void
1079 InOrderCPU::activateThreadInPipeline(ThreadID tid)
1080 {
1081     for (int stNum=0; stNum < NumStages; stNum++) {
1082         pipelineStage[stNum]->activateThread(tid);
1083     }
1084 }
1085
1086 void
1087 InOrderCPU::deactivateContext(ThreadID tid, Cycles delay)
1088 {
1089     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
1090
1091     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
1092
1093     // Be sure to signal that there's some activity so the CPU doesn't
1094     // deschedule itself.
1095     activityRec.activity();
1096
1097     _status = Running;
1098 }
1099
1100 void
1101 InOrderCPU::deactivateThread(ThreadID tid)
1102 {
1103     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
1104
1105     if (isThreadActive(tid)) {
1106         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
1107                 tid);
1108         list<ThreadID>::iterator thread_it =
1109             std::find(activeThreads.begin(), activeThreads.end(), tid);
1110
1111         removePipelineStalls(*thread_it);
1112
1113         activeThreads.erase(thread_it);
1114
1115         // Ideally, this should be triggered from the
1116         // suspendContext/Thread functions
1117         tcBase(tid)->setStatus(ThreadContext::Suspended);
1118     }
1119
1120     assert(!isThreadActive(tid));
1121 }
1122
1123 void
1124 InOrderCPU::removePipelineStalls(ThreadID tid)
1125 {
1126     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
1127             tid);
1128
1129     for (int stNum = 0; stNum < NumStages ; stNum++) {
1130         pipelineStage[stNum]->removeStalls(tid);
1131     }
1132
1133 }
1134
1135 void
1136 InOrderCPU::updateThreadPriority()
1137 {
1138     if (activeThreads.size() > 1)
1139     {
1140         //DEFAULT TO ROUND ROBIN SCHEME
1141         //e.g. Move highest priority to end of thread list
1142         list<ThreadID>::iterator list_begin = activeThreads.begin();
1143
1144         unsigned high_thread = *list_begin;
1145
1146         activeThreads.erase(list_begin);
1147
1148         activeThreads.push_back(high_thread);
1149     }
1150 }
1151
1152 inline void
1153 InOrderCPU::tickThreadStats()
1154 {
1155     /** Keep track of cycles that each thread is active */
1156     list<ThreadID>::iterator thread_it = activeThreads.begin();
1157     while (thread_it != activeThreads.end()) {
1158         threadCycles[*thread_it]++;
1159         thread_it++;
1160     }
1161
1162     // Keep track of cycles where SMT is active
1163     if (activeThreads.size() > 1) {
1164         smtCycles++;
1165     }
1166 }
1167
1168 void
1169 InOrderCPU::activateContext(ThreadID tid, Cycles delay)
1170 {
1171     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
1172
1173
1174     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
1175
1176     // Be sure to signal that there's some activity so the CPU doesn't
1177     // deschedule itself.
1178     activityRec.activity();
1179
1180     _status = Running;
1181 }
1182
1183 void
1184 InOrderCPU::activateNextReadyContext(Cycles delay)
1185 {
1186     DPRINTF(InOrderCPU,"Activating next ready thread\n");
1187
1188     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
1189                      delay, ActivateNextReadyThread_Pri);
1190
1191     // Be sure to signal that there's some activity so the CPU doesn't
1192     // deschedule itself.
1193     activityRec.activity();
1194
1195     _status = Running;
1196 }
1197
1198 void
1199 InOrderCPU::haltContext(ThreadID tid)
1200 {
1201     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
1202
1203     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid]);
1204
1205     activityRec.activity();
1206 }
1207
1208 void
1209 InOrderCPU::haltThread(ThreadID tid)
1210 {
1211     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
1212     deactivateThread(tid);
1213     squashThreadInPipeline(tid);
1214     haltedThreads.push_back(tid);
1215
1216     tcBase(tid)->setStatus(ThreadContext::Halted);
1217
1218     if (threadModel == SwitchOnCacheMiss) {
1219         activateNextReadyContext();
1220     }
1221 }
1222
1223 void
1224 InOrderCPU::suspendContext(ThreadID tid)
1225 {
1226     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid]);
1227 }
1228
1229 void
1230 InOrderCPU::suspendThread(ThreadID tid)
1231 {
1232     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
1233             tid);
1234     deactivateThread(tid);
1235     suspendedThreads.push_back(tid);
1236     thread[tid]->lastSuspend = curTick();
1237
1238     tcBase(tid)->setStatus(ThreadContext::Suspended);
1239 }
1240
1241 void
1242 InOrderCPU::squashThreadInPipeline(ThreadID tid)
1243 {
1244     //Squash all instructions in each stage
1245     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
1246         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
1247     }
1248 }
1249
1250 PipelineStage*
1251 InOrderCPU::getPipeStage(int stage_num)
1252 {
1253     return pipelineStage[stage_num];
1254 }
1255
1256
1257 RegIndex
1258 InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
1259 {
1260     if (reg_idx < FP_Base_DepTag) {
1261         reg_type = IntType;
1262         return isa[tid]->flattenIntIndex(reg_idx);
1263     } else if (reg_idx < Ctrl_Base_DepTag) {
1264         reg_type = FloatType;
1265         reg_idx -= FP_Base_DepTag;
1266         return isa[tid]->flattenFloatIndex(reg_idx);
1267     } else {
1268         reg_type = MiscType;
1269         return reg_idx - TheISA::Ctrl_Base_DepTag;
1270     }
1271 }
1272
1273 uint64_t
1274 InOrderCPU::readIntReg(RegIndex reg_idx, ThreadID tid)
1275 {
1276     DPRINTF(IntRegs, "[tid:%i]: Reading Int. Reg %i as %x\n",
1277             tid, reg_idx, intRegs[tid][reg_idx]);
1278
1279     return intRegs[tid][reg_idx];
1280 }
1281
1282 FloatReg
1283 InOrderCPU::readFloatReg(RegIndex reg_idx, ThreadID tid)
1284 {
1285     DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1286             tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
1287
1288     return floatRegs.f[tid][reg_idx];
1289 }
1290
1291 FloatRegBits
1292 InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
1293 {
1294     DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1295             tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
1296
1297     return floatRegs.i[tid][reg_idx];
1298 }
1299
1300 void
1301 InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid)
1302 {
1303     if (reg_idx == TheISA::ZeroReg) {
1304         DPRINTF(IntRegs, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1305                 "(Int. Reg %i) to %x\n", tid, reg_idx, val);
1306         return;
1307     } else {
1308         DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
1309                 tid, reg_idx, val);
1310
1311         intRegs[tid][reg_idx] = val;
1312     }
1313 }
1314
1315
1316 void
1317 InOrderCPU::setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid)
1318 {
1319     floatRegs.f[tid][reg_idx] = val;
1320     DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
1321             "%x, %08f\n",
1322             tid, reg_idx,
1323             floatRegs.i[tid][reg_idx],
1324             floatRegs.f[tid][reg_idx]);
1325 }
1326
1327
1328 void
1329 InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid)
1330 {
1331     floatRegs.i[tid][reg_idx] = val;
1332     DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
1333             "%x, %08f\n",
1334             tid, reg_idx,
1335             floatRegs.i[tid][reg_idx],
1336             floatRegs.f[tid][reg_idx]);
1337 }
1338
1339 uint64_t
1340 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1341 {
1342     // If Default value is set, then retrieve target thread
1343     if (tid == InvalidThreadID) {
1344         tid = TheISA::getTargetThread(tcBase(tid));
1345     }
1346
1347     if (reg_idx < FP_Base_DepTag) {
1348         // Integer Register File
1349         return readIntReg(reg_idx, tid);
1350     } else if (reg_idx < Ctrl_Base_DepTag) {
1351         // Float Register File
1352         reg_idx -= FP_Base_DepTag;
1353         return readFloatRegBits(reg_idx, tid);
1354     } else {
1355         reg_idx -= Ctrl_Base_DepTag;
1356         return readMiscReg(reg_idx, tid);  // Misc. Register File
1357     }
1358 }
1359 void
1360 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1361                               ThreadID tid)
1362 {
1363     // If Default value is set, then retrieve target thread
1364     if (tid == InvalidThreadID) {
1365         tid = TheISA::getTargetThread(tcBase(tid));
1366     }
1367
1368     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1369         setIntReg(reg_idx, val, tid);
1370     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1371         reg_idx -= FP_Base_DepTag;
1372         setFloatRegBits(reg_idx, val, tid);
1373     } else {
1374         reg_idx -= Ctrl_Base_DepTag;
1375         setMiscReg(reg_idx, val, tid); // Misc. Register File
1376     }
1377 }
1378
1379 MiscReg
1380 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1381 {
1382     return isa[tid]->readMiscRegNoEffect(misc_reg);
1383 }
1384
1385 MiscReg
1386 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1387 {
1388     return isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1389 }
1390
1391 void
1392 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1393 {
1394     isa[tid]->setMiscRegNoEffect(misc_reg, val);
1395 }
1396
1397 void
1398 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1399 {
1400     isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1401 }
1402
1403
1404 InOrderCPU::ListIt
1405 InOrderCPU::addInst(DynInstPtr inst)
1406 {
1407     ThreadID tid = inst->readTid();
1408
1409     instList[tid].push_back(inst);
1410
1411     return --(instList[tid].end());
1412 }
1413
1414 InOrderCPU::ListIt
1415 InOrderCPU::findInst(InstSeqNum seq_num, ThreadID tid)
1416 {
1417     ListIt it = instList[tid].begin();
1418     ListIt end = instList[tid].end();
1419
1420     while (it != end) {
1421         if ((*it)->seqNum == seq_num)
1422             return it;
1423         else if ((*it)->seqNum > seq_num)
1424             break;
1425
1426         it++;
1427     }
1428
1429     return instList[tid].end();
1430 }
1431
1432 void
1433 InOrderCPU::updateContextSwitchStats()
1434 {
1435     // Set Average Stat Here, then reset to 0
1436     instsPerCtxtSwitch = instsPerSwitch;
1437     instsPerSwitch = 0;
1438 }
1439
1440
1441 void
1442 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1443 {
1444     // Set the nextPC to be fetched if this is the last instruction
1445     // committed
1446     // ========
1447     // This contributes to the precise state of the CPU
1448     // which can be used when restoring a thread to the CPU after after any
1449     // type of context switching activity (fork, exception, etc.)
1450     TheISA::PCState comm_pc = inst->pcState();
1451     lastCommittedPC[tid] = comm_pc;
1452     TheISA::advancePC(comm_pc, inst->staticInst);
1453     pcState(comm_pc, tid);
1454
1455     //@todo: may be unnecessary with new-ISA-specific branch handling code
1456     if (inst->isControl()) {
1457         thread[tid]->lastGradIsBranch = true;
1458         thread[tid]->lastBranchPC = inst->pcState();
1459         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1460     } else {
1461         thread[tid]->lastGradIsBranch = false;
1462     }
1463
1464
1465     // Finalize Trace Data For Instruction
1466     if (inst->traceData) {
1467         //inst->traceData->setCycle(curTick());
1468         inst->traceData->setFetchSeq(inst->seqNum);
1469         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1470         inst->traceData->dump();
1471         delete inst->traceData;
1472         inst->traceData = NULL;
1473     }
1474
1475     // Increment active thread's instruction count
1476     instsPerSwitch++;
1477
1478     // Increment thread-state's instruction count
1479     thread[tid]->numInst++;
1480     thread[tid]->numOp++;
1481
1482     // Increment thread-state's instruction stats
1483     thread[tid]->numInsts++;
1484     thread[tid]->numOps++;
1485
1486     // Count committed insts per thread stats
1487     if (!inst->isMicroop() || inst->isLastMicroop()) {
1488         committedInsts[tid]++;
1489
1490         // Count total insts committed stat
1491         totalCommittedInsts++;
1492     }
1493
1494     committedOps[tid]++;
1495
1496     // Count SMT-committed insts per thread stat
1497     if (numActiveThreads() > 1) {
1498         if (!inst->isMicroop() || inst->isLastMicroop())
1499             smtCommittedInsts[tid]++;
1500     }
1501
1502     // Instruction-Mix Stats
1503     if (inst->isLoad()) {
1504         comLoads++;
1505     } else if (inst->isStore()) {
1506         comStores++;
1507     } else if (inst->isControl()) {
1508         comBranches++;
1509     } else if (inst->isNop()) {
1510         comNops++;
1511     } else if (inst->isNonSpeculative()) {
1512         comNonSpec++;
1513     } else if (inst->isInteger()) {
1514         comInts++;
1515     } else if (inst->isFloating()) {
1516         comFloats++;
1517     }
1518
1519     // Check for instruction-count-based events.
1520     comInstEventQueue[tid]->serviceEvents(thread[tid]->numOp);
1521
1522     // Finally, remove instruction from CPU
1523     removeInst(inst);
1524 }
1525
1526 // currently unused function, but substitute repetitive code w/this function
1527 // call
1528 void
1529 InOrderCPU::addToRemoveList(DynInstPtr inst)
1530 {
1531     removeInstsThisCycle = true;
1532     if (!inst->isRemoveList()) {
1533         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1534                 "[sn:%lli] to remove list\n",
1535                 inst->threadNumber, inst->pcState(), inst->seqNum);
1536         inst->setRemoveList();
1537         removeList.push(inst->getInstListIt());
1538     }  else {
1539         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1540                 "[sn:%lli], already remove list\n",
1541                 inst->threadNumber, inst->pcState(), inst->seqNum);
1542     }
1543
1544 }
1545
1546 void
1547 InOrderCPU::removeInst(DynInstPtr inst)
1548 {
1549     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1550             "[sn:%lli]\n",
1551             inst->threadNumber, inst->pcState(), inst->seqNum);
1552
1553     removeInstsThisCycle = true;
1554
1555     // Remove the instruction.
1556     if (!inst->isRemoveList()) {
1557         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1558                 "[sn:%lli] to remove list\n",
1559                 inst->threadNumber, inst->pcState(), inst->seqNum);
1560         inst->setRemoveList();
1561         removeList.push(inst->getInstListIt());
1562     } else {
1563         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1564                 "[sn:%lli], already on remove list\n",
1565                 inst->threadNumber, inst->pcState(), inst->seqNum);
1566     }
1567
1568 }
1569
1570 void
1571 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1572 {
1573     //assert(!instList[tid].empty());
1574
1575     removeInstsThisCycle = true;
1576
1577     ListIt inst_iter = instList[tid].end();
1578
1579     inst_iter--;
1580
1581     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1582             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1583             tid, seq_num, (*inst_iter)->seqNum);
1584
1585     while ((*inst_iter)->seqNum > seq_num) {
1586
1587         bool break_loop = (inst_iter == instList[tid].begin());
1588
1589         squashInstIt(inst_iter, tid);
1590
1591         inst_iter--;
1592
1593         if (break_loop)
1594             break;
1595     }
1596 }
1597
1598
1599 inline void
1600 InOrderCPU::squashInstIt(const ListIt inst_it, ThreadID tid)
1601 {
1602     DynInstPtr inst = (*inst_it);
1603     if (inst->threadNumber == tid) {
1604         DPRINTF(InOrderCPU, "Squashing instruction, "
1605                 "[tid:%i] [sn:%lli] PC %s\n",
1606                 inst->threadNumber,
1607                 inst->seqNum,
1608                 inst->pcState());
1609
1610         inst->setSquashed();
1611         archRegDepMap[tid].remove(inst);
1612
1613         if (!inst->isRemoveList()) {
1614             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1615                     "[sn:%lli] to remove list\n",
1616                     inst->threadNumber, inst->pcState(),
1617                     inst->seqNum);
1618             inst->setRemoveList();
1619             removeList.push(inst_it);
1620         } else {
1621             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1622                     " PC %s [sn:%lli], already on remove list\n",
1623                     inst->threadNumber, inst->pcState(),
1624                     inst->seqNum);
1625         }
1626
1627     }
1628
1629 }
1630
1631
1632 void
1633 InOrderCPU::cleanUpRemovedInsts()
1634 {
1635     while (!removeList.empty()) {
1636         DPRINTF(InOrderCPU, "Removing instruction, "
1637                 "[tid:%i] [sn:%lli] PC %s\n",
1638                 (*removeList.front())->threadNumber,
1639                 (*removeList.front())->seqNum,
1640                (*removeList.front())->pcState());
1641
1642         DynInstPtr inst = *removeList.front();
1643         ThreadID tid = inst->threadNumber;
1644
1645         // Remove From Register Dependency Map, If Necessary
1646         // archRegDepMap[tid].remove(inst);
1647
1648         // Clear if Non-Speculative
1649         if (inst->staticInst &&
1650             inst->seqNum == nonSpecSeqNum[tid] &&
1651             nonSpecInstActive[tid] == true) {
1652             nonSpecInstActive[tid] = false;
1653         }
1654
1655         inst->onInstList = false;
1656
1657         instList[tid].erase(removeList.front());
1658
1659         removeList.pop();
1660     }
1661
1662     removeInstsThisCycle = false;
1663 }
1664
1665 void
1666 InOrderCPU::cleanUpRemovedEvents()
1667 {
1668     while (!cpuEventRemoveList.empty()) {
1669         Event *cpu_event = cpuEventRemoveList.front();
1670         cpuEventRemoveList.pop();
1671         delete cpu_event;
1672     }
1673 }
1674
1675
1676 void
1677 InOrderCPU::dumpInsts()
1678 {
1679     int num = 0;
1680
1681     ListIt inst_list_it = instList[0].begin();
1682
1683     cprintf("Dumping Instruction List\n");
1684
1685     while (inst_list_it != instList[0].end()) {
1686         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1687                 "Squashed:%i\n\n",
1688                 num, (*inst_list_it)->pcState(),
1689                 (*inst_list_it)->threadNumber,
1690                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1691                 (*inst_list_it)->isSquashed());
1692         inst_list_it++;
1693         ++num;
1694     }
1695 }
1696
1697 void
1698 InOrderCPU::wakeCPU()
1699 {
1700     if (/*activityRec.active() || */tickEvent.scheduled()) {
1701         DPRINTF(Activity, "CPU already running.\n");
1702         return;
1703     }
1704
1705     DPRINTF(Activity, "Waking up CPU\n");
1706
1707     Tick extra_cycles = curCycle() - lastRunningCycle;
1708     if (extra_cycles != 0)
1709         --extra_cycles;
1710
1711     idleCycles += extra_cycles;
1712     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1713         pipelineStage[stage_num]->idleCycles += extra_cycles;
1714     }
1715
1716     numCycles += extra_cycles;
1717
1718     schedule(&tickEvent, nextCycle());
1719 }
1720
1721 // Lots of copied full system code...place into BaseCPU class?
1722 void
1723 InOrderCPU::wakeup()
1724 {
1725     if (thread[0]->status() != ThreadContext::Suspended)
1726         return;
1727
1728     wakeCPU();
1729
1730     DPRINTF(Quiesce, "Suspended Processor woken\n");
1731     threadContexts[0]->activate();
1732 }
1733
1734 void
1735 InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
1736                            Cycles delay)
1737 {
1738     // Syscall must be non-speculative, so squash from last stage
1739     unsigned squash_stage = NumStages - 1;
1740     inst->setSquashInfo(squash_stage);
1741
1742     // Squash In Pipeline Stage
1743     pipelineStage[squash_stage]->setupSquash(inst, tid);
1744
1745     // Schedule Squash Through-out Resource Pool
1746     resPool->scheduleEvent(
1747         (InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst,
1748         Cycles(0));
1749     scheduleCpuEvent(Syscall, fault, tid, inst, delay, Syscall_Pri);
1750 }
1751
1752 void
1753 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1754 {
1755     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1756
1757     DPRINTF(Activity,"Activity: syscall() called.\n");
1758
1759     // Temporarily increase this by one to account for the syscall
1760     // instruction.
1761     ++(this->thread[tid]->funcExeInst);
1762
1763     // Execute the actual syscall.
1764     this->thread[tid]->syscall(callnum);
1765
1766     // Decrease funcExeInst by one as the normal commit will handle
1767     // incrementing it.
1768     --(this->thread[tid]->funcExeInst);
1769
1770     // Clear Non-Speculative Block Variable
1771     nonSpecInstActive[tid] = false;
1772 }
1773
1774 TheISA::TLB*
1775 InOrderCPU::getITBPtr()
1776 {
1777     CacheUnit *itb_res = resPool->getInstUnit();
1778     return itb_res->tlb();
1779 }
1780
1781
1782 TheISA::TLB*
1783 InOrderCPU::getDTBPtr()
1784 {
1785     return resPool->getDataUnit()->tlb();
1786 }
1787
1788 TheISA::Decoder *
1789 InOrderCPU::getDecoderPtr(unsigned tid)
1790 {
1791     return resPool->getInstUnit()->decoder[tid];
1792 }
1793
1794 Fault
1795 InOrderCPU::read(DynInstPtr inst, Addr addr,
1796                  uint8_t *data, unsigned size, unsigned flags)
1797 {
1798     return resPool->getDataUnit()->read(inst, addr, data, size, flags);
1799 }
1800
1801 Fault
1802 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1803                   Addr addr, unsigned flags, uint64_t *write_res)
1804 {
1805     return resPool->getDataUnit()->write(inst, data, size, addr, flags,
1806                                          write_res);
1807 }