src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <algorithm>
  33
  34 #include "arch/utility.hh"
  35 #include "config/full_system.hh"
  36 #include "config/the_isa.hh"
  37 #include "cpu/activity.hh"
  38 #include "cpu/base.hh"
  39 #include "cpu/exetrace.hh"
  40 #include "cpu/inorder/cpu.hh"
  41 #include "cpu/inorder/first_stage.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource_pool.hh"
  45 #include "cpu/inorder/resources/resource_list.hh"
  46 #include "cpu/inorder/thread_context.hh"
  47 #include "cpu/inorder/thread_state.hh"
  48 #include "cpu/simple_thread.hh"
  49 #include "cpu/thread_context.hh"
  50 #include "mem/translating_port.hh"
  51 #include "params/InOrderCPU.hh"
  52 #include "sim/process.hh"
  53 #include "sim/stat_control.hh"
  54
  55 #if FULL_SYSTEM
  56 #include "cpu/quiesce_event.hh"
  57 #include "sim/system.hh"
  58 #endif
  59
  60 #if THE_ISA == ALPHA_ISA
  61 #include "arch/alpha/osfpal.hh"
  62 #endif
  63
  64 using namespace std;
  65 using namespace TheISA;
  66 using namespace ThePipeline;
  67
  68 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
  69   : Event(CPU_Tick_Pri), cpu(c)
  70 { }
  71
  72
  73 void
  74 InOrderCPU::TickEvent::process()
  75 {
  76     cpu->tick();
  77 }
  78
  79
  80 const char *
  81 InOrderCPU::TickEvent::description()
  82 {
  83     return "InOrderCPU tick event";
  84 }
  85
  86 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
  87                                Fault fault, ThreadID _tid, DynInstPtr inst,
  88                                unsigned event_pri_offset)
  89     : Event(Event::Priority((unsigned int)CPU_Tick_Pri + event_pri_offset)),
  90       cpu(_cpu)
  91 {
  92     setEvent(e_type, fault, _tid, inst);
  93 }
  94
  95
  96 std::string InOrderCPU::eventNames[NumCPUEvents] =
  97 {
  98     "ActivateThread",
  99     "ActivateNextReadyThread",
 100     "DeactivateThread",
 101     "HaltThread",
 102     "SuspendThread",
 103     "Trap",
 104     "InstGraduated",
 105     "SquashFromMemStall",
 106     "UpdatePCs"
 107 };
 108
 109 void
 110 InOrderCPU::CPUEvent::process()
 111 {
 112     switch (cpuEventType)
 113     {
 114       case ActivateThread:
 115         cpu->activateThread(tid);
 116         break;
 117
 118       case ActivateNextReadyThread:
 119         cpu->activateNextReadyThread();
 120         break;
 121
 122       case DeactivateThread:
 123         cpu->deactivateThread(tid);
 124         break;
 125
 126       case HaltThread:
 127         cpu->haltThread(tid);
 128         break;
 129
 130       case SuspendThread:
 131         cpu->suspendThread(tid);
 132         break;
 133
 134       case SquashFromMemStall:
 135         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 136         break;
 137
 138       case Trap:
 139         cpu->trapCPU(fault, tid, inst);
 140         break;
 141
 142       default:
 143         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 144     }
 145
 146     cpu->cpuEventRemoveList.push(this);
 147 }
 148
 149
 150
 151 const char *
 152 InOrderCPU::CPUEvent::description()
 153 {
 154     return "InOrderCPU event";
 155 }
 156
 157 void
 158 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 159 {
 160     assert(!scheduled() || squashed());
 161     cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
 162 }
 163
 164 void
 165 InOrderCPU::CPUEvent::unscheduleEvent()
 166 {
 167     if (scheduled())
 168         squash();
 169 }
 170
 171 InOrderCPU::InOrderCPU(Params *params)
 172     : BaseCPU(params),
 173       cpu_id(params->cpu_id),
 174       coreType("default"),
 175       _status(Idle),
 176       tickEvent(this),
 177       stageWidth(params->stageWidth),
 178       timeBuffer(2 , 2),
 179       removeInstsThisCycle(false),
 180       activityRec(params->name, NumStages, 10, params->activity),
 181 #if FULL_SYSTEM
 182       system(params->system),
 183       physmem(system->physmem),
 184 #endif // FULL_SYSTEM
 185 #ifdef DEBUG
 186       cpuEventNum(0),
 187       resReqCount(0),
 188 #endif // DEBUG
 189       switchCount(0),
 190       deferRegistration(false/*params->deferRegistration*/),
 191       stageTracing(params->stageTracing),
 192       instsPerSwitch(0)
 193 {
 194     ThreadID active_threads;
 195     cpu_params = params;
 196
 197     resPool = new ResourcePool(this, params);
 198
 199     // Resize for Multithreading CPUs
 200     thread.resize(numThreads);
 201
 202 #if FULL_SYSTEM
 203     active_threads = 1;
 204 #else
 205     active_threads = params->workload.size();
 206
 207     if (active_threads > MaxThreads) {
 208         panic("Workload Size too large. Increase the 'MaxThreads'"
 209               "in your InOrder implementation or "
 210               "edit your workload size.");
 211     }
 212
 213
 214     if (active_threads > 1) {
 215         threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 216
 217         if (threadModel == SMT) {
 218             DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 219         } else if (threadModel == SwitchOnCacheMiss) {
 220             DPRINTF(InOrderCPU, "Setting Thread Model to "
 221                     "Switch On Cache Miss\n");
 222         }
 223
 224     } else {
 225         threadModel = Single;
 226     }
 227
 228
 229
 230 #endif
 231
 232     // Bind the fetch & data ports from the resource pool.
 233     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
 234     if (fetchPortIdx == 0) {
 235         fatal("Unable to find port to fetch instructions from.\n");
 236     }
 237
 238     dataPortIdx = resPool->getPortIdx(params->dataMemPort);
 239     if (dataPortIdx == 0) {
 240         fatal("Unable to find port for data.\n");
 241     }
 242
 243     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 244 #if FULL_SYSTEM
 245         // SMT is not supported in FS mode yet.
 246         assert(numThreads == 1);
 247         thread[tid] = new Thread(this, 0);
 248 #else
 249         if (tid < (ThreadID)params->workload.size()) {
 250             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 251                     tid, params->workload[tid]->prog_fname);
 252             thread[tid] =
 253                 new Thread(this, tid, params->workload[tid]);
 254         } else {
 255             //Allocate Empty thread so M5 can use later
 256             //when scheduling threads to CPU
 257             Process* dummy_proc = params->workload[0];
 258             thread[tid] = new Thread(this, tid, dummy_proc);
 259         }
 260
 261         // Eventually set this with parameters...
 262         asid[tid] = tid;
 263 #endif
 264
 265         // Setup the TC that will serve as the interface to the threads/CPU.
 266         InOrderThreadContext *tc = new InOrderThreadContext;
 267         tc->cpu = this;
 268         tc->thread = thread[tid];
 269
 270         // Give the thread the TC.
 271         thread[tid]->tc = tc;
 272         thread[tid]->setFuncExeInst(0);
 273         globalSeqNum[tid] = 1;
 274
 275         // Add the TC to the CPU's list of TC's.
 276         this->threadContexts.push_back(tc);
 277     }
 278
 279     // Initialize TimeBuffer Stage Queues
 280     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 281         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 282         stageQueue[stNum]->id(stNum);
 283     }
 284
 285
 286     // Set Up Pipeline Stages
 287     for (int stNum=0; stNum < NumStages; stNum++) {
 288         if (stNum == 0)
 289             pipelineStage[stNum] = new FirstStage(params, stNum);
 290         else
 291             pipelineStage[stNum] = new PipelineStage(params, stNum);
 292
 293         pipelineStage[stNum]->setCPU(this);
 294         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 295         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 296
 297         // Take Care of 1st/Nth stages
 298         if (stNum > 0)
 299             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 300         if (stNum < NumStages - 1)
 301             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 302     }
 303
 304     // Initialize thread specific variables
 305     for (ThreadID tid = 0; tid < numThreads; tid++) {
 306         archRegDepMap[tid].setCPU(this);
 307
 308         nonSpecInstActive[tid] = false;
 309         nonSpecSeqNum[tid] = 0;
 310
 311         squashSeqNum[tid] = MaxAddr;
 312         lastSquashCycle[tid] = 0;
 313
 314         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 315         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 316         isa[tid].clear();
 317
 318         isa[tid].expandForMultithreading(numThreads, 1/*numVirtProcs*/);
 319
 320         // Define dummy instructions and resource requests to be used.
 321         dummyInst[tid] = new InOrderDynInst(this,
 322                                             thread[tid],
 323                                             0,
 324                                             tid,
 325                                             asid[tid]);
 326
 327         dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
 328     }
 329
 330     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 331     dummyReqInst->setSquashed();
 332     dummyReqInst->resetInstCount();
 333
 334     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 335     dummyBufferInst->setSquashed();
 336     dummyBufferInst->resetInstCount();
 337
 338     endOfSkedIt = skedCache.end();
 339     frontEndSked = createFrontEndSked();
 340
 341     lastRunningCycle = curTick();
 342
 343     // Reset CPU to reset state.
 344 #if FULL_SYSTEM
 345     Fault resetFault = new ResetFault();
 346     resetFault->invoke(tcBase());
 347 #else
 348     reset();
 349 #endif
 350
 351
 352     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 353     scheduleTickEvent(0);
 354 }
 355
 356 InOrderCPU::~InOrderCPU()
 357 {
 358     delete resPool;
 359 }
 360
 361 std::map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
 362
 363 RSkedPtr
 364 InOrderCPU::createFrontEndSked()
 365 {
 366     RSkedPtr res_sked = new ResourceSked();
 367     int stage_num = 0;
 368     StageScheduler F(res_sked, stage_num++);
 369     StageScheduler D(res_sked, stage_num++);
 370
 371     // FETCH
 372     F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
 373     F.needs(ICache, FetchUnit::InitiateFetch);
 374
 375     // DECODE
 376     D.needs(ICache, FetchUnit::CompleteFetch);
 377     D.needs(Decode, DecodeUnit::DecodeInst);
 378     D.needs(BPred, BranchPredictor::PredictBranch);
 379     D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
 380
 381
 382     DPRINTF(SkedCache, "Resource Sked created for instruction \"front_end\"\n");
 383
 384     return res_sked;
 385 }
 386
 387 RSkedPtr
 388 InOrderCPU::createBackEndSked(DynInstPtr inst)
 389 {
 390     RSkedPtr res_sked = lookupSked(inst);
 391     if (res_sked != NULL) {
 392         DPRINTF(SkedCache, "Found %s in sked cache.\n",
 393                 inst->instName());
 394         return res_sked;
 395     } else {
 396         res_sked = new ResourceSked();
 397     }
 398
 399     int stage_num = ThePipeline::BackEndStartStage;
 400     StageScheduler X(res_sked, stage_num++);
 401     StageScheduler M(res_sked, stage_num++);
 402     StageScheduler W(res_sked, stage_num++);
 403
 404     if (!inst->staticInst) {
 405         warn_once("Static Instruction Object Not Set. Can't Create"
 406                   " Back End Schedule");
 407         return NULL;
 408     }
 409
 410     // EXECUTE
 411     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 412         if (!idx || !inst->isStore()) {
 413             X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
 414         }
 415     }
 416
 417     if ( inst->isNonSpeculative() ) {
 418         // skip execution of non speculative insts until later
 419     } else if ( inst->isMemRef() ) {
 420         if ( inst->isLoad() ) {
 421             X.needs(AGEN, AGENUnit::GenerateAddr);
 422         }
 423     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 424         X.needs(MDU, MultDivUnit::StartMultDiv);
 425     } else {
 426         X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 427     }
 428
 429     if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 430         X.needs(MDU, MultDivUnit::EndMultDiv);
 431     }
 432
 433     // MEMORY
 434     if ( inst->isLoad() ) {
 435         M.needs(DCache, CacheUnit::InitiateReadData);
 436     } else if ( inst->isStore() ) {
 437         if ( inst->numSrcRegs() >= 2 ) {
 438             M.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 439         }
 440         M.needs(AGEN, AGENUnit::GenerateAddr);
 441         M.needs(DCache, CacheUnit::InitiateWriteData);
 442     }
 443
 444
 445     // WRITEBACK
 446     if ( inst->isLoad() ) {
 447         W.needs(DCache, CacheUnit::CompleteReadData);
 448     } else if ( inst->isStore() ) {
 449         W.needs(DCache, CacheUnit::CompleteWriteData);
 450     }
 451
 452     if ( inst->isNonSpeculative() ) {
 453         if ( inst->isMemRef() ) fatal("Non-Speculative Memory Instruction");
 454         W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 455     }
 456
 457     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 458         W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
 459     }
 460
 461     W.needs(Grad, GraduationUnit::GraduateInst);
 462
 463     // Insert Front Schedule into our cache of
 464     // resource schedules
 465     addToSkedCache(inst, res_sked);
 466
 467     DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
 468             inst->instName(), inst->getMachInst());
 469     res_sked->print();
 470
 471     return res_sked;
 472 }
 473
 474 void
 475 InOrderCPU::regStats()
 476 {
 477     /* Register the Resource Pool's stats here.*/
 478     resPool->regStats();
 479
 480     /* Register for each Pipeline Stage */
 481     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 482         pipelineStage[stage_num]->regStats();
 483     }
 484
 485     /* Register any of the InOrderCPU's stats here.*/
 486     instsPerCtxtSwitch
 487         .name(name() + ".instsPerContextSwitch")
 488         .desc("Instructions Committed Per Context Switch")
 489         .prereq(instsPerCtxtSwitch);
 490
 491     numCtxtSwitches
 492         .name(name() + ".contextSwitches")
 493         .desc("Number of context switches");
 494
 495     comLoads
 496         .name(name() + ".comLoads")
 497         .desc("Number of Load instructions committed");
 498
 499     comStores
 500         .name(name() + ".comStores")
 501         .desc("Number of Store instructions committed");
 502
 503     comBranches
 504         .name(name() + ".comBranches")
 505         .desc("Number of Branches instructions committed");
 506
 507     comNops
 508         .name(name() + ".comNops")
 509         .desc("Number of Nop instructions committed");
 510
 511     comNonSpec
 512         .name(name() + ".comNonSpec")
 513         .desc("Number of Non-Speculative instructions committed");
 514
 515     comInts
 516         .name(name() + ".comInts")
 517         .desc("Number of Integer instructions committed");
 518
 519     comFloats
 520         .name(name() + ".comFloats")
 521         .desc("Number of Floating Point instructions committed");
 522
 523     timesIdled
 524         .name(name() + ".timesIdled")
 525         .desc("Number of times that the entire CPU went into an idle state and"
 526               " unscheduled itself")
 527         .prereq(timesIdled);
 528
 529     idleCycles
 530         .name(name() + ".idleCycles")
 531         .desc("Number of cycles cpu's stages were not processed");
 532
 533     runCycles
 534         .name(name() + ".runCycles")
 535         .desc("Number of cycles cpu stages are processed.");
 536
 537     activity
 538         .name(name() + ".activity")
 539         .desc("Percentage of cycles cpu is active")
 540         .precision(6);
 541     activity = (runCycles / numCycles) * 100;
 542
 543     threadCycles
 544         .init(numThreads)
 545         .name(name() + ".threadCycles")
 546         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 547
 548     smtCycles
 549         .name(name() + ".smtCycles")
 550         .desc("Total number of cycles that the CPU was in SMT-mode");
 551
 552     committedInsts
 553         .init(numThreads)
 554         .name(name() + ".committedInsts")
 555         .desc("Number of Instructions Simulated (Per-Thread)");
 556
 557     smtCommittedInsts
 558         .init(numThreads)
 559         .name(name() + ".smtCommittedInsts")
 560         .desc("Number of SMT Instructions Simulated (Per-Thread)");
 561
 562     totalCommittedInsts
 563         .name(name() + ".committedInsts_total")
 564         .desc("Number of Instructions Simulated (Total)");
 565
 566     cpi
 567         .name(name() + ".cpi")
 568         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 569         .precision(6);
 570     cpi = numCycles / committedInsts;
 571
 572     smtCpi
 573         .name(name() + ".smt_cpi")
 574         .desc("CPI: Total SMT-CPI")
 575         .precision(6);
 576     smtCpi = smtCycles / smtCommittedInsts;
 577
 578     totalCpi
 579         .name(name() + ".cpi_total")
 580         .desc("CPI: Total CPI of All Threads")
 581         .precision(6);
 582     totalCpi = numCycles / totalCommittedInsts;
 583
 584     ipc
 585         .name(name() + ".ipc")
 586         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 587         .precision(6);
 588     ipc =  committedInsts / numCycles;
 589
 590     smtIpc
 591         .name(name() + ".smt_ipc")
 592         .desc("IPC: Total SMT-IPC")
 593         .precision(6);
 594     smtIpc = smtCommittedInsts / smtCycles;
 595
 596     totalIpc
 597         .name(name() + ".ipc_total")
 598         .desc("IPC: Total IPC of All Threads")
 599         .precision(6);
 600         totalIpc =  totalCommittedInsts / numCycles;
 601
 602     BaseCPU::regStats();
 603 }
 604
 605
 606 void
 607 InOrderCPU::tick()
 608 {
 609     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 610
 611     ++numCycles;
 612
 613     bool pipes_idle = true;
 614
 615     //Tick each of the stages
 616     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 617         pipelineStage[stNum]->tick();
 618
 619         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 620     }
 621
 622     if (pipes_idle)
 623         idleCycles++;
 624     else
 625         runCycles++;
 626
 627     // Now advance the time buffers one tick
 628     timeBuffer.advance();
 629     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 630         stageQueue[sqNum]->advance();
 631     }
 632     activityRec.advance();
 633
 634     // Any squashed events, or insts then remove them now
 635     cleanUpRemovedEvents();
 636     cleanUpRemovedInsts();
 637
 638     // Re-schedule CPU for this cycle
 639     if (!tickEvent.scheduled()) {
 640         if (_status == SwitchedOut) {
 641             // increment stat
 642             lastRunningCycle = curTick();
 643         } else if (!activityRec.active()) {
 644             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 645             lastRunningCycle = curTick();
 646             timesIdled++;
 647         } else {
 648             //Tick next_tick = curTick() + cycles(1);
 649             //tickEvent.schedule(next_tick);
 650             schedule(&tickEvent, nextCycle(curTick() + 1));
 651             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 652                     nextCycle(curTick() + 1));
 653         }
 654     }
 655
 656     tickThreadStats();
 657     updateThreadPriority();
 658 }
 659
 660
 661 void
 662 InOrderCPU::init()
 663 {
 664     if (!deferRegistration) {
 665         registerThreadContexts();
 666     }
 667
 668     // Set inSyscall so that the CPU doesn't squash when initially
 669     // setting up registers.
 670     for (ThreadID tid = 0; tid < numThreads; ++tid)
 671         thread[tid]->inSyscall = true;
 672
 673 #if FULL_SYSTEM
 674     for (ThreadID tid = 0; tid < numThreads; tid++) {
 675         ThreadContext *src_tc = threadContexts[tid];
 676         TheISA::initCPU(src_tc, src_tc->contextId());
 677     }
 678 #endif
 679
 680     // Clear inSyscall.
 681     for (ThreadID tid = 0; tid < numThreads; ++tid)
 682         thread[tid]->inSyscall = false;
 683
 684     // Call Initializiation Routine for Resource Pool
 685     resPool->init();
 686 }
 687
 688 void
 689 InOrderCPU::reset()
 690 {
 691     for (int i = 0; i < numThreads; i++) {
 692         isa[i].reset(coreType, numThreads,
 693                      1/*numVirtProcs*/, dynamic_cast<BaseCPU*>(this));
 694     }
 695 }
 696
 697 Port*
 698 InOrderCPU::getPort(const std::string &if_name, int idx)
 699 {
 700     return resPool->getPort(if_name, idx);
 701 }
 702
 703 #if FULL_SYSTEM
 704 Fault
 705 InOrderCPU::hwrei(ThreadID tid)
 706 {
 707     panic("hwrei: Unimplemented");
 708
 709     return NoFault;
 710 }
 711
 712
 713 bool
 714 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 715 {
 716     panic("simPalCheck: Unimplemented");
 717
 718     return true;
 719 }
 720
 721
 722 Fault
 723 InOrderCPU::getInterrupts()
 724 {
 725     // Check if there are any outstanding interrupts
 726     return interrupts->getInterrupt(threadContexts[0]);
 727 }
 728
 729
 730 void
 731 InOrderCPU::processInterrupts(Fault interrupt)
 732 {
 733     // Check for interrupts here.  For now can copy the code that
 734     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 735     // is the one that handles the interrupts.
 736     // @todo: Possibly consolidate the interrupt checking code.
 737     // @todo: Allow other threads to handle interrupts.
 738
 739     assert(interrupt != NoFault);
 740     interrupts->updateIntrInfo(threadContexts[0]);
 741
 742     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 743
 744     // Note: Context ID ok here? Impl. of FS mode needs to revisit this
 745     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 746 }
 747
 748
 749 void
 750 InOrderCPU::updateMemPorts()
 751 {
 752     // Update all ThreadContext's memory ports (Functional/Virtual
 753     // Ports)
 754     ThreadID size = thread.size();
 755     for (ThreadID i = 0; i < size; ++i)
 756         thread[i]->connectMemPorts(thread[i]->getTC());
 757 }
 758 #endif
 759
 760 void
 761 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 762 {
 763     //@ Squash Pipeline during TRAP
 764     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 765 }
 766
 767 void
 768 InOrderCPU::trapCPU(Fault fault, ThreadID tid, DynInstPtr inst)
 769 {
 770     fault->invoke(tcBase(tid), inst->staticInst);
 771 }
 772
 773 void
 774 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 775 {
 776     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 777 }
 778
 779
 780 void
 781 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 782                                 ThreadID tid)
 783 {
 784     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 785
 786     // Squash all instructions in each stage including
 787     // instruction that caused the squash (seq_num - 1)
 788     // NOTE: The stage bandwidth needs to be cleared so thats why
 789     //       the stalling instruction is squashed as well. The stalled
 790     //       instruction is previously placed in another intermediate buffer
 791     //       while it's stall is being handled.
 792     InstSeqNum squash_seq_num = seq_num - 1;
 793
 794     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 795         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 796     }
 797 }
 798
 799 void
 800 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 801                              ThreadID tid, DynInstPtr inst,
 802                              unsigned delay, unsigned event_pri_offset)
 803 {
 804     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 805                                        event_pri_offset);
 806
 807     Tick sked_tick = nextCycle(curTick() + ticks(delay));
 808     if (delay >= 0) {
 809         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 810                 eventNames[c_event], curTick() + delay, tid);
 811         schedule(cpu_event, sked_tick);
 812     } else {
 813         cpu_event->process();
 814         cpuEventRemoveList.push(cpu_event);
 815     }
 816
 817     // Broadcast event to the Resource Pool
 818     // Need to reset tid just in case this is a dummy instruction
 819     inst->setTid(tid);
 820     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 821 }
 822
 823 bool
 824 InOrderCPU::isThreadActive(ThreadID tid)
 825 {
 826   list<ThreadID>::iterator isActive =
 827       std::find(activeThreads.begin(), activeThreads.end(), tid);
 828
 829     return (isActive != activeThreads.end());
 830 }
 831
 832 bool
 833 InOrderCPU::isThreadReady(ThreadID tid)
 834 {
 835   list<ThreadID>::iterator isReady =
 836       std::find(readyThreads.begin(), readyThreads.end(), tid);
 837
 838     return (isReady != readyThreads.end());
 839 }
 840
 841 bool
 842 InOrderCPU::isThreadSuspended(ThreadID tid)
 843 {
 844   list<ThreadID>::iterator isSuspended =
 845       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
 846
 847     return (isSuspended != suspendedThreads.end());
 848 }
 849
 850 void
 851 InOrderCPU::activateNextReadyThread()
 852 {
 853     if (readyThreads.size() >= 1) {
 854         ThreadID ready_tid = readyThreads.front();
 855
 856         // Activate in Pipeline
 857         activateThread(ready_tid);
 858
 859         // Activate in Resource Pool
 860         resPool->activateAll(ready_tid);
 861
 862         list<ThreadID>::iterator ready_it =
 863             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
 864         readyThreads.erase(ready_it);
 865     } else {
 866         DPRINTF(InOrderCPU,
 867                 "Attempting to activate new thread, but No Ready Threads to"
 868                 "activate.\n");
 869         DPRINTF(InOrderCPU,
 870                 "Unable to switch to next active thread.\n");
 871     }
 872 }
 873
 874 void
 875 InOrderCPU::activateThread(ThreadID tid)
 876 {
 877     if (isThreadSuspended(tid)) {
 878         DPRINTF(InOrderCPU,
 879                 "Removing [tid:%i] from suspended threads list.\n", tid);
 880
 881         list<ThreadID>::iterator susp_it =
 882             std::find(suspendedThreads.begin(), suspendedThreads.end(),
 883                       tid);
 884         suspendedThreads.erase(susp_it);
 885     }
 886
 887     if (threadModel == SwitchOnCacheMiss &&
 888         numActiveThreads() == 1) {
 889         DPRINTF(InOrderCPU,
 890                 "Ignoring activation of [tid:%i], since [tid:%i] is "
 891                 "already running.\n", tid, activeThreadId());
 892
 893         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
 894                 tid);
 895
 896         readyThreads.push_back(tid);
 897
 898     } else if (!isThreadActive(tid)) {
 899         DPRINTF(InOrderCPU,
 900                 "Adding [tid:%i] to active threads list.\n", tid);
 901         activeThreads.push_back(tid);
 902
 903         activateThreadInPipeline(tid);
 904
 905         thread[tid]->lastActivate = curTick();
 906
 907         tcBase(tid)->setStatus(ThreadContext::Active);
 908
 909         wakeCPU();
 910
 911         numCtxtSwitches++;
 912     }
 913 }
 914
 915 void
 916 InOrderCPU::activateThreadInPipeline(ThreadID tid)
 917 {
 918     for (int stNum=0; stNum < NumStages; stNum++) {
 919         pipelineStage[stNum]->activateThread(tid);
 920     }
 921 }
 922
 923 void
 924 InOrderCPU::deactivateContext(ThreadID tid, int delay)
 925 {
 926     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
 927
 928     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
 929
 930     // Be sure to signal that there's some activity so the CPU doesn't
 931     // deschedule itself.
 932     activityRec.activity();
 933
 934     _status = Running;
 935 }
 936
 937 void
 938 InOrderCPU::deactivateThread(ThreadID tid)
 939 {
 940     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
 941
 942     if (isThreadActive(tid)) {
 943         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
 944                 tid);
 945         list<ThreadID>::iterator thread_it =
 946             std::find(activeThreads.begin(), activeThreads.end(), tid);
 947
 948         removePipelineStalls(*thread_it);
 949
 950         activeThreads.erase(thread_it);
 951
 952         // Ideally, this should be triggered from the
 953         // suspendContext/Thread functions
 954         tcBase(tid)->setStatus(ThreadContext::Suspended);
 955     }
 956
 957     assert(!isThreadActive(tid));
 958 }
 959
 960 void
 961 InOrderCPU::removePipelineStalls(ThreadID tid)
 962 {
 963     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
 964             tid);
 965
 966     for (int stNum = 0; stNum < NumStages ; stNum++) {
 967         pipelineStage[stNum]->removeStalls(tid);
 968     }
 969
 970 }
 971
 972 void
 973 InOrderCPU::updateThreadPriority()
 974 {
 975     if (activeThreads.size() > 1)
 976     {
 977         //DEFAULT TO ROUND ROBIN SCHEME
 978         //e.g. Move highest priority to end of thread list
 979         list<ThreadID>::iterator list_begin = activeThreads.begin();
 980         list<ThreadID>::iterator list_end   = activeThreads.end();
 981
 982         unsigned high_thread = *list_begin;
 983
 984         activeThreads.erase(list_begin);
 985
 986         activeThreads.push_back(high_thread);
 987     }
 988 }
 989
 990 inline void
 991 InOrderCPU::tickThreadStats()
 992 {
 993     /** Keep track of cycles that each thread is active */
 994     list<ThreadID>::iterator thread_it = activeThreads.begin();
 995     while (thread_it != activeThreads.end()) {
 996         threadCycles[*thread_it]++;
 997         thread_it++;
 998     }
 999
1000     // Keep track of cycles where SMT is active
1001     if (activeThreads.size() > 1) {
1002         smtCycles++;
1003     }
1004 }
1005
1006 void
1007 InOrderCPU::activateContext(ThreadID tid, int delay)
1008 {
1009     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
1010
1011
1012     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
1013
1014     // Be sure to signal that there's some activity so the CPU doesn't
1015     // deschedule itself.
1016     activityRec.activity();
1017
1018     _status = Running;
1019 }
1020
1021 void
1022 InOrderCPU::activateNextReadyContext(int delay)
1023 {
1024     DPRINTF(InOrderCPU,"Activating next ready thread\n");
1025
1026     // NOTE: Add 5 to the event priority so that we always activate
1027     // threads after we've finished deactivating, squashing,etc.
1028     // other threads
1029     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
1030                      delay, 5);
1031
1032     // Be sure to signal that there's some activity so the CPU doesn't
1033     // deschedule itself.
1034     activityRec.activity();
1035
1036     _status = Running;
1037 }
1038
1039 void
1040 InOrderCPU::haltContext(ThreadID tid, int delay)
1041 {
1042     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
1043
1044     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
1045
1046     activityRec.activity();
1047 }
1048
1049 void
1050 InOrderCPU::haltThread(ThreadID tid)
1051 {
1052     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
1053     deactivateThread(tid);
1054     squashThreadInPipeline(tid);
1055     haltedThreads.push_back(tid);
1056
1057     tcBase(tid)->setStatus(ThreadContext::Halted);
1058
1059     if (threadModel == SwitchOnCacheMiss) {
1060         activateNextReadyContext();
1061     }
1062 }
1063
1064 void
1065 InOrderCPU::suspendContext(ThreadID tid, int delay)
1066 {
1067     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
1068 }
1069
1070 void
1071 InOrderCPU::suspendThread(ThreadID tid)
1072 {
1073     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
1074             tid);
1075     deactivateThread(tid);
1076     suspendedThreads.push_back(tid);
1077     thread[tid]->lastSuspend = curTick();
1078
1079     tcBase(tid)->setStatus(ThreadContext::Suspended);
1080 }
1081
1082 void
1083 InOrderCPU::squashThreadInPipeline(ThreadID tid)
1084 {
1085     //Squash all instructions in each stage
1086     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
1087         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
1088     }
1089 }
1090
1091 PipelineStage*
1092 InOrderCPU::getPipeStage(int stage_num)
1093 {
1094     return pipelineStage[stage_num];
1095 }
1096
1097 uint64_t
1098 InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
1099 {
1100     return intRegs[tid][reg_idx];
1101 }
1102
1103 FloatReg
1104 InOrderCPU::readFloatReg(int reg_idx, ThreadID tid)
1105 {
1106     return floatRegs.f[tid][reg_idx];
1107 }
1108
1109 FloatRegBits
1110 InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
1111 {;
1112     return floatRegs.i[tid][reg_idx];
1113 }
1114
1115 void
1116 InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
1117 {
1118     intRegs[tid][reg_idx] = val;
1119 }
1120
1121
1122 void
1123 InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid)
1124 {
1125     floatRegs.f[tid][reg_idx] = val;
1126 }
1127
1128
1129 void
1130 InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid)
1131 {
1132     floatRegs.i[tid][reg_idx] = val;
1133 }
1134
1135 uint64_t
1136 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1137 {
1138     // If Default value is set, then retrieve target thread
1139     if (tid == InvalidThreadID) {
1140         tid = TheISA::getTargetThread(tcBase(tid));
1141     }
1142
1143     if (reg_idx < FP_Base_DepTag) {
1144         // Integer Register File
1145         return readIntReg(reg_idx, tid);
1146     } else if (reg_idx < Ctrl_Base_DepTag) {
1147         // Float Register File
1148         reg_idx -= FP_Base_DepTag;
1149         return readFloatRegBits(reg_idx, tid);
1150     } else {
1151         reg_idx -= Ctrl_Base_DepTag;
1152         return readMiscReg(reg_idx, tid);  // Misc. Register File
1153     }
1154 }
1155 void
1156 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1157                               ThreadID tid)
1158 {
1159     // If Default value is set, then retrieve target thread
1160     if (tid == InvalidThreadID) {
1161         tid = TheISA::getTargetThread(tcBase(tid));
1162     }
1163
1164     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1165         setIntReg(reg_idx, val, tid);
1166     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1167         reg_idx -= FP_Base_DepTag;
1168         setFloatRegBits(reg_idx, val, tid);
1169     } else {
1170         reg_idx -= Ctrl_Base_DepTag;
1171         setMiscReg(reg_idx, val, tid); // Misc. Register File
1172     }
1173 }
1174
1175 MiscReg
1176 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1177 {
1178     return isa[tid].readMiscRegNoEffect(misc_reg);
1179 }
1180
1181 MiscReg
1182 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1183 {
1184     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1185 }
1186
1187 void
1188 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1189 {
1190     isa[tid].setMiscRegNoEffect(misc_reg, val);
1191 }
1192
1193 void
1194 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1195 {
1196     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1197 }
1198
1199
1200 InOrderCPU::ListIt
1201 InOrderCPU::addInst(DynInstPtr &inst)
1202 {
1203     ThreadID tid = inst->readTid();
1204
1205     instList[tid].push_back(inst);
1206
1207     return --(instList[tid].end());
1208 }
1209
1210 void
1211 InOrderCPU::updateContextSwitchStats()
1212 {
1213     // Set Average Stat Here, then reset to 0
1214     instsPerCtxtSwitch = instsPerSwitch;
1215     instsPerSwitch = 0;
1216 }
1217
1218
1219 void
1220 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1221 {
1222     // Set the CPU's PCs - This contributes to the precise state of the CPU
1223     // which can be used when restoring a thread to the CPU after after any
1224     // type of context switching activity (fork, exception, etc.)
1225     pcState(inst->pcState(), tid);
1226
1227     if (inst->isControl()) {
1228         thread[tid]->lastGradIsBranch = true;
1229         thread[tid]->lastBranchPC = inst->pcState();
1230         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1231     } else {
1232         thread[tid]->lastGradIsBranch = false;
1233     }
1234
1235
1236     // Finalize Trace Data For Instruction
1237     if (inst->traceData) {
1238         //inst->traceData->setCycle(curTick());
1239         inst->traceData->setFetchSeq(inst->seqNum);
1240         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1241         inst->traceData->dump();
1242         delete inst->traceData;
1243         inst->traceData = NULL;
1244     }
1245
1246     // Increment active thread's instruction count
1247     instsPerSwitch++;
1248
1249     // Increment thread-state's instruction count
1250     thread[tid]->numInst++;
1251
1252     // Increment thread-state's instruction stats
1253     thread[tid]->numInsts++;
1254
1255     // Count committed insts per thread stats
1256     committedInsts[tid]++;
1257
1258     // Count total insts committed stat
1259     totalCommittedInsts++;
1260
1261     // Count SMT-committed insts per thread stat
1262     if (numActiveThreads() > 1) {
1263         smtCommittedInsts[tid]++;
1264     }
1265
1266     // Instruction-Mix Stats
1267     if (inst->isLoad()) {
1268         comLoads++;
1269     } else if (inst->isStore()) {
1270         comStores++;
1271     } else if (inst->isControl()) {
1272         comBranches++;
1273     } else if (inst->isNop()) {
1274         comNops++;
1275     } else if (inst->isNonSpeculative()) {
1276         comNonSpec++;
1277     } else if (inst->isInteger()) {
1278         comInts++;
1279     } else if (inst->isFloating()) {
1280         comFloats++;
1281     }
1282
1283     // Check for instruction-count-based events.
1284     comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1285
1286     // Broadcast to other resources an instruction
1287     // has been completed
1288     resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
1289                            0, 0, tid);
1290
1291     // Finally, remove instruction from CPU
1292     removeInst(inst);
1293 }
1294
1295 // currently unused function, but substitute repetitive code w/this function
1296 // call
1297 void
1298 InOrderCPU::addToRemoveList(DynInstPtr &inst)
1299 {
1300     removeInstsThisCycle = true;
1301     if (!inst->isRemoveList()) {
1302         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1303                 "[sn:%lli] to remove list\n",
1304                 inst->threadNumber, inst->pcState(), inst->seqNum);
1305         inst->setRemoveList();
1306         removeList.push(inst->getInstListIt());
1307     }  else {
1308         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1309                 "[sn:%lli], already remove list\n",
1310                 inst->threadNumber, inst->pcState(), inst->seqNum);
1311     }
1312
1313 }
1314
1315 void
1316 InOrderCPU::removeInst(DynInstPtr &inst)
1317 {
1318     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1319             "[sn:%lli]\n",
1320             inst->threadNumber, inst->pcState(), inst->seqNum);
1321
1322     removeInstsThisCycle = true;
1323
1324     // Remove the instruction.
1325     if (!inst->isRemoveList()) {
1326         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1327                 "[sn:%lli] to remove list\n",
1328                 inst->threadNumber, inst->pcState(), inst->seqNum);
1329         inst->setRemoveList();
1330         removeList.push(inst->getInstListIt());
1331     } else {
1332         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1333                 "[sn:%lli], already on remove list\n",
1334                 inst->threadNumber, inst->pcState(), inst->seqNum);
1335     }
1336
1337 }
1338
1339 void
1340 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1341 {
1342     //assert(!instList[tid].empty());
1343
1344     removeInstsThisCycle = true;
1345
1346     ListIt inst_iter = instList[tid].end();
1347
1348     inst_iter--;
1349
1350     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1351             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1352             tid, seq_num, (*inst_iter)->seqNum);
1353
1354     while ((*inst_iter)->seqNum > seq_num) {
1355
1356         bool break_loop = (inst_iter == instList[tid].begin());
1357
1358         squashInstIt(inst_iter, tid);
1359
1360         inst_iter--;
1361
1362         if (break_loop)
1363             break;
1364     }
1365 }
1366
1367
1368 inline void
1369 InOrderCPU::squashInstIt(const ListIt &instIt, ThreadID tid)
1370 {
1371     if ((*instIt)->threadNumber == tid) {
1372         DPRINTF(InOrderCPU, "Squashing instruction, "
1373                 "[tid:%i] [sn:%lli] PC %s\n",
1374                 (*instIt)->threadNumber,
1375                 (*instIt)->seqNum,
1376                 (*instIt)->pcState());
1377
1378         (*instIt)->setSquashed();
1379
1380         if (!(*instIt)->isRemoveList()) {
1381             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1382                     "[sn:%lli] to remove list\n",
1383                     (*instIt)->threadNumber, (*instIt)->pcState(),
1384                     (*instIt)->seqNum);
1385             (*instIt)->setRemoveList();
1386             removeList.push(instIt);
1387         } else {
1388             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1389                     " PC %s [sn:%lli], already on remove list\n",
1390                     (*instIt)->threadNumber, (*instIt)->pcState(),
1391                     (*instIt)->seqNum);
1392         }
1393
1394     }
1395
1396 }
1397
1398
1399 void
1400 InOrderCPU::cleanUpRemovedInsts()
1401 {
1402     while (!removeList.empty()) {
1403         DPRINTF(InOrderCPU, "Removing instruction, "
1404                 "[tid:%i] [sn:%lli] PC %s\n",
1405                 (*removeList.front())->threadNumber,
1406                 (*removeList.front())->seqNum,
1407                (*removeList.front())->pcState());
1408
1409         DynInstPtr inst = *removeList.front();
1410         ThreadID tid = inst->threadNumber;
1411
1412         // Remove From Register Dependency Map, If Necessary
1413         archRegDepMap[(*removeList.front())->threadNumber].
1414             remove((*removeList.front()));
1415
1416
1417         // Clear if Non-Speculative
1418         if (inst->staticInst &&
1419             inst->seqNum == nonSpecSeqNum[tid] &&
1420             nonSpecInstActive[tid] == true) {
1421             nonSpecInstActive[tid] = false;
1422         }
1423
1424         instList[tid].erase(removeList.front());
1425
1426         removeList.pop();
1427     }
1428
1429     removeInstsThisCycle = false;
1430 }
1431
1432 void
1433 InOrderCPU::cleanUpRemovedEvents()
1434 {
1435     while (!cpuEventRemoveList.empty()) {
1436         Event *cpu_event = cpuEventRemoveList.front();
1437         cpuEventRemoveList.pop();
1438         delete cpu_event;
1439     }
1440 }
1441
1442
1443 void
1444 InOrderCPU::dumpInsts()
1445 {
1446     int num = 0;
1447
1448     ListIt inst_list_it = instList[0].begin();
1449
1450     cprintf("Dumping Instruction List\n");
1451
1452     while (inst_list_it != instList[0].end()) {
1453         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1454                 "Squashed:%i\n\n",
1455                 num, (*inst_list_it)->pcState(),
1456                 (*inst_list_it)->threadNumber,
1457                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1458                 (*inst_list_it)->isSquashed());
1459         inst_list_it++;
1460         ++num;
1461     }
1462 }
1463
1464 void
1465 InOrderCPU::wakeCPU()
1466 {
1467     if (/*activityRec.active() || */tickEvent.scheduled()) {
1468         DPRINTF(Activity, "CPU already running.\n");
1469         return;
1470     }
1471
1472     DPRINTF(Activity, "Waking up CPU\n");
1473
1474     Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
1475
1476     idleCycles += extra_cycles;
1477     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1478         pipelineStage[stage_num]->idleCycles += extra_cycles;
1479     }
1480
1481     numCycles += extra_cycles;
1482
1483     schedule(&tickEvent, nextCycle(curTick()));
1484 }
1485
1486 #if FULL_SYSTEM
1487
1488 void
1489 InOrderCPU::wakeup()
1490 {
1491     if (thread[0]->status() != ThreadContext::Suspended)
1492         return;
1493
1494     wakeCPU();
1495
1496     DPRINTF(Quiesce, "Suspended Processor woken\n");
1497     threadContexts[0]->activate();
1498 }
1499 #endif
1500
1501 #if !FULL_SYSTEM
1502 void
1503 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1504 {
1505     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1506
1507     DPRINTF(Activity,"Activity: syscall() called.\n");
1508
1509     // Temporarily increase this by one to account for the syscall
1510     // instruction.
1511     ++(this->thread[tid]->funcExeInst);
1512
1513     // Execute the actual syscall.
1514     this->thread[tid]->syscall(callnum);
1515
1516     // Decrease funcExeInst by one as the normal commit will handle
1517     // incrementing it.
1518     --(this->thread[tid]->funcExeInst);
1519
1520     // Clear Non-Speculative Block Variable
1521     nonSpecInstActive[tid] = false;
1522 }
1523 #endif
1524
1525 TheISA::TLB*
1526 InOrderCPU::getITBPtr()
1527 {
1528     CacheUnit *itb_res =
1529         dynamic_cast<CacheUnit*>(resPool->getResource(fetchPortIdx));
1530     return itb_res->tlb();
1531 }
1532
1533
1534 TheISA::TLB*
1535 InOrderCPU::getDTBPtr()
1536 {
1537     CacheUnit *dtb_res =
1538         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1539     return dtb_res->tlb();
1540 }
1541
1542 Fault
1543 InOrderCPU::read(DynInstPtr inst, Addr addr,
1544                  uint8_t *data, unsigned size, unsigned flags)
1545 {
1546     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1547     //       you want to run w/out caches?
1548     CacheUnit *cache_res =
1549         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1550
1551     return cache_res->read(inst, addr, data, size, flags);
1552 }
1553
1554 Fault
1555 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1556                   Addr addr, unsigned flags, uint64_t *write_res)
1557 {
1558     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1559     //       you want to run w/out caches?
1560     CacheUnit *cache_res =
1561         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1562     return cache_res->write(inst, data, size, addr, flags, write_res);
1563 }