src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <algorithm>
  33
  34 #include "arch/utility.hh"
  35 #include "config/full_system.hh"
  36 #include "config/the_isa.hh"
  37 #include "cpu/activity.hh"
  38 #include "cpu/base.hh"
  39 #include "cpu/exetrace.hh"
  40 #include "cpu/inorder/cpu.hh"
  41 #include "cpu/inorder/first_stage.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource_pool.hh"
  45 #include "cpu/inorder/resources/resource_list.hh"
  46 #include "cpu/inorder/thread_context.hh"
  47 #include "cpu/inorder/thread_state.hh"
  48 #include "cpu/simple_thread.hh"
  49 #include "cpu/thread_context.hh"
  50 #include "mem/translating_port.hh"
  51 #include "params/InOrderCPU.hh"
  52 #include "sim/process.hh"
  53 #include "sim/stat_control.hh"
  54
  55 #if FULL_SYSTEM
  56 #include "cpu/quiesce_event.hh"
  57 #include "sim/system.hh"
  58 #endif
  59
  60 #if THE_ISA == ALPHA_ISA
  61 #include "arch/alpha/osfpal.hh"
  62 #endif
  63
  64 using namespace std;
  65 using namespace TheISA;
  66 using namespace ThePipeline;
  67
  68 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
  69   : Event(CPU_Tick_Pri), cpu(c)
  70 { }
  71
  72
  73 void
  74 InOrderCPU::TickEvent::process()
  75 {
  76     cpu->tick();
  77 }
  78
  79
  80 const char *
  81 InOrderCPU::TickEvent::description()
  82 {
  83     return "InOrderCPU tick event";
  84 }
  85
  86 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
  87                                Fault fault, ThreadID _tid, DynInstPtr inst,
  88                                unsigned event_pri_offset)
  89     : Event(Event::Priority((unsigned int)CPU_Tick_Pri + event_pri_offset)),
  90       cpu(_cpu)
  91 {
  92     setEvent(e_type, fault, _tid, inst);
  93 }
  94
  95
  96 std::string InOrderCPU::eventNames[NumCPUEvents] =
  97 {
  98     "ActivateThread",
  99     "ActivateNextReadyThread",
 100     "DeactivateThread",
 101     "HaltThread",
 102     "SuspendThread",
 103     "Trap",
 104     "InstGraduated",
 105     "SquashFromMemStall",
 106     "UpdatePCs"
 107 };
 108
 109 void
 110 InOrderCPU::CPUEvent::process()
 111 {
 112     switch (cpuEventType)
 113     {
 114       case ActivateThread:
 115         cpu->activateThread(tid);
 116         break;
 117
 118       case ActivateNextReadyThread:
 119         cpu->activateNextReadyThread();
 120         break;
 121
 122       case DeactivateThread:
 123         cpu->deactivateThread(tid);
 124         break;
 125
 126       case HaltThread:
 127         cpu->haltThread(tid);
 128         break;
 129
 130       case SuspendThread:
 131         cpu->suspendThread(tid);
 132         break;
 133
 134       case SquashFromMemStall:
 135         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 136         break;
 137
 138       case Trap:
 139         cpu->trapCPU(fault, tid, inst);
 140         break;
 141
 142       default:
 143         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 144     }
 145
 146     cpu->cpuEventRemoveList.push(this);
 147 }
 148
 149
 150
 151 const char *
 152 InOrderCPU::CPUEvent::description()
 153 {
 154     return "InOrderCPU event";
 155 }
 156
 157 void
 158 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 159 {
 160     assert(!scheduled() || squashed());
 161     cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
 162 }
 163
 164 void
 165 InOrderCPU::CPUEvent::unscheduleEvent()
 166 {
 167     if (scheduled())
 168         squash();
 169 }
 170
 171 InOrderCPU::InOrderCPU(Params *params)
 172     : BaseCPU(params),
 173       cpu_id(params->cpu_id),
 174       coreType("default"),
 175       _status(Idle),
 176       tickEvent(this),
 177       stageWidth(params->stageWidth),
 178       timeBuffer(2 , 2),
 179       removeInstsThisCycle(false),
 180       activityRec(params->name, NumStages, 10, params->activity),
 181 #if FULL_SYSTEM
 182       system(params->system),
 183       physmem(system->physmem),
 184 #endif // FULL_SYSTEM
 185 #ifdef DEBUG
 186       cpuEventNum(0),
 187       resReqCount(0),
 188 #endif // DEBUG
 189       switchCount(0),
 190       deferRegistration(false/*params->deferRegistration*/),
 191       stageTracing(params->stageTracing),
 192       instsPerSwitch(0)
 193 {
 194     ThreadID active_threads;
 195     cpu_params = params;
 196
 197     resPool = new ResourcePool(this, params);
 198
 199     // Resize for Multithreading CPUs
 200     thread.resize(numThreads);
 201
 202 #if FULL_SYSTEM
 203     active_threads = 1;
 204 #else
 205     active_threads = params->workload.size();
 206
 207     if (active_threads > MaxThreads) {
 208         panic("Workload Size too large. Increase the 'MaxThreads'"
 209               "in your InOrder implementation or "
 210               "edit your workload size.");
 211     }
 212
 213
 214     if (active_threads > 1) {
 215         threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 216
 217         if (threadModel == SMT) {
 218             DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 219         } else if (threadModel == SwitchOnCacheMiss) {
 220             DPRINTF(InOrderCPU, "Setting Thread Model to "
 221                     "Switch On Cache Miss\n");
 222         }
 223
 224     } else {
 225         threadModel = Single;
 226     }
 227
 228
 229
 230 #endif
 231
 232     // Bind the fetch & data ports from the resource pool.
 233     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
 234     if (fetchPortIdx == 0) {
 235         fatal("Unable to find port to fetch instructions from.\n");
 236     }
 237
 238     dataPortIdx = resPool->getPortIdx(params->dataMemPort);
 239     if (dataPortIdx == 0) {
 240         fatal("Unable to find port for data.\n");
 241     }
 242
 243     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 244 #if FULL_SYSTEM
 245         // SMT is not supported in FS mode yet.
 246         assert(numThreads == 1);
 247         thread[tid] = new Thread(this, 0);
 248 #else
 249         if (tid < (ThreadID)params->workload.size()) {
 250             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 251                     tid, params->workload[tid]->prog_fname);
 252             thread[tid] =
 253                 new Thread(this, tid, params->workload[tid]);
 254         } else {
 255             //Allocate Empty thread so M5 can use later
 256             //when scheduling threads to CPU
 257             Process* dummy_proc = params->workload[0];
 258             thread[tid] = new Thread(this, tid, dummy_proc);
 259         }
 260
 261         // Eventually set this with parameters...
 262         asid[tid] = tid;
 263 #endif
 264
 265         // Setup the TC that will serve as the interface to the threads/CPU.
 266         InOrderThreadContext *tc = new InOrderThreadContext;
 267         tc->cpu = this;
 268         tc->thread = thread[tid];
 269
 270         // Give the thread the TC.
 271         thread[tid]->tc = tc;
 272         thread[tid]->setFuncExeInst(0);
 273         globalSeqNum[tid] = 1;
 274
 275         // Add the TC to the CPU's list of TC's.
 276         this->threadContexts.push_back(tc);
 277     }
 278
 279     // Initialize TimeBuffer Stage Queues
 280     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 281         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 282         stageQueue[stNum]->id(stNum);
 283     }
 284
 285
 286     // Set Up Pipeline Stages
 287     for (int stNum=0; stNum < NumStages; stNum++) {
 288         if (stNum == 0)
 289             pipelineStage[stNum] = new FirstStage(params, stNum);
 290         else
 291             pipelineStage[stNum] = new PipelineStage(params, stNum);
 292
 293         pipelineStage[stNum]->setCPU(this);
 294         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 295         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 296
 297         // Take Care of 1st/Nth stages
 298         if (stNum > 0)
 299             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 300         if (stNum < NumStages - 1)
 301             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 302     }
 303
 304     // Initialize thread specific variables
 305     for (ThreadID tid = 0; tid < numThreads; tid++) {
 306         archRegDepMap[tid].setCPU(this);
 307
 308         nonSpecInstActive[tid] = false;
 309         nonSpecSeqNum[tid] = 0;
 310
 311         squashSeqNum[tid] = MaxAddr;
 312         lastSquashCycle[tid] = 0;
 313
 314         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 315         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 316         isa[tid].clear();
 317
 318         // Define dummy instructions and resource requests to be used.
 319         dummyInst[tid] = new InOrderDynInst(this,
 320                                             thread[tid],
 321                                             0,
 322                                             tid,
 323                                             asid[tid]);
 324
 325         dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
 326     }
 327
 328     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 329     dummyReqInst->setSquashed();
 330     dummyReqInst->resetInstCount();
 331
 332     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 333     dummyBufferInst->setSquashed();
 334     dummyBufferInst->resetInstCount();
 335
 336     endOfSkedIt = skedCache.end();
 337     frontEndSked = createFrontEndSked();
 338
 339     lastRunningCycle = curTick();
 340
 341     // Reset CPU to reset state.
 342 #if FULL_SYSTEM
 343     Fault resetFault = new ResetFault();
 344     resetFault->invoke(tcBase());
 345 #endif
 346
 347
 348     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 349     scheduleTickEvent(0);
 350 }
 351
 352 InOrderCPU::~InOrderCPU()
 353 {
 354     delete resPool;
 355
 356     std::map<SkedID, ThePipeline::RSkedPtr>::iterator sked_it =
 357         skedCache.begin();
 358     std::map<SkedID, ThePipeline::RSkedPtr>::iterator sked_end =
 359         skedCache.end();
 360
 361     while (sked_it != sked_end) {
 362         delete (*sked_it).second;
 363         sked_it++;
 364     }
 365     skedCache.clear();
 366 }
 367
 368 std::map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
 369
 370 RSkedPtr
 371 InOrderCPU::createFrontEndSked()
 372 {
 373     RSkedPtr res_sked = new ResourceSked();
 374     int stage_num = 0;
 375     StageScheduler F(res_sked, stage_num++);
 376     StageScheduler D(res_sked, stage_num++);
 377
 378     // FETCH
 379     F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
 380     F.needs(ICache, FetchUnit::InitiateFetch);
 381
 382     // DECODE
 383     D.needs(ICache, FetchUnit::CompleteFetch);
 384     D.needs(Decode, DecodeUnit::DecodeInst);
 385     D.needs(BPred, BranchPredictor::PredictBranch);
 386     D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
 387
 388
 389     DPRINTF(SkedCache, "Resource Sked created for instruction \"front_end\"\n");
 390
 391     return res_sked;
 392 }
 393
 394 RSkedPtr
 395 InOrderCPU::createBackEndSked(DynInstPtr inst)
 396 {
 397     RSkedPtr res_sked = lookupSked(inst);
 398     if (res_sked != NULL) {
 399         DPRINTF(SkedCache, "Found %s in sked cache.\n",
 400                 inst->instName());
 401         return res_sked;
 402     } else {
 403         res_sked = new ResourceSked();
 404     }
 405
 406     int stage_num = ThePipeline::BackEndStartStage;
 407     StageScheduler X(res_sked, stage_num++);
 408     StageScheduler M(res_sked, stage_num++);
 409     StageScheduler W(res_sked, stage_num++);
 410
 411     if (!inst->staticInst) {
 412         warn_once("Static Instruction Object Not Set. Can't Create"
 413                   " Back End Schedule");
 414         return NULL;
 415     }
 416
 417     // EXECUTE
 418     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 419         if (!idx || !inst->isStore()) {
 420             X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
 421         }
 422     }
 423
 424     if ( inst->isNonSpeculative() ) {
 425         // skip execution of non speculative insts until later
 426     } else if ( inst->isMemRef() ) {
 427         if ( inst->isLoad() ) {
 428             X.needs(AGEN, AGENUnit::GenerateAddr);
 429         }
 430     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 431         X.needs(MDU, MultDivUnit::StartMultDiv);
 432     } else {
 433         X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 434     }
 435
 436     if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 437         X.needs(MDU, MultDivUnit::EndMultDiv);
 438     }
 439
 440     // MEMORY
 441     if ( inst->isLoad() ) {
 442         M.needs(DCache, CacheUnit::InitiateReadData);
 443     } else if ( inst->isStore() ) {
 444         if ( inst->numSrcRegs() >= 2 ) {
 445             M.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 446         }
 447         M.needs(AGEN, AGENUnit::GenerateAddr);
 448         M.needs(DCache, CacheUnit::InitiateWriteData);
 449     }
 450
 451
 452     // WRITEBACK
 453     if ( inst->isLoad() ) {
 454         W.needs(DCache, CacheUnit::CompleteReadData);
 455     } else if ( inst->isStore() ) {
 456         W.needs(DCache, CacheUnit::CompleteWriteData);
 457     }
 458
 459     if ( inst->isNonSpeculative() ) {
 460         if ( inst->isMemRef() ) fatal("Non-Speculative Memory Instruction");
 461         W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 462     }
 463
 464     W.needs(Grad, GraduationUnit::GraduateInst);
 465
 466     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 467         W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
 468     }
 469
 470     // Insert Back Schedule into our cache of
 471     // resource schedules
 472     addToSkedCache(inst, res_sked);
 473
 474     DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
 475             inst->instName(), inst->getMachInst());
 476     res_sked->print();
 477
 478     return res_sked;
 479 }
 480
 481 void
 482 InOrderCPU::regStats()
 483 {
 484     /* Register the Resource Pool's stats here.*/
 485     resPool->regStats();
 486
 487     /* Register for each Pipeline Stage */
 488     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 489         pipelineStage[stage_num]->regStats();
 490     }
 491
 492     /* Register any of the InOrderCPU's stats here.*/
 493     instsPerCtxtSwitch
 494         .name(name() + ".instsPerContextSwitch")
 495         .desc("Instructions Committed Per Context Switch")
 496         .prereq(instsPerCtxtSwitch);
 497
 498     numCtxtSwitches
 499         .name(name() + ".contextSwitches")
 500         .desc("Number of context switches");
 501
 502     comLoads
 503         .name(name() + ".comLoads")
 504         .desc("Number of Load instructions committed");
 505
 506     comStores
 507         .name(name() + ".comStores")
 508         .desc("Number of Store instructions committed");
 509
 510     comBranches
 511         .name(name() + ".comBranches")
 512         .desc("Number of Branches instructions committed");
 513
 514     comNops
 515         .name(name() + ".comNops")
 516         .desc("Number of Nop instructions committed");
 517
 518     comNonSpec
 519         .name(name() + ".comNonSpec")
 520         .desc("Number of Non-Speculative instructions committed");
 521
 522     comInts
 523         .name(name() + ".comInts")
 524         .desc("Number of Integer instructions committed");
 525
 526     comFloats
 527         .name(name() + ".comFloats")
 528         .desc("Number of Floating Point instructions committed");
 529
 530     timesIdled
 531         .name(name() + ".timesIdled")
 532         .desc("Number of times that the entire CPU went into an idle state and"
 533               " unscheduled itself")
 534         .prereq(timesIdled);
 535
 536     idleCycles
 537         .name(name() + ".idleCycles")
 538         .desc("Number of cycles cpu's stages were not processed");
 539
 540     runCycles
 541         .name(name() + ".runCycles")
 542         .desc("Number of cycles cpu stages are processed.");
 543
 544     activity
 545         .name(name() + ".activity")
 546         .desc("Percentage of cycles cpu is active")
 547         .precision(6);
 548     activity = (runCycles / numCycles) * 100;
 549
 550     threadCycles
 551         .init(numThreads)
 552         .name(name() + ".threadCycles")
 553         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 554
 555     smtCycles
 556         .name(name() + ".smtCycles")
 557         .desc("Total number of cycles that the CPU was in SMT-mode");
 558
 559     committedInsts
 560         .init(numThreads)
 561         .name(name() + ".committedInsts")
 562         .desc("Number of Instructions Simulated (Per-Thread)");
 563
 564     smtCommittedInsts
 565         .init(numThreads)
 566         .name(name() + ".smtCommittedInsts")
 567         .desc("Number of SMT Instructions Simulated (Per-Thread)");
 568
 569     totalCommittedInsts
 570         .name(name() + ".committedInsts_total")
 571         .desc("Number of Instructions Simulated (Total)");
 572
 573     cpi
 574         .name(name() + ".cpi")
 575         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 576         .precision(6);
 577     cpi = numCycles / committedInsts;
 578
 579     smtCpi
 580         .name(name() + ".smt_cpi")
 581         .desc("CPI: Total SMT-CPI")
 582         .precision(6);
 583     smtCpi = smtCycles / smtCommittedInsts;
 584
 585     totalCpi
 586         .name(name() + ".cpi_total")
 587         .desc("CPI: Total CPI of All Threads")
 588         .precision(6);
 589     totalCpi = numCycles / totalCommittedInsts;
 590
 591     ipc
 592         .name(name() + ".ipc")
 593         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 594         .precision(6);
 595     ipc =  committedInsts / numCycles;
 596
 597     smtIpc
 598         .name(name() + ".smt_ipc")
 599         .desc("IPC: Total SMT-IPC")
 600         .precision(6);
 601     smtIpc = smtCommittedInsts / smtCycles;
 602
 603     totalIpc
 604         .name(name() + ".ipc_total")
 605         .desc("IPC: Total IPC of All Threads")
 606         .precision(6);
 607         totalIpc =  totalCommittedInsts / numCycles;
 608
 609     BaseCPU::regStats();
 610 }
 611
 612
 613 void
 614 InOrderCPU::tick()
 615 {
 616     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 617
 618     ++numCycles;
 619
 620     bool pipes_idle = true;
 621
 622     //Tick each of the stages
 623     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 624         pipelineStage[stNum]->tick();
 625
 626         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 627     }
 628
 629     if (pipes_idle)
 630         idleCycles++;
 631     else
 632         runCycles++;
 633
 634     // Now advance the time buffers one tick
 635     timeBuffer.advance();
 636     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 637         stageQueue[sqNum]->advance();
 638     }
 639     activityRec.advance();
 640
 641     // Any squashed events, or insts then remove them now
 642     cleanUpRemovedEvents();
 643     cleanUpRemovedInsts();
 644
 645     // Re-schedule CPU for this cycle
 646     if (!tickEvent.scheduled()) {
 647         if (_status == SwitchedOut) {
 648             // increment stat
 649             lastRunningCycle = curTick();
 650         } else if (!activityRec.active()) {
 651             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 652             lastRunningCycle = curTick();
 653             timesIdled++;
 654         } else {
 655             //Tick next_tick = curTick() + cycles(1);
 656             //tickEvent.schedule(next_tick);
 657             schedule(&tickEvent, nextCycle(curTick() + 1));
 658             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 659                     nextCycle(curTick() + 1));
 660         }
 661     }
 662
 663     tickThreadStats();
 664     updateThreadPriority();
 665 }
 666
 667
 668 void
 669 InOrderCPU::init()
 670 {
 671     if (!deferRegistration) {
 672         registerThreadContexts();
 673     }
 674
 675     // Set inSyscall so that the CPU doesn't squash when initially
 676     // setting up registers.
 677     for (ThreadID tid = 0; tid < numThreads; ++tid)
 678         thread[tid]->inSyscall = true;
 679
 680 #if FULL_SYSTEM
 681     for (ThreadID tid = 0; tid < numThreads; tid++) {
 682         ThreadContext *src_tc = threadContexts[tid];
 683         TheISA::initCPU(src_tc, src_tc->contextId());
 684     }
 685 #endif
 686
 687     // Clear inSyscall.
 688     for (ThreadID tid = 0; tid < numThreads; ++tid)
 689         thread[tid]->inSyscall = false;
 690
 691     // Call Initializiation Routine for Resource Pool
 692     resPool->init();
 693 }
 694
 695 Port*
 696 InOrderCPU::getPort(const std::string &if_name, int idx)
 697 {
 698     return resPool->getPort(if_name, idx);
 699 }
 700
 701 #if FULL_SYSTEM
 702 Fault
 703 InOrderCPU::hwrei(ThreadID tid)
 704 {
 705     panic("hwrei: Unimplemented");
 706
 707     return NoFault;
 708 }
 709
 710
 711 bool
 712 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 713 {
 714     panic("simPalCheck: Unimplemented");
 715
 716     return true;
 717 }
 718
 719
 720 Fault
 721 InOrderCPU::getInterrupts()
 722 {
 723     // Check if there are any outstanding interrupts
 724     return interrupts->getInterrupt(threadContexts[0]);
 725 }
 726
 727
 728 void
 729 InOrderCPU::processInterrupts(Fault interrupt)
 730 {
 731     // Check for interrupts here.  For now can copy the code that
 732     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 733     // is the one that handles the interrupts.
 734     // @todo: Possibly consolidate the interrupt checking code.
 735     // @todo: Allow other threads to handle interrupts.
 736
 737     assert(interrupt != NoFault);
 738     interrupts->updateIntrInfo(threadContexts[0]);
 739
 740     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 741
 742     // Note: Context ID ok here? Impl. of FS mode needs to revisit this
 743     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 744 }
 745
 746
 747 void
 748 InOrderCPU::updateMemPorts()
 749 {
 750     // Update all ThreadContext's memory ports (Functional/Virtual
 751     // Ports)
 752     ThreadID size = thread.size();
 753     for (ThreadID i = 0; i < size; ++i)
 754         thread[i]->connectMemPorts(thread[i]->getTC());
 755 }
 756 #endif
 757
 758 void
 759 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 760 {
 761     //@ Squash Pipeline during TRAP
 762     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 763 }
 764
 765 void
 766 InOrderCPU::trapCPU(Fault fault, ThreadID tid, DynInstPtr inst)
 767 {
 768     fault->invoke(tcBase(tid), inst->staticInst);
 769 }
 770
 771 void
 772 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 773 {
 774     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 775 }
 776
 777
 778 void
 779 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 780                                 ThreadID tid)
 781 {
 782     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 783
 784     // Squash all instructions in each stage including
 785     // instruction that caused the squash (seq_num - 1)
 786     // NOTE: The stage bandwidth needs to be cleared so thats why
 787     //       the stalling instruction is squashed as well. The stalled
 788     //       instruction is previously placed in another intermediate buffer
 789     //       while it's stall is being handled.
 790     InstSeqNum squash_seq_num = seq_num - 1;
 791
 792     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 793         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 794     }
 795 }
 796
 797 void
 798 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 799                              ThreadID tid, DynInstPtr inst,
 800                              unsigned delay, unsigned event_pri_offset)
 801 {
 802     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 803                                        event_pri_offset);
 804
 805     Tick sked_tick = nextCycle(curTick() + ticks(delay));
 806     if (delay >= 0) {
 807         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 808                 eventNames[c_event], curTick() + delay, tid);
 809         schedule(cpu_event, sked_tick);
 810     } else {
 811         cpu_event->process();
 812         cpuEventRemoveList.push(cpu_event);
 813     }
 814
 815     // Broadcast event to the Resource Pool
 816     // Need to reset tid just in case this is a dummy instruction
 817     inst->setTid(tid);
 818     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 819 }
 820
 821 bool
 822 InOrderCPU::isThreadActive(ThreadID tid)
 823 {
 824   list<ThreadID>::iterator isActive =
 825       std::find(activeThreads.begin(), activeThreads.end(), tid);
 826
 827     return (isActive != activeThreads.end());
 828 }
 829
 830 bool
 831 InOrderCPU::isThreadReady(ThreadID tid)
 832 {
 833   list<ThreadID>::iterator isReady =
 834       std::find(readyThreads.begin(), readyThreads.end(), tid);
 835
 836     return (isReady != readyThreads.end());
 837 }
 838
 839 bool
 840 InOrderCPU::isThreadSuspended(ThreadID tid)
 841 {
 842   list<ThreadID>::iterator isSuspended =
 843       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
 844
 845     return (isSuspended != suspendedThreads.end());
 846 }
 847
 848 void
 849 InOrderCPU::activateNextReadyThread()
 850 {
 851     if (readyThreads.size() >= 1) {
 852         ThreadID ready_tid = readyThreads.front();
 853
 854         // Activate in Pipeline
 855         activateThread(ready_tid);
 856
 857         // Activate in Resource Pool
 858         resPool->activateAll(ready_tid);
 859
 860         list<ThreadID>::iterator ready_it =
 861             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
 862         readyThreads.erase(ready_it);
 863     } else {
 864         DPRINTF(InOrderCPU,
 865                 "Attempting to activate new thread, but No Ready Threads to"
 866                 "activate.\n");
 867         DPRINTF(InOrderCPU,
 868                 "Unable to switch to next active thread.\n");
 869     }
 870 }
 871
 872 void
 873 InOrderCPU::activateThread(ThreadID tid)
 874 {
 875     if (isThreadSuspended(tid)) {
 876         DPRINTF(InOrderCPU,
 877                 "Removing [tid:%i] from suspended threads list.\n", tid);
 878
 879         list<ThreadID>::iterator susp_it =
 880             std::find(suspendedThreads.begin(), suspendedThreads.end(),
 881                       tid);
 882         suspendedThreads.erase(susp_it);
 883     }
 884
 885     if (threadModel == SwitchOnCacheMiss &&
 886         numActiveThreads() == 1) {
 887         DPRINTF(InOrderCPU,
 888                 "Ignoring activation of [tid:%i], since [tid:%i] is "
 889                 "already running.\n", tid, activeThreadId());
 890
 891         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
 892                 tid);
 893
 894         readyThreads.push_back(tid);
 895
 896     } else if (!isThreadActive(tid)) {
 897         DPRINTF(InOrderCPU,
 898                 "Adding [tid:%i] to active threads list.\n", tid);
 899         activeThreads.push_back(tid);
 900
 901         activateThreadInPipeline(tid);
 902
 903         thread[tid]->lastActivate = curTick();
 904
 905         tcBase(tid)->setStatus(ThreadContext::Active);
 906
 907         wakeCPU();
 908
 909         numCtxtSwitches++;
 910     }
 911 }
 912
 913 void
 914 InOrderCPU::activateThreadInPipeline(ThreadID tid)
 915 {
 916     for (int stNum=0; stNum < NumStages; stNum++) {
 917         pipelineStage[stNum]->activateThread(tid);
 918     }
 919 }
 920
 921 void
 922 InOrderCPU::deactivateContext(ThreadID tid, int delay)
 923 {
 924     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
 925
 926     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
 927
 928     // Be sure to signal that there's some activity so the CPU doesn't
 929     // deschedule itself.
 930     activityRec.activity();
 931
 932     _status = Running;
 933 }
 934
 935 void
 936 InOrderCPU::deactivateThread(ThreadID tid)
 937 {
 938     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
 939
 940     if (isThreadActive(tid)) {
 941         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
 942                 tid);
 943         list<ThreadID>::iterator thread_it =
 944             std::find(activeThreads.begin(), activeThreads.end(), tid);
 945
 946         removePipelineStalls(*thread_it);
 947
 948         activeThreads.erase(thread_it);
 949
 950         // Ideally, this should be triggered from the
 951         // suspendContext/Thread functions
 952         tcBase(tid)->setStatus(ThreadContext::Suspended);
 953     }
 954
 955     assert(!isThreadActive(tid));
 956 }
 957
 958 void
 959 InOrderCPU::removePipelineStalls(ThreadID tid)
 960 {
 961     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
 962             tid);
 963
 964     for (int stNum = 0; stNum < NumStages ; stNum++) {
 965         pipelineStage[stNum]->removeStalls(tid);
 966     }
 967
 968 }
 969
 970 void
 971 InOrderCPU::updateThreadPriority()
 972 {
 973     if (activeThreads.size() > 1)
 974     {
 975         //DEFAULT TO ROUND ROBIN SCHEME
 976         //e.g. Move highest priority to end of thread list
 977         list<ThreadID>::iterator list_begin = activeThreads.begin();
 978         list<ThreadID>::iterator list_end   = activeThreads.end();
 979
 980         unsigned high_thread = *list_begin;
 981
 982         activeThreads.erase(list_begin);
 983
 984         activeThreads.push_back(high_thread);
 985     }
 986 }
 987
 988 inline void
 989 InOrderCPU::tickThreadStats()
 990 {
 991     /** Keep track of cycles that each thread is active */
 992     list<ThreadID>::iterator thread_it = activeThreads.begin();
 993     while (thread_it != activeThreads.end()) {
 994         threadCycles[*thread_it]++;
 995         thread_it++;
 996     }
 997
 998     // Keep track of cycles where SMT is active
 999     if (activeThreads.size() > 1) {
1000         smtCycles++;
1001     }
1002 }
1003
1004 void
1005 InOrderCPU::activateContext(ThreadID tid, int delay)
1006 {
1007     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
1008
1009
1010     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
1011
1012     // Be sure to signal that there's some activity so the CPU doesn't
1013     // deschedule itself.
1014     activityRec.activity();
1015
1016     _status = Running;
1017 }
1018
1019 void
1020 InOrderCPU::activateNextReadyContext(int delay)
1021 {
1022     DPRINTF(InOrderCPU,"Activating next ready thread\n");
1023
1024     // NOTE: Add 5 to the event priority so that we always activate
1025     // threads after we've finished deactivating, squashing,etc.
1026     // other threads
1027     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
1028                      delay, 5);
1029
1030     // Be sure to signal that there's some activity so the CPU doesn't
1031     // deschedule itself.
1032     activityRec.activity();
1033
1034     _status = Running;
1035 }
1036
1037 void
1038 InOrderCPU::haltContext(ThreadID tid, int delay)
1039 {
1040     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
1041
1042     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
1043
1044     activityRec.activity();
1045 }
1046
1047 void
1048 InOrderCPU::haltThread(ThreadID tid)
1049 {
1050     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
1051     deactivateThread(tid);
1052     squashThreadInPipeline(tid);
1053     haltedThreads.push_back(tid);
1054
1055     tcBase(tid)->setStatus(ThreadContext::Halted);
1056
1057     if (threadModel == SwitchOnCacheMiss) {
1058         activateNextReadyContext();
1059     }
1060 }
1061
1062 void
1063 InOrderCPU::suspendContext(ThreadID tid, int delay)
1064 {
1065     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
1066 }
1067
1068 void
1069 InOrderCPU::suspendThread(ThreadID tid)
1070 {
1071     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
1072             tid);
1073     deactivateThread(tid);
1074     suspendedThreads.push_back(tid);
1075     thread[tid]->lastSuspend = curTick();
1076
1077     tcBase(tid)->setStatus(ThreadContext::Suspended);
1078 }
1079
1080 void
1081 InOrderCPU::squashThreadInPipeline(ThreadID tid)
1082 {
1083     //Squash all instructions in each stage
1084     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
1085         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
1086     }
1087 }
1088
1089 PipelineStage*
1090 InOrderCPU::getPipeStage(int stage_num)
1091 {
1092     return pipelineStage[stage_num];
1093 }
1094
1095 uint64_t
1096 InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
1097 {
1098     return intRegs[tid][reg_idx];
1099 }
1100
1101 FloatReg
1102 InOrderCPU::readFloatReg(int reg_idx, ThreadID tid)
1103 {
1104     return floatRegs.f[tid][reg_idx];
1105 }
1106
1107 FloatRegBits
1108 InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
1109 {;
1110     return floatRegs.i[tid][reg_idx];
1111 }
1112
1113 void
1114 InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
1115 {
1116     intRegs[tid][reg_idx] = val;
1117 }
1118
1119
1120 void
1121 InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid)
1122 {
1123     floatRegs.f[tid][reg_idx] = val;
1124 }
1125
1126
1127 void
1128 InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid)
1129 {
1130     floatRegs.i[tid][reg_idx] = val;
1131 }
1132
1133 uint64_t
1134 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1135 {
1136     // If Default value is set, then retrieve target thread
1137     if (tid == InvalidThreadID) {
1138         tid = TheISA::getTargetThread(tcBase(tid));
1139     }
1140
1141     if (reg_idx < FP_Base_DepTag) {
1142         // Integer Register File
1143         return readIntReg(reg_idx, tid);
1144     } else if (reg_idx < Ctrl_Base_DepTag) {
1145         // Float Register File
1146         reg_idx -= FP_Base_DepTag;
1147         return readFloatRegBits(reg_idx, tid);
1148     } else {
1149         reg_idx -= Ctrl_Base_DepTag;
1150         return readMiscReg(reg_idx, tid);  // Misc. Register File
1151     }
1152 }
1153 void
1154 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1155                               ThreadID tid)
1156 {
1157     // If Default value is set, then retrieve target thread
1158     if (tid == InvalidThreadID) {
1159         tid = TheISA::getTargetThread(tcBase(tid));
1160     }
1161
1162     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1163         setIntReg(reg_idx, val, tid);
1164     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1165         reg_idx -= FP_Base_DepTag;
1166         setFloatRegBits(reg_idx, val, tid);
1167     } else {
1168         reg_idx -= Ctrl_Base_DepTag;
1169         setMiscReg(reg_idx, val, tid); // Misc. Register File
1170     }
1171 }
1172
1173 MiscReg
1174 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1175 {
1176     return isa[tid].readMiscRegNoEffect(misc_reg);
1177 }
1178
1179 MiscReg
1180 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1181 {
1182     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1183 }
1184
1185 void
1186 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1187 {
1188     isa[tid].setMiscRegNoEffect(misc_reg, val);
1189 }
1190
1191 void
1192 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1193 {
1194     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1195 }
1196
1197
1198 InOrderCPU::ListIt
1199 InOrderCPU::addInst(DynInstPtr &inst)
1200 {
1201     ThreadID tid = inst->readTid();
1202
1203     instList[tid].push_back(inst);
1204
1205     return --(instList[tid].end());
1206 }
1207
1208 void
1209 InOrderCPU::updateContextSwitchStats()
1210 {
1211     // Set Average Stat Here, then reset to 0
1212     instsPerCtxtSwitch = instsPerSwitch;
1213     instsPerSwitch = 0;
1214 }
1215
1216
1217 void
1218 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1219 {
1220     // Set the CPU's PCs - This contributes to the precise state of the CPU
1221     // which can be used when restoring a thread to the CPU after after any
1222     // type of context switching activity (fork, exception, etc.)
1223     pcState(inst->pcState(), tid);
1224
1225     if (inst->isControl()) {
1226         thread[tid]->lastGradIsBranch = true;
1227         thread[tid]->lastBranchPC = inst->pcState();
1228         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1229     } else {
1230         thread[tid]->lastGradIsBranch = false;
1231     }
1232
1233
1234     // Finalize Trace Data For Instruction
1235     if (inst->traceData) {
1236         //inst->traceData->setCycle(curTick());
1237         inst->traceData->setFetchSeq(inst->seqNum);
1238         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1239         inst->traceData->dump();
1240         delete inst->traceData;
1241         inst->traceData = NULL;
1242     }
1243
1244     // Increment active thread's instruction count
1245     instsPerSwitch++;
1246
1247     // Increment thread-state's instruction count
1248     thread[tid]->numInst++;
1249
1250     // Increment thread-state's instruction stats
1251     thread[tid]->numInsts++;
1252
1253     // Count committed insts per thread stats
1254     committedInsts[tid]++;
1255
1256     // Count total insts committed stat
1257     totalCommittedInsts++;
1258
1259     // Count SMT-committed insts per thread stat
1260     if (numActiveThreads() > 1) {
1261         smtCommittedInsts[tid]++;
1262     }
1263
1264     // Instruction-Mix Stats
1265     if (inst->isLoad()) {
1266         comLoads++;
1267     } else if (inst->isStore()) {
1268         comStores++;
1269     } else if (inst->isControl()) {
1270         comBranches++;
1271     } else if (inst->isNop()) {
1272         comNops++;
1273     } else if (inst->isNonSpeculative()) {
1274         comNonSpec++;
1275     } else if (inst->isInteger()) {
1276         comInts++;
1277     } else if (inst->isFloating()) {
1278         comFloats++;
1279     }
1280
1281     // Check for instruction-count-based events.
1282     comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1283
1284     // Broadcast to other resources an instruction
1285     // has been completed
1286     resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
1287                            0, 0, tid);
1288
1289     // Finally, remove instruction from CPU
1290     removeInst(inst);
1291 }
1292
1293 // currently unused function, but substitute repetitive code w/this function
1294 // call
1295 void
1296 InOrderCPU::addToRemoveList(DynInstPtr &inst)
1297 {
1298     removeInstsThisCycle = true;
1299     if (!inst->isRemoveList()) {
1300         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1301                 "[sn:%lli] to remove list\n",
1302                 inst->threadNumber, inst->pcState(), inst->seqNum);
1303         inst->setRemoveList();
1304         removeList.push(inst->getInstListIt());
1305     }  else {
1306         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1307                 "[sn:%lli], already remove list\n",
1308                 inst->threadNumber, inst->pcState(), inst->seqNum);
1309     }
1310
1311 }
1312
1313 void
1314 InOrderCPU::removeInst(DynInstPtr &inst)
1315 {
1316     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1317             "[sn:%lli]\n",
1318             inst->threadNumber, inst->pcState(), inst->seqNum);
1319
1320     removeInstsThisCycle = true;
1321
1322     // Remove the instruction.
1323     if (!inst->isRemoveList()) {
1324         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1325                 "[sn:%lli] to remove list\n",
1326                 inst->threadNumber, inst->pcState(), inst->seqNum);
1327         inst->setRemoveList();
1328         removeList.push(inst->getInstListIt());
1329     } else {
1330         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1331                 "[sn:%lli], already on remove list\n",
1332                 inst->threadNumber, inst->pcState(), inst->seqNum);
1333     }
1334
1335 }
1336
1337 void
1338 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1339 {
1340     //assert(!instList[tid].empty());
1341
1342     removeInstsThisCycle = true;
1343
1344     ListIt inst_iter = instList[tid].end();
1345
1346     inst_iter--;
1347
1348     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1349             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1350             tid, seq_num, (*inst_iter)->seqNum);
1351
1352     while ((*inst_iter)->seqNum > seq_num) {
1353
1354         bool break_loop = (inst_iter == instList[tid].begin());
1355
1356         squashInstIt(inst_iter, tid);
1357
1358         inst_iter--;
1359
1360         if (break_loop)
1361             break;
1362     }
1363 }
1364
1365
1366 inline void
1367 InOrderCPU::squashInstIt(const ListIt &instIt, ThreadID tid)
1368 {
1369     if ((*instIt)->threadNumber == tid) {
1370         DPRINTF(InOrderCPU, "Squashing instruction, "
1371                 "[tid:%i] [sn:%lli] PC %s\n",
1372                 (*instIt)->threadNumber,
1373                 (*instIt)->seqNum,
1374                 (*instIt)->pcState());
1375
1376         (*instIt)->setSquashed();
1377
1378         if (!(*instIt)->isRemoveList()) {
1379             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1380                     "[sn:%lli] to remove list\n",
1381                     (*instIt)->threadNumber, (*instIt)->pcState(),
1382                     (*instIt)->seqNum);
1383             (*instIt)->setRemoveList();
1384             removeList.push(instIt);
1385         } else {
1386             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1387                     " PC %s [sn:%lli], already on remove list\n",
1388                     (*instIt)->threadNumber, (*instIt)->pcState(),
1389                     (*instIt)->seqNum);
1390         }
1391
1392     }
1393
1394 }
1395
1396
1397 void
1398 InOrderCPU::cleanUpRemovedInsts()
1399 {
1400     while (!removeList.empty()) {
1401         DPRINTF(InOrderCPU, "Removing instruction, "
1402                 "[tid:%i] [sn:%lli] PC %s\n",
1403                 (*removeList.front())->threadNumber,
1404                 (*removeList.front())->seqNum,
1405                (*removeList.front())->pcState());
1406
1407         DynInstPtr inst = *removeList.front();
1408         ThreadID tid = inst->threadNumber;
1409
1410         // Remove From Register Dependency Map, If Necessary
1411         archRegDepMap[(*removeList.front())->threadNumber].
1412             remove((*removeList.front()));
1413
1414
1415         // Clear if Non-Speculative
1416         if (inst->staticInst &&
1417             inst->seqNum == nonSpecSeqNum[tid] &&
1418             nonSpecInstActive[tid] == true) {
1419             nonSpecInstActive[tid] = false;
1420         }
1421
1422         instList[tid].erase(removeList.front());
1423
1424         removeList.pop();
1425     }
1426
1427     removeInstsThisCycle = false;
1428 }
1429
1430 void
1431 InOrderCPU::cleanUpRemovedEvents()
1432 {
1433     while (!cpuEventRemoveList.empty()) {
1434         Event *cpu_event = cpuEventRemoveList.front();
1435         cpuEventRemoveList.pop();
1436         delete cpu_event;
1437     }
1438 }
1439
1440
1441 void
1442 InOrderCPU::dumpInsts()
1443 {
1444     int num = 0;
1445
1446     ListIt inst_list_it = instList[0].begin();
1447
1448     cprintf("Dumping Instruction List\n");
1449
1450     while (inst_list_it != instList[0].end()) {
1451         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1452                 "Squashed:%i\n\n",
1453                 num, (*inst_list_it)->pcState(),
1454                 (*inst_list_it)->threadNumber,
1455                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1456                 (*inst_list_it)->isSquashed());
1457         inst_list_it++;
1458         ++num;
1459     }
1460 }
1461
1462 void
1463 InOrderCPU::wakeCPU()
1464 {
1465     if (/*activityRec.active() || */tickEvent.scheduled()) {
1466         DPRINTF(Activity, "CPU already running.\n");
1467         return;
1468     }
1469
1470     DPRINTF(Activity, "Waking up CPU\n");
1471
1472     Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
1473
1474     idleCycles += extra_cycles;
1475     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1476         pipelineStage[stage_num]->idleCycles += extra_cycles;
1477     }
1478
1479     numCycles += extra_cycles;
1480
1481     schedule(&tickEvent, nextCycle(curTick()));
1482 }
1483
1484 #if FULL_SYSTEM
1485
1486 void
1487 InOrderCPU::wakeup()
1488 {
1489     if (thread[0]->status() != ThreadContext::Suspended)
1490         return;
1491
1492     wakeCPU();
1493
1494     DPRINTF(Quiesce, "Suspended Processor woken\n");
1495     threadContexts[0]->activate();
1496 }
1497 #endif
1498
1499 #if !FULL_SYSTEM
1500 void
1501 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1502 {
1503     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1504
1505     DPRINTF(Activity,"Activity: syscall() called.\n");
1506
1507     // Temporarily increase this by one to account for the syscall
1508     // instruction.
1509     ++(this->thread[tid]->funcExeInst);
1510
1511     // Execute the actual syscall.
1512     this->thread[tid]->syscall(callnum);
1513
1514     // Decrease funcExeInst by one as the normal commit will handle
1515     // incrementing it.
1516     --(this->thread[tid]->funcExeInst);
1517
1518     // Clear Non-Speculative Block Variable
1519     nonSpecInstActive[tid] = false;
1520 }
1521 #endif
1522
1523 TheISA::TLB*
1524 InOrderCPU::getITBPtr()
1525 {
1526     CacheUnit *itb_res =
1527         dynamic_cast<CacheUnit*>(resPool->getResource(fetchPortIdx));
1528     return itb_res->tlb();
1529 }
1530
1531
1532 TheISA::TLB*
1533 InOrderCPU::getDTBPtr()
1534 {
1535     CacheUnit *dtb_res =
1536         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1537     return dtb_res->tlb();
1538 }
1539
1540 Fault
1541 InOrderCPU::read(DynInstPtr inst, Addr addr,
1542                  uint8_t *data, unsigned size, unsigned flags)
1543 {
1544     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1545     //       you want to run w/out caches?
1546     CacheUnit *cache_res =
1547         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1548
1549     return cache_res->read(inst, addr, data, size, flags);
1550 }
1551
1552 Fault
1553 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1554                   Addr addr, unsigned flags, uint64_t *write_res)
1555 {
1556     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1557     //       you want to run w/out caches?
1558     CacheUnit *cache_res =
1559         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1560     return cache_res->write(inst, data, size, addr, flags, write_res);
1561 }