src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <algorithm>
  33
  34 #include "arch/utility.hh"
  35 #include "config/full_system.hh"
  36 #include "config/the_isa.hh"
  37 #include "cpu/activity.hh"
  38 #include "cpu/base.hh"
  39 #include "cpu/exetrace.hh"
  40 #include "cpu/inorder/cpu.hh"
  41 #include "cpu/inorder/first_stage.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource_pool.hh"
  45 #include "cpu/inorder/resources/resource_list.hh"
  46 #include "cpu/inorder/thread_context.hh"
  47 #include "cpu/inorder/thread_state.hh"
  48 #include "cpu/simple_thread.hh"
  49 #include "cpu/thread_context.hh"
  50 #include "mem/translating_port.hh"
  51 #include "params/InOrderCPU.hh"
  52 #include "sim/process.hh"
  53 #include "sim/stat_control.hh"
  54
  55 #if FULL_SYSTEM
  56 #include "cpu/quiesce_event.hh"
  57 #include "sim/system.hh"
  58 #endif
  59
  60 #if THE_ISA == ALPHA_ISA
  61 #include "arch/alpha/osfpal.hh"
  62 #endif
  63
  64 using namespace std;
  65 using namespace TheISA;
  66 using namespace ThePipeline;
  67
  68 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
  69   : Event(CPU_Tick_Pri), cpu(c)
  70 { }
  71
  72
  73 void
  74 InOrderCPU::TickEvent::process()
  75 {
  76     cpu->tick();
  77 }
  78
  79
  80 const char *
  81 InOrderCPU::TickEvent::description()
  82 {
  83     return "InOrderCPU tick event";
  84 }
  85
  86 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
  87                                Fault fault, ThreadID _tid, DynInstPtr inst,
  88                                unsigned event_pri_offset)
  89     : Event(Event::Priority((unsigned int)CPU_Tick_Pri + event_pri_offset)),
  90       cpu(_cpu)
  91 {
  92     setEvent(e_type, fault, _tid, inst);
  93 }
  94
  95
  96 std::string InOrderCPU::eventNames[NumCPUEvents] =
  97 {
  98     "ActivateThread",
  99     "ActivateNextReadyThread",
 100     "DeactivateThread",
 101     "HaltThread",
 102     "SuspendThread",
 103     "Trap",
 104     "InstGraduated",
 105     "SquashFromMemStall",
 106     "UpdatePCs"
 107 };
 108
 109 void
 110 InOrderCPU::CPUEvent::process()
 111 {
 112     switch (cpuEventType)
 113     {
 114       case ActivateThread:
 115         cpu->activateThread(tid);
 116         break;
 117
 118       case ActivateNextReadyThread:
 119         cpu->activateNextReadyThread();
 120         break;
 121
 122       case DeactivateThread:
 123         cpu->deactivateThread(tid);
 124         break;
 125
 126       case HaltThread:
 127         cpu->haltThread(tid);
 128         break;
 129
 130       case SuspendThread:
 131         cpu->suspendThread(tid);
 132         break;
 133
 134       case SquashFromMemStall:
 135         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 136         break;
 137
 138       case Trap:
 139         cpu->trapCPU(fault, tid, inst);
 140         break;
 141
 142       default:
 143         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 144     }
 145
 146     cpu->cpuEventRemoveList.push(this);
 147 }
 148
 149
 150
 151 const char *
 152 InOrderCPU::CPUEvent::description()
 153 {
 154     return "InOrderCPU event";
 155 }
 156
 157 void
 158 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 159 {
 160     assert(!scheduled() || squashed());
 161     cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
 162 }
 163
 164 void
 165 InOrderCPU::CPUEvent::unscheduleEvent()
 166 {
 167     if (scheduled())
 168         squash();
 169 }
 170
 171 InOrderCPU::InOrderCPU(Params *params)
 172     : BaseCPU(params),
 173       cpu_id(params->cpu_id),
 174       coreType("default"),
 175       _status(Idle),
 176       tickEvent(this),
 177       stageWidth(params->stageWidth),
 178       timeBuffer(2 , 2),
 179       removeInstsThisCycle(false),
 180       activityRec(params->name, NumStages, 10, params->activity),
 181 #if FULL_SYSTEM
 182       system(params->system),
 183       physmem(system->physmem),
 184 #endif // FULL_SYSTEM
 185 #ifdef DEBUG
 186       cpuEventNum(0),
 187       resReqCount(0),
 188 #endif // DEBUG
 189       switchCount(0),
 190       deferRegistration(false/*params->deferRegistration*/),
 191       stageTracing(params->stageTracing),
 192       instsPerSwitch(0)
 193 {
 194     ThreadID active_threads;
 195     cpu_params = params;
 196
 197     resPool = new ResourcePool(this, params);
 198
 199     // Resize for Multithreading CPUs
 200     thread.resize(numThreads);
 201
 202 #if FULL_SYSTEM
 203     active_threads = 1;
 204 #else
 205     active_threads = params->workload.size();
 206
 207     if (active_threads > MaxThreads) {
 208         panic("Workload Size too large. Increase the 'MaxThreads'"
 209               "in your InOrder implementation or "
 210               "edit your workload size.");
 211     }
 212
 213
 214     if (active_threads > 1) {
 215         threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 216
 217         if (threadModel == SMT) {
 218             DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 219         } else if (threadModel == SwitchOnCacheMiss) {
 220             DPRINTF(InOrderCPU, "Setting Thread Model to "
 221                     "Switch On Cache Miss\n");
 222         }
 223
 224     } else {
 225         threadModel = Single;
 226     }
 227
 228
 229
 230 #endif
 231
 232     // Bind the fetch & data ports from the resource pool.
 233     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
 234     if (fetchPortIdx == 0) {
 235         fatal("Unable to find port to fetch instructions from.\n");
 236     }
 237
 238     dataPortIdx = resPool->getPortIdx(params->dataMemPort);
 239     if (dataPortIdx == 0) {
 240         fatal("Unable to find port for data.\n");
 241     }
 242
 243     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 244 #if FULL_SYSTEM
 245         // SMT is not supported in FS mode yet.
 246         assert(numThreads == 1);
 247         thread[tid] = new Thread(this, 0);
 248 #else
 249         if (tid < (ThreadID)params->workload.size()) {
 250             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 251                     tid, params->workload[tid]->prog_fname);
 252             thread[tid] =
 253                 new Thread(this, tid, params->workload[tid]);
 254         } else {
 255             //Allocate Empty thread so M5 can use later
 256             //when scheduling threads to CPU
 257             Process* dummy_proc = params->workload[0];
 258             thread[tid] = new Thread(this, tid, dummy_proc);
 259         }
 260
 261         // Eventually set this with parameters...
 262         asid[tid] = tid;
 263 #endif
 264
 265         // Setup the TC that will serve as the interface to the threads/CPU.
 266         InOrderThreadContext *tc = new InOrderThreadContext;
 267         tc->cpu = this;
 268         tc->thread = thread[tid];
 269
 270         // Give the thread the TC.
 271         thread[tid]->tc = tc;
 272         thread[tid]->setFuncExeInst(0);
 273         globalSeqNum[tid] = 1;
 274
 275         // Add the TC to the CPU's list of TC's.
 276         this->threadContexts.push_back(tc);
 277     }
 278
 279     // Initialize TimeBuffer Stage Queues
 280     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 281         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 282         stageQueue[stNum]->id(stNum);
 283     }
 284
 285
 286     // Set Up Pipeline Stages
 287     for (int stNum=0; stNum < NumStages; stNum++) {
 288         if (stNum == 0)
 289             pipelineStage[stNum] = new FirstStage(params, stNum);
 290         else
 291             pipelineStage[stNum] = new PipelineStage(params, stNum);
 292
 293         pipelineStage[stNum]->setCPU(this);
 294         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 295         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 296
 297         // Take Care of 1st/Nth stages
 298         if (stNum > 0)
 299             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 300         if (stNum < NumStages - 1)
 301             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 302     }
 303
 304     // Initialize thread specific variables
 305     for (ThreadID tid = 0; tid < numThreads; tid++) {
 306         archRegDepMap[tid].setCPU(this);
 307
 308         nonSpecInstActive[tid] = false;
 309         nonSpecSeqNum[tid] = 0;
 310
 311         squashSeqNum[tid] = MaxAddr;
 312         lastSquashCycle[tid] = 0;
 313
 314         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 315         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 316         isa[tid].clear();
 317
 318         isa[tid].expandForMultithreading(numThreads, 1/*numVirtProcs*/);
 319
 320         // Define dummy instructions and resource requests to be used.
 321         dummyInst[tid] = new InOrderDynInst(this,
 322                                             thread[tid],
 323                                             0,
 324                                             tid,
 325                                             asid[tid]);
 326
 327         dummyReq[tid] = new ResourceRequest(resPool->getResource(0),
 328                                             dummyInst[tid],
 329                                             0,
 330                                             0,
 331                                             0,
 332                                             0);
 333     }
 334
 335     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 336     dummyReqInst->setSquashed();
 337     dummyReqInst->resetInstCount();
 338
 339     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 340     dummyBufferInst->setSquashed();
 341     dummyBufferInst->resetInstCount();
 342
 343     endOfSkedIt = skedCache.end();
 344     frontEndSked = createFrontEndSked();
 345
 346     lastRunningCycle = curTick();
 347
 348     // Reset CPU to reset state.
 349 #if FULL_SYSTEM
 350     Fault resetFault = new ResetFault();
 351     resetFault->invoke(tcBase());
 352 #else
 353     reset();
 354 #endif
 355
 356
 357     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 358     scheduleTickEvent(0);
 359 }
 360
 361 InOrderCPU::~InOrderCPU()
 362 {
 363     delete resPool;
 364 }
 365
 366 std::map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
 367
 368 RSkedPtr
 369 InOrderCPU::createFrontEndSked()
 370 {
 371     RSkedPtr res_sked = new ResourceSked();
 372     int stage_num = 0;
 373     StageScheduler F(res_sked, stage_num++);
 374     StageScheduler D(res_sked, stage_num++);
 375
 376     // FETCH
 377     F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
 378     F.needs(ICache, FetchUnit::InitiateFetch);
 379
 380     // DECODE
 381     D.needs(ICache, FetchUnit::CompleteFetch);
 382     D.needs(Decode, DecodeUnit::DecodeInst);
 383     D.needs(BPred, BranchPredictor::PredictBranch);
 384     D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
 385
 386
 387     DPRINTF(SkedCache, "Resource Sked created for instruction \"front_end\"\n");
 388
 389     return res_sked;
 390 }
 391
 392 RSkedPtr
 393 InOrderCPU::createBackEndSked(DynInstPtr inst)
 394 {
 395     RSkedPtr res_sked = lookupSked(inst);
 396     if (res_sked != NULL) {
 397         DPRINTF(SkedCache, "Found %s in sked cache.\n",
 398                 inst->instName());
 399         return res_sked;
 400     } else {
 401         res_sked = new ResourceSked();
 402     }
 403
 404     int stage_num = ThePipeline::BackEndStartStage;
 405     StageScheduler X(res_sked, stage_num++);
 406     StageScheduler M(res_sked, stage_num++);
 407     StageScheduler W(res_sked, stage_num++);
 408
 409     if (!inst->staticInst) {
 410         warn_once("Static Instruction Object Not Set. Can't Create"
 411                   " Back End Schedule");
 412         return NULL;
 413     }
 414
 415     // EXECUTE
 416     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 417         if (!idx || !inst->isStore()) {
 418             X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
 419         }
 420     }
 421
 422     if ( inst->isNonSpeculative() ) {
 423         // skip execution of non speculative insts until later
 424     } else if ( inst->isMemRef() ) {
 425         if ( inst->isLoad() ) {
 426             X.needs(AGEN, AGENUnit::GenerateAddr);
 427         }
 428     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 429         X.needs(MDU, MultDivUnit::StartMultDiv);
 430     } else {
 431         X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 432     }
 433
 434     if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 435         X.needs(MDU, MultDivUnit::EndMultDiv);
 436     }
 437
 438     // MEMORY
 439     if ( inst->isLoad() ) {
 440         M.needs(DCache, CacheUnit::InitiateReadData);
 441     } else if ( inst->isStore() ) {
 442         if ( inst->numSrcRegs() >= 2 ) {
 443             M.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 444         }
 445         M.needs(AGEN, AGENUnit::GenerateAddr);
 446         M.needs(DCache, CacheUnit::InitiateWriteData);
 447     }
 448
 449
 450     // WRITEBACK
 451     if ( inst->isLoad() ) {
 452         W.needs(DCache, CacheUnit::CompleteReadData);
 453     } else if ( inst->isStore() ) {
 454         W.needs(DCache, CacheUnit::CompleteWriteData);
 455     }
 456
 457     if ( inst->isNonSpeculative() ) {
 458         if ( inst->isMemRef() ) fatal("Non-Speculative Memory Instruction");
 459         W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 460     }
 461
 462     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 463         W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
 464     }
 465
 466     W.needs(Grad, GraduationUnit::GraduateInst);
 467
 468     // Insert Front Schedule into our cache of
 469     // resource schedules
 470     addToSkedCache(inst, res_sked);
 471
 472     DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
 473             inst->instName(), inst->getMachInst());
 474     res_sked->print();
 475
 476     return res_sked;
 477 }
 478
 479 void
 480 InOrderCPU::regStats()
 481 {
 482     /* Register the Resource Pool's stats here.*/
 483     resPool->regStats();
 484
 485     /* Register for each Pipeline Stage */
 486     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 487         pipelineStage[stage_num]->regStats();
 488     }
 489
 490     /* Register any of the InOrderCPU's stats here.*/
 491     instsPerCtxtSwitch
 492         .name(name() + ".instsPerContextSwitch")
 493         .desc("Instructions Committed Per Context Switch")
 494         .prereq(instsPerCtxtSwitch);
 495
 496     numCtxtSwitches
 497         .name(name() + ".contextSwitches")
 498         .desc("Number of context switches");
 499
 500     comLoads
 501         .name(name() + ".comLoads")
 502         .desc("Number of Load instructions committed");
 503
 504     comStores
 505         .name(name() + ".comStores")
 506         .desc("Number of Store instructions committed");
 507
 508     comBranches
 509         .name(name() + ".comBranches")
 510         .desc("Number of Branches instructions committed");
 511
 512     comNops
 513         .name(name() + ".comNops")
 514         .desc("Number of Nop instructions committed");
 515
 516     comNonSpec
 517         .name(name() + ".comNonSpec")
 518         .desc("Number of Non-Speculative instructions committed");
 519
 520     comInts
 521         .name(name() + ".comInts")
 522         .desc("Number of Integer instructions committed");
 523
 524     comFloats
 525         .name(name() + ".comFloats")
 526         .desc("Number of Floating Point instructions committed");
 527
 528     timesIdled
 529         .name(name() + ".timesIdled")
 530         .desc("Number of times that the entire CPU went into an idle state and"
 531               " unscheduled itself")
 532         .prereq(timesIdled);
 533
 534     idleCycles
 535         .name(name() + ".idleCycles")
 536         .desc("Number of cycles cpu's stages were not processed");
 537
 538     runCycles
 539         .name(name() + ".runCycles")
 540         .desc("Number of cycles cpu stages are processed.");
 541
 542     activity
 543         .name(name() + ".activity")
 544         .desc("Percentage of cycles cpu is active")
 545         .precision(6);
 546     activity = (runCycles / numCycles) * 100;
 547
 548     threadCycles
 549         .init(numThreads)
 550         .name(name() + ".threadCycles")
 551         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 552
 553     smtCycles
 554         .name(name() + ".smtCycles")
 555         .desc("Total number of cycles that the CPU was in SMT-mode");
 556
 557     committedInsts
 558         .init(numThreads)
 559         .name(name() + ".committedInsts")
 560         .desc("Number of Instructions Simulated (Per-Thread)");
 561
 562     smtCommittedInsts
 563         .init(numThreads)
 564         .name(name() + ".smtCommittedInsts")
 565         .desc("Number of SMT Instructions Simulated (Per-Thread)");
 566
 567     totalCommittedInsts
 568         .name(name() + ".committedInsts_total")
 569         .desc("Number of Instructions Simulated (Total)");
 570
 571     cpi
 572         .name(name() + ".cpi")
 573         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 574         .precision(6);
 575     cpi = numCycles / committedInsts;
 576
 577     smtCpi
 578         .name(name() + ".smt_cpi")
 579         .desc("CPI: Total SMT-CPI")
 580         .precision(6);
 581     smtCpi = smtCycles / smtCommittedInsts;
 582
 583     totalCpi
 584         .name(name() + ".cpi_total")
 585         .desc("CPI: Total CPI of All Threads")
 586         .precision(6);
 587     totalCpi = numCycles / totalCommittedInsts;
 588
 589     ipc
 590         .name(name() + ".ipc")
 591         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 592         .precision(6);
 593     ipc =  committedInsts / numCycles;
 594
 595     smtIpc
 596         .name(name() + ".smt_ipc")
 597         .desc("IPC: Total SMT-IPC")
 598         .precision(6);
 599     smtIpc = smtCommittedInsts / smtCycles;
 600
 601     totalIpc
 602         .name(name() + ".ipc_total")
 603         .desc("IPC: Total IPC of All Threads")
 604         .precision(6);
 605         totalIpc =  totalCommittedInsts / numCycles;
 606
 607     BaseCPU::regStats();
 608 }
 609
 610
 611 void
 612 InOrderCPU::tick()
 613 {
 614     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 615
 616     ++numCycles;
 617
 618     bool pipes_idle = true;
 619
 620     //Tick each of the stages
 621     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 622         pipelineStage[stNum]->tick();
 623
 624         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 625     }
 626
 627     if (pipes_idle)
 628         idleCycles++;
 629     else
 630         runCycles++;
 631
 632     // Now advance the time buffers one tick
 633     timeBuffer.advance();
 634     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 635         stageQueue[sqNum]->advance();
 636     }
 637     activityRec.advance();
 638
 639     // Any squashed requests, events, or insts then remove them now
 640     cleanUpRemovedReqs();
 641     cleanUpRemovedEvents();
 642     cleanUpRemovedInsts();
 643
 644     // Re-schedule CPU for this cycle
 645     if (!tickEvent.scheduled()) {
 646         if (_status == SwitchedOut) {
 647             // increment stat
 648             lastRunningCycle = curTick();
 649         } else if (!activityRec.active()) {
 650             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 651             lastRunningCycle = curTick();
 652             timesIdled++;
 653         } else {
 654             //Tick next_tick = curTick() + cycles(1);
 655             //tickEvent.schedule(next_tick);
 656             schedule(&tickEvent, nextCycle(curTick() + 1));
 657             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 658                     nextCycle(curTick() + 1));
 659         }
 660     }
 661
 662     tickThreadStats();
 663     updateThreadPriority();
 664 }
 665
 666
 667 void
 668 InOrderCPU::init()
 669 {
 670     if (!deferRegistration) {
 671         registerThreadContexts();
 672     }
 673
 674     // Set inSyscall so that the CPU doesn't squash when initially
 675     // setting up registers.
 676     for (ThreadID tid = 0; tid < numThreads; ++tid)
 677         thread[tid]->inSyscall = true;
 678
 679 #if FULL_SYSTEM
 680     for (ThreadID tid = 0; tid < numThreads; tid++) {
 681         ThreadContext *src_tc = threadContexts[tid];
 682         TheISA::initCPU(src_tc, src_tc->contextId());
 683     }
 684 #endif
 685
 686     // Clear inSyscall.
 687     for (ThreadID tid = 0; tid < numThreads; ++tid)
 688         thread[tid]->inSyscall = false;
 689
 690     // Call Initializiation Routine for Resource Pool
 691     resPool->init();
 692 }
 693
 694 void
 695 InOrderCPU::reset()
 696 {
 697     for (int i = 0; i < numThreads; i++) {
 698         isa[i].reset(coreType, numThreads,
 699                      1/*numVirtProcs*/, dynamic_cast<BaseCPU*>(this));
 700     }
 701 }
 702
 703 Port*
 704 InOrderCPU::getPort(const std::string &if_name, int idx)
 705 {
 706     return resPool->getPort(if_name, idx);
 707 }
 708
 709 #if FULL_SYSTEM
 710 Fault
 711 InOrderCPU::hwrei(ThreadID tid)
 712 {
 713     panic("hwrei: Unimplemented");
 714
 715     return NoFault;
 716 }
 717
 718
 719 bool
 720 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 721 {
 722     panic("simPalCheck: Unimplemented");
 723
 724     return true;
 725 }
 726
 727
 728 Fault
 729 InOrderCPU::getInterrupts()
 730 {
 731     // Check if there are any outstanding interrupts
 732     return interrupts->getInterrupt(threadContexts[0]);
 733 }
 734
 735
 736 void
 737 InOrderCPU::processInterrupts(Fault interrupt)
 738 {
 739     // Check for interrupts here.  For now can copy the code that
 740     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 741     // is the one that handles the interrupts.
 742     // @todo: Possibly consolidate the interrupt checking code.
 743     // @todo: Allow other threads to handle interrupts.
 744
 745     assert(interrupt != NoFault);
 746     interrupts->updateIntrInfo(threadContexts[0]);
 747
 748     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 749
 750     // Note: Context ID ok here? Impl. of FS mode needs to revisit this
 751     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 752 }
 753
 754
 755 void
 756 InOrderCPU::updateMemPorts()
 757 {
 758     // Update all ThreadContext's memory ports (Functional/Virtual
 759     // Ports)
 760     ThreadID size = thread.size();
 761     for (ThreadID i = 0; i < size; ++i)
 762         thread[i]->connectMemPorts(thread[i]->getTC());
 763 }
 764 #endif
 765
 766 void
 767 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 768 {
 769     //@ Squash Pipeline during TRAP
 770     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 771 }
 772
 773 void
 774 InOrderCPU::trapCPU(Fault fault, ThreadID tid, DynInstPtr inst)
 775 {
 776     fault->invoke(tcBase(tid), inst->staticInst);
 777 }
 778
 779 void
 780 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 781 {
 782     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 783 }
 784
 785
 786 void
 787 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 788                                 ThreadID tid)
 789 {
 790     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 791
 792     // Squash all instructions in each stage including
 793     // instruction that caused the squash (seq_num - 1)
 794     // NOTE: The stage bandwidth needs to be cleared so thats why
 795     //       the stalling instruction is squashed as well. The stalled
 796     //       instruction is previously placed in another intermediate buffer
 797     //       while it's stall is being handled.
 798     InstSeqNum squash_seq_num = seq_num - 1;
 799
 800     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 801         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 802     }
 803 }
 804
 805 void
 806 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 807                              ThreadID tid, DynInstPtr inst,
 808                              unsigned delay, unsigned event_pri_offset)
 809 {
 810     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 811                                        event_pri_offset);
 812
 813     Tick sked_tick = nextCycle(curTick() + ticks(delay));
 814     if (delay >= 0) {
 815         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 816                 eventNames[c_event], curTick() + delay, tid);
 817         schedule(cpu_event, sked_tick);
 818     } else {
 819         cpu_event->process();
 820         cpuEventRemoveList.push(cpu_event);
 821     }
 822
 823     // Broadcast event to the Resource Pool
 824     // Need to reset tid just in case this is a dummy instruction
 825     inst->setTid(tid);
 826     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 827 }
 828
 829 bool
 830 InOrderCPU::isThreadActive(ThreadID tid)
 831 {
 832   list<ThreadID>::iterator isActive =
 833       std::find(activeThreads.begin(), activeThreads.end(), tid);
 834
 835     return (isActive != activeThreads.end());
 836 }
 837
 838 bool
 839 InOrderCPU::isThreadReady(ThreadID tid)
 840 {
 841   list<ThreadID>::iterator isReady =
 842       std::find(readyThreads.begin(), readyThreads.end(), tid);
 843
 844     return (isReady != readyThreads.end());
 845 }
 846
 847 bool
 848 InOrderCPU::isThreadSuspended(ThreadID tid)
 849 {
 850   list<ThreadID>::iterator isSuspended =
 851       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
 852
 853     return (isSuspended != suspendedThreads.end());
 854 }
 855
 856 void
 857 InOrderCPU::activateNextReadyThread()
 858 {
 859     if (readyThreads.size() >= 1) {
 860         ThreadID ready_tid = readyThreads.front();
 861
 862         // Activate in Pipeline
 863         activateThread(ready_tid);
 864
 865         // Activate in Resource Pool
 866         resPool->activateAll(ready_tid);
 867
 868         list<ThreadID>::iterator ready_it =
 869             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
 870         readyThreads.erase(ready_it);
 871     } else {
 872         DPRINTF(InOrderCPU,
 873                 "Attempting to activate new thread, but No Ready Threads to"
 874                 "activate.\n");
 875         DPRINTF(InOrderCPU,
 876                 "Unable to switch to next active thread.\n");
 877     }
 878 }
 879
 880 void
 881 InOrderCPU::activateThread(ThreadID tid)
 882 {
 883     if (isThreadSuspended(tid)) {
 884         DPRINTF(InOrderCPU,
 885                 "Removing [tid:%i] from suspended threads list.\n", tid);
 886
 887         list<ThreadID>::iterator susp_it =
 888             std::find(suspendedThreads.begin(), suspendedThreads.end(),
 889                       tid);
 890         suspendedThreads.erase(susp_it);
 891     }
 892
 893     if (threadModel == SwitchOnCacheMiss &&
 894         numActiveThreads() == 1) {
 895         DPRINTF(InOrderCPU,
 896                 "Ignoring activation of [tid:%i], since [tid:%i] is "
 897                 "already running.\n", tid, activeThreadId());
 898
 899         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
 900                 tid);
 901
 902         readyThreads.push_back(tid);
 903
 904     } else if (!isThreadActive(tid)) {
 905         DPRINTF(InOrderCPU,
 906                 "Adding [tid:%i] to active threads list.\n", tid);
 907         activeThreads.push_back(tid);
 908
 909         activateThreadInPipeline(tid);
 910
 911         thread[tid]->lastActivate = curTick();
 912
 913         tcBase(tid)->setStatus(ThreadContext::Active);
 914
 915         wakeCPU();
 916
 917         numCtxtSwitches++;
 918     }
 919 }
 920
 921 void
 922 InOrderCPU::activateThreadInPipeline(ThreadID tid)
 923 {
 924     for (int stNum=0; stNum < NumStages; stNum++) {
 925         pipelineStage[stNum]->activateThread(tid);
 926     }
 927 }
 928
 929 void
 930 InOrderCPU::deactivateContext(ThreadID tid, int delay)
 931 {
 932     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
 933
 934     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
 935
 936     // Be sure to signal that there's some activity so the CPU doesn't
 937     // deschedule itself.
 938     activityRec.activity();
 939
 940     _status = Running;
 941 }
 942
 943 void
 944 InOrderCPU::deactivateThread(ThreadID tid)
 945 {
 946     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
 947
 948     if (isThreadActive(tid)) {
 949         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
 950                 tid);
 951         list<ThreadID>::iterator thread_it =
 952             std::find(activeThreads.begin(), activeThreads.end(), tid);
 953
 954         removePipelineStalls(*thread_it);
 955
 956         activeThreads.erase(thread_it);
 957
 958         // Ideally, this should be triggered from the
 959         // suspendContext/Thread functions
 960         tcBase(tid)->setStatus(ThreadContext::Suspended);
 961     }
 962
 963     assert(!isThreadActive(tid));
 964 }
 965
 966 void
 967 InOrderCPU::removePipelineStalls(ThreadID tid)
 968 {
 969     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
 970             tid);
 971
 972     for (int stNum = 0; stNum < NumStages ; stNum++) {
 973         pipelineStage[stNum]->removeStalls(tid);
 974     }
 975
 976 }
 977
 978 void
 979 InOrderCPU::updateThreadPriority()
 980 {
 981     if (activeThreads.size() > 1)
 982     {
 983         //DEFAULT TO ROUND ROBIN SCHEME
 984         //e.g. Move highest priority to end of thread list
 985         list<ThreadID>::iterator list_begin = activeThreads.begin();
 986         list<ThreadID>::iterator list_end   = activeThreads.end();
 987
 988         unsigned high_thread = *list_begin;
 989
 990         activeThreads.erase(list_begin);
 991
 992         activeThreads.push_back(high_thread);
 993     }
 994 }
 995
 996 inline void
 997 InOrderCPU::tickThreadStats()
 998 {
 999     /** Keep track of cycles that each thread is active */
1000     list<ThreadID>::iterator thread_it = activeThreads.begin();
1001     while (thread_it != activeThreads.end()) {
1002         threadCycles[*thread_it]++;
1003         thread_it++;
1004     }
1005
1006     // Keep track of cycles where SMT is active
1007     if (activeThreads.size() > 1) {
1008         smtCycles++;
1009     }
1010 }
1011
1012 void
1013 InOrderCPU::activateContext(ThreadID tid, int delay)
1014 {
1015     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
1016
1017
1018     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
1019
1020     // Be sure to signal that there's some activity so the CPU doesn't
1021     // deschedule itself.
1022     activityRec.activity();
1023
1024     _status = Running;
1025 }
1026
1027 void
1028 InOrderCPU::activateNextReadyContext(int delay)
1029 {
1030     DPRINTF(InOrderCPU,"Activating next ready thread\n");
1031
1032     // NOTE: Add 5 to the event priority so that we always activate
1033     // threads after we've finished deactivating, squashing,etc.
1034     // other threads
1035     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
1036                      delay, 5);
1037
1038     // Be sure to signal that there's some activity so the CPU doesn't
1039     // deschedule itself.
1040     activityRec.activity();
1041
1042     _status = Running;
1043 }
1044
1045 void
1046 InOrderCPU::haltContext(ThreadID tid, int delay)
1047 {
1048     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
1049
1050     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
1051
1052     activityRec.activity();
1053 }
1054
1055 void
1056 InOrderCPU::haltThread(ThreadID tid)
1057 {
1058     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
1059     deactivateThread(tid);
1060     squashThreadInPipeline(tid);
1061     haltedThreads.push_back(tid);
1062
1063     tcBase(tid)->setStatus(ThreadContext::Halted);
1064
1065     if (threadModel == SwitchOnCacheMiss) {
1066         activateNextReadyContext();
1067     }
1068 }
1069
1070 void
1071 InOrderCPU::suspendContext(ThreadID tid, int delay)
1072 {
1073     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
1074 }
1075
1076 void
1077 InOrderCPU::suspendThread(ThreadID tid)
1078 {
1079     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
1080             tid);
1081     deactivateThread(tid);
1082     suspendedThreads.push_back(tid);
1083     thread[tid]->lastSuspend = curTick();
1084
1085     tcBase(tid)->setStatus(ThreadContext::Suspended);
1086 }
1087
1088 void
1089 InOrderCPU::squashThreadInPipeline(ThreadID tid)
1090 {
1091     //Squash all instructions in each stage
1092     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
1093         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
1094     }
1095 }
1096
1097 PipelineStage*
1098 InOrderCPU::getPipeStage(int stage_num)
1099 {
1100     return pipelineStage[stage_num];
1101 }
1102
1103 uint64_t
1104 InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
1105 {
1106     return intRegs[tid][reg_idx];
1107 }
1108
1109 FloatReg
1110 InOrderCPU::readFloatReg(int reg_idx, ThreadID tid)
1111 {
1112     return floatRegs.f[tid][reg_idx];
1113 }
1114
1115 FloatRegBits
1116 InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
1117 {;
1118     return floatRegs.i[tid][reg_idx];
1119 }
1120
1121 void
1122 InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
1123 {
1124     intRegs[tid][reg_idx] = val;
1125 }
1126
1127
1128 void
1129 InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid)
1130 {
1131     floatRegs.f[tid][reg_idx] = val;
1132 }
1133
1134
1135 void
1136 InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid)
1137 {
1138     floatRegs.i[tid][reg_idx] = val;
1139 }
1140
1141 uint64_t
1142 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1143 {
1144     // If Default value is set, then retrieve target thread
1145     if (tid == InvalidThreadID) {
1146         tid = TheISA::getTargetThread(tcBase(tid));
1147     }
1148
1149     if (reg_idx < FP_Base_DepTag) {
1150         // Integer Register File
1151         return readIntReg(reg_idx, tid);
1152     } else if (reg_idx < Ctrl_Base_DepTag) {
1153         // Float Register File
1154         reg_idx -= FP_Base_DepTag;
1155         return readFloatRegBits(reg_idx, tid);
1156     } else {
1157         reg_idx -= Ctrl_Base_DepTag;
1158         return readMiscReg(reg_idx, tid);  // Misc. Register File
1159     }
1160 }
1161 void
1162 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1163                               ThreadID tid)
1164 {
1165     // If Default value is set, then retrieve target thread
1166     if (tid == InvalidThreadID) {
1167         tid = TheISA::getTargetThread(tcBase(tid));
1168     }
1169
1170     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1171         setIntReg(reg_idx, val, tid);
1172     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1173         reg_idx -= FP_Base_DepTag;
1174         setFloatRegBits(reg_idx, val, tid);
1175     } else {
1176         reg_idx -= Ctrl_Base_DepTag;
1177         setMiscReg(reg_idx, val, tid); // Misc. Register File
1178     }
1179 }
1180
1181 MiscReg
1182 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1183 {
1184     return isa[tid].readMiscRegNoEffect(misc_reg);
1185 }
1186
1187 MiscReg
1188 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1189 {
1190     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1191 }
1192
1193 void
1194 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1195 {
1196     isa[tid].setMiscRegNoEffect(misc_reg, val);
1197 }
1198
1199 void
1200 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1201 {
1202     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1203 }
1204
1205
1206 InOrderCPU::ListIt
1207 InOrderCPU::addInst(DynInstPtr &inst)
1208 {
1209     ThreadID tid = inst->readTid();
1210
1211     instList[tid].push_back(inst);
1212
1213     return --(instList[tid].end());
1214 }
1215
1216 void
1217 InOrderCPU::updateContextSwitchStats()
1218 {
1219     // Set Average Stat Here, then reset to 0
1220     instsPerCtxtSwitch = instsPerSwitch;
1221     instsPerSwitch = 0;
1222 }
1223
1224
1225 void
1226 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1227 {
1228     // Set the CPU's PCs - This contributes to the precise state of the CPU
1229     // which can be used when restoring a thread to the CPU after after any
1230     // type of context switching activity (fork, exception, etc.)
1231     pcState(inst->pcState(), tid);
1232
1233     if (inst->isControl()) {
1234         thread[tid]->lastGradIsBranch = true;
1235         thread[tid]->lastBranchPC = inst->pcState();
1236         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1237     } else {
1238         thread[tid]->lastGradIsBranch = false;
1239     }
1240
1241
1242     // Finalize Trace Data For Instruction
1243     if (inst->traceData) {
1244         //inst->traceData->setCycle(curTick());
1245         inst->traceData->setFetchSeq(inst->seqNum);
1246         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1247         inst->traceData->dump();
1248         delete inst->traceData;
1249         inst->traceData = NULL;
1250     }
1251
1252     // Increment active thread's instruction count
1253     instsPerSwitch++;
1254
1255     // Increment thread-state's instruction count
1256     thread[tid]->numInst++;
1257
1258     // Increment thread-state's instruction stats
1259     thread[tid]->numInsts++;
1260
1261     // Count committed insts per thread stats
1262     committedInsts[tid]++;
1263
1264     // Count total insts committed stat
1265     totalCommittedInsts++;
1266
1267     // Count SMT-committed insts per thread stat
1268     if (numActiveThreads() > 1) {
1269         smtCommittedInsts[tid]++;
1270     }
1271
1272     // Instruction-Mix Stats
1273     if (inst->isLoad()) {
1274         comLoads++;
1275     } else if (inst->isStore()) {
1276         comStores++;
1277     } else if (inst->isControl()) {
1278         comBranches++;
1279     } else if (inst->isNop()) {
1280         comNops++;
1281     } else if (inst->isNonSpeculative()) {
1282         comNonSpec++;
1283     } else if (inst->isInteger()) {
1284         comInts++;
1285     } else if (inst->isFloating()) {
1286         comFloats++;
1287     }
1288
1289     // Check for instruction-count-based events.
1290     comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1291
1292     // Broadcast to other resources an instruction
1293     // has been completed
1294     resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
1295                            0, 0, tid);
1296
1297     // Finally, remove instruction from CPU
1298     removeInst(inst);
1299 }
1300
1301 // currently unused function, but substitute repetitive code w/this function
1302 // call
1303 void
1304 InOrderCPU::addToRemoveList(DynInstPtr &inst)
1305 {
1306     removeInstsThisCycle = true;
1307     if (!inst->isRemoveList()) {
1308         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1309                 "[sn:%lli] to remove list\n",
1310                 inst->threadNumber, inst->pcState(), inst->seqNum);
1311         inst->setRemoveList();
1312         removeList.push(inst->getInstListIt());
1313     }  else {
1314         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1315                 "[sn:%lli], already remove list\n",
1316                 inst->threadNumber, inst->pcState(), inst->seqNum);
1317     }
1318
1319 }
1320
1321 void
1322 InOrderCPU::removeInst(DynInstPtr &inst)
1323 {
1324     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1325             "[sn:%lli]\n",
1326             inst->threadNumber, inst->pcState(), inst->seqNum);
1327
1328     removeInstsThisCycle = true;
1329
1330     // Remove the instruction.
1331     if (!inst->isRemoveList()) {
1332         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1333                 "[sn:%lli] to remove list\n",
1334                 inst->threadNumber, inst->pcState(), inst->seqNum);
1335         inst->setRemoveList();
1336         removeList.push(inst->getInstListIt());
1337     } else {
1338         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1339                 "[sn:%lli], already on remove list\n",
1340                 inst->threadNumber, inst->pcState(), inst->seqNum);
1341     }
1342
1343 }
1344
1345 void
1346 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1347 {
1348     //assert(!instList[tid].empty());
1349
1350     removeInstsThisCycle = true;
1351
1352     ListIt inst_iter = instList[tid].end();
1353
1354     inst_iter--;
1355
1356     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1357             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1358             tid, seq_num, (*inst_iter)->seqNum);
1359
1360     while ((*inst_iter)->seqNum > seq_num) {
1361
1362         bool break_loop = (inst_iter == instList[tid].begin());
1363
1364         squashInstIt(inst_iter, tid);
1365
1366         inst_iter--;
1367
1368         if (break_loop)
1369             break;
1370     }
1371 }
1372
1373
1374 inline void
1375 InOrderCPU::squashInstIt(const ListIt &instIt, ThreadID tid)
1376 {
1377     if ((*instIt)->threadNumber == tid) {
1378         DPRINTF(InOrderCPU, "Squashing instruction, "
1379                 "[tid:%i] [sn:%lli] PC %s\n",
1380                 (*instIt)->threadNumber,
1381                 (*instIt)->seqNum,
1382                 (*instIt)->pcState());
1383
1384         (*instIt)->setSquashed();
1385
1386         if (!(*instIt)->isRemoveList()) {
1387             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1388                     "[sn:%lli] to remove list\n",
1389                     (*instIt)->threadNumber, (*instIt)->pcState(),
1390                     (*instIt)->seqNum);
1391             (*instIt)->setRemoveList();
1392             removeList.push(instIt);
1393         } else {
1394             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1395                     " PC %s [sn:%lli], already on remove list\n",
1396                     (*instIt)->threadNumber, (*instIt)->pcState(),
1397                     (*instIt)->seqNum);
1398         }
1399
1400     }
1401
1402 }
1403
1404
1405 void
1406 InOrderCPU::cleanUpRemovedInsts()
1407 {
1408     while (!removeList.empty()) {
1409         DPRINTF(InOrderCPU, "Removing instruction, "
1410                 "[tid:%i] [sn:%lli] PC %s\n",
1411                 (*removeList.front())->threadNumber,
1412                 (*removeList.front())->seqNum,
1413                (*removeList.front())->pcState());
1414
1415         DynInstPtr inst = *removeList.front();
1416         ThreadID tid = inst->threadNumber;
1417
1418         // Remove From Register Dependency Map, If Necessary
1419         archRegDepMap[(*removeList.front())->threadNumber].
1420             remove((*removeList.front()));
1421
1422
1423         // Clear if Non-Speculative
1424         if (inst->staticInst &&
1425             inst->seqNum == nonSpecSeqNum[tid] &&
1426             nonSpecInstActive[tid] == true) {
1427             nonSpecInstActive[tid] = false;
1428         }
1429
1430         instList[tid].erase(removeList.front());
1431
1432         removeList.pop();
1433     }
1434
1435     removeInstsThisCycle = false;
1436 }
1437
1438 void
1439 InOrderCPU::cleanUpRemovedReqs()
1440 {
1441     while (!reqRemoveList.empty()) {
1442         ResourceRequest *res_req = reqRemoveList.front();
1443
1444         DPRINTF(RefCount, "[tid:%i] [sn:%lli]: Removing Request "
1445                 "[stage_num:%i] [res:%s] [slot:%i] [completed:%i].\n",
1446                 res_req->inst->threadNumber,
1447                 res_req->inst->seqNum,
1448                 res_req->getStageNum(),
1449                 res_req->res->name(),
1450                 (res_req->isCompleted()) ?
1451                 res_req->getComplSlot() : res_req->getSlot(),
1452                 res_req->isCompleted());
1453
1454         reqRemoveList.pop();
1455
1456         delete res_req;
1457     }
1458 }
1459
1460 void
1461 InOrderCPU::cleanUpRemovedEvents()
1462 {
1463     while (!cpuEventRemoveList.empty()) {
1464         Event *cpu_event = cpuEventRemoveList.front();
1465         cpuEventRemoveList.pop();
1466         delete cpu_event;
1467     }
1468 }
1469
1470
1471 void
1472 InOrderCPU::dumpInsts()
1473 {
1474     int num = 0;
1475
1476     ListIt inst_list_it = instList[0].begin();
1477
1478     cprintf("Dumping Instruction List\n");
1479
1480     while (inst_list_it != instList[0].end()) {
1481         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1482                 "Squashed:%i\n\n",
1483                 num, (*inst_list_it)->pcState(),
1484                 (*inst_list_it)->threadNumber,
1485                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1486                 (*inst_list_it)->isSquashed());
1487         inst_list_it++;
1488         ++num;
1489     }
1490 }
1491
1492 void
1493 InOrderCPU::wakeCPU()
1494 {
1495     if (/*activityRec.active() || */tickEvent.scheduled()) {
1496         DPRINTF(Activity, "CPU already running.\n");
1497         return;
1498     }
1499
1500     DPRINTF(Activity, "Waking up CPU\n");
1501
1502     Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
1503
1504     idleCycles += extra_cycles;
1505     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1506         pipelineStage[stage_num]->idleCycles += extra_cycles;
1507     }
1508
1509     numCycles += extra_cycles;
1510
1511     schedule(&tickEvent, nextCycle(curTick()));
1512 }
1513
1514 #if FULL_SYSTEM
1515
1516 void
1517 InOrderCPU::wakeup()
1518 {
1519     if (thread[0]->status() != ThreadContext::Suspended)
1520         return;
1521
1522     wakeCPU();
1523
1524     DPRINTF(Quiesce, "Suspended Processor woken\n");
1525     threadContexts[0]->activate();
1526 }
1527 #endif
1528
1529 #if !FULL_SYSTEM
1530 void
1531 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1532 {
1533     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1534
1535     DPRINTF(Activity,"Activity: syscall() called.\n");
1536
1537     // Temporarily increase this by one to account for the syscall
1538     // instruction.
1539     ++(this->thread[tid]->funcExeInst);
1540
1541     // Execute the actual syscall.
1542     this->thread[tid]->syscall(callnum);
1543
1544     // Decrease funcExeInst by one as the normal commit will handle
1545     // incrementing it.
1546     --(this->thread[tid]->funcExeInst);
1547
1548     // Clear Non-Speculative Block Variable
1549     nonSpecInstActive[tid] = false;
1550 }
1551 #endif
1552
1553 TheISA::TLB*
1554 InOrderCPU::getITBPtr()
1555 {
1556     CacheUnit *itb_res =
1557         dynamic_cast<CacheUnit*>(resPool->getResource(fetchPortIdx));
1558     return itb_res->tlb();
1559 }
1560
1561
1562 TheISA::TLB*
1563 InOrderCPU::getDTBPtr()
1564 {
1565     CacheUnit *dtb_res =
1566         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1567     return dtb_res->tlb();
1568 }
1569
1570 Fault
1571 InOrderCPU::read(DynInstPtr inst, Addr addr,
1572                  uint8_t *data, unsigned size, unsigned flags)
1573 {
1574     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1575     //       you want to run w/out caches?
1576     CacheUnit *cache_res =
1577         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1578
1579     return cache_res->read(inst, addr, data, size, flags);
1580 }
1581
1582 Fault
1583 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1584                   Addr addr, unsigned flags, uint64_t *write_res)
1585 {
1586     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1587     //       you want to run w/out caches?
1588     CacheUnit *cache_res =
1589         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1590     return cache_res->write(inst, data, size, addr, flags, write_res);
1591 }