2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "arch/utility.hh"
35 #include "base/bigint.hh"
36 #include "config/full_system.hh"
37 #include "config/the_isa.hh"
38 #include "cpu/inorder/resources/resource_list.hh"
39 #include "cpu/inorder/cpu.hh"
40 #include "cpu/inorder/first_stage.hh"
41 #include "cpu/inorder/inorder_dyn_inst.hh"
42 #include "cpu/inorder/pipeline_traits.hh"
43 #include "cpu/inorder/resource_pool.hh"
44 #include "cpu/inorder/thread_context.hh"
45 #include "cpu/inorder/thread_state.hh"
46 #include "cpu/activity.hh"
47 #include "cpu/base.hh"
48 #include "cpu/exetrace.hh"
49 #include "cpu/simple_thread.hh"
50 #include "cpu/thread_context.hh"
51 #include "debug/Activity.hh"
52 #include "debug/InOrderCPU.hh"
53 #include "debug/RefCount.hh"
54 #include "debug/SkedCache.hh"
55 #include "debug/Quiesce.hh"
56 #include "mem/translating_port.hh"
57 #include "params/InOrderCPU.hh"
58 #include "sim/process.hh"
59 #include "sim/stat_control.hh"
62 #include "cpu/quiesce_event.hh"
63 #include "sim/system.hh"
66 #if THE_ISA == ALPHA_ISA
67 #include "arch/alpha/osfpal.hh"
71 using namespace TheISA
;
72 using namespace ThePipeline
;
74 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
75 : Event(CPU_Tick_Pri
), cpu(c
)
80 InOrderCPU::TickEvent::process()
87 InOrderCPU::TickEvent::description()
89 return "InOrderCPU tick event";
92 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
93 Fault fault
, ThreadID _tid
, DynInstPtr inst
,
94 CPUEventPri event_pri
)
95 : Event(event_pri
), cpu(_cpu
)
97 setEvent(e_type
, fault
, _tid
, inst
);
101 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
104 "ActivateNextReadyThread",
110 "SquashFromMemStall",
115 InOrderCPU::CPUEvent::process()
117 switch (cpuEventType
)
120 cpu
->activateThread(tid
);
121 cpu
->resPool
->activateThread(tid
);
124 case ActivateNextReadyThread
:
125 cpu
->activateNextReadyThread();
128 case DeactivateThread
:
129 cpu
->deactivateThread(tid
);
130 cpu
->resPool
->deactivateThread(tid
);
134 cpu
->haltThread(tid
);
135 cpu
->resPool
->deactivateThread(tid
);
139 cpu
->suspendThread(tid
);
140 cpu
->resPool
->suspendThread(tid
);
143 case SquashFromMemStall
:
144 cpu
->squashDueToMemStall(inst
->squashingStage
, inst
->seqNum
, tid
);
145 cpu
->resPool
->squashDueToMemStall(inst
, inst
->squashingStage
,
150 DPRINTF(InOrderCPU
, "Trapping CPU\n");
151 cpu
->trap(fault
, tid
, inst
);
152 cpu
->resPool
->trap(fault
, tid
, inst
);
153 cpu
->trapPending
[tid
] = false;
158 cpu
->syscall(inst
->syscallNum
, tid
);
159 cpu
->resPool
->trap(fault
, tid
, inst
);
163 fatal("Unrecognized Event Type %s", eventNames
[cpuEventType
]);
166 cpu
->cpuEventRemoveList
.push(this);
172 InOrderCPU::CPUEvent::description()
174 return "InOrderCPU event";
178 InOrderCPU::CPUEvent::scheduleEvent(int delay
)
180 assert(!scheduled() || squashed());
181 cpu
->reschedule(this, cpu
->nextCycle(curTick() + cpu
->ticks(delay
)), true);
185 InOrderCPU::CPUEvent::unscheduleEvent()
191 InOrderCPU::InOrderCPU(Params
*params
)
193 cpu_id(params
->cpu_id
),
197 stageWidth(params
->stageWidth
),
199 removeInstsThisCycle(false),
200 activityRec(params
->name
, NumStages
, 10, params
->activity
),
202 system(params
->system
),
203 #endif // FULL_SYSTEM
209 deferRegistration(false/*params->deferRegistration*/),
210 stageTracing(params
->stageTracing
),
214 ThreadID active_threads
;
217 resPool
= new ResourcePool(this, params
);
219 // Resize for Multithreading CPUs
220 thread
.resize(numThreads
);
225 active_threads
= params
->workload
.size();
227 if (active_threads
> MaxThreads
) {
228 panic("Workload Size too large. Increase the 'MaxThreads'"
229 "in your InOrder implementation or "
230 "edit your workload size.");
234 if (active_threads
> 1) {
235 threadModel
= (InOrderCPU::ThreadModel
) params
->threadModel
;
237 if (threadModel
== SMT
) {
238 DPRINTF(InOrderCPU
, "Setting Thread Model to SMT.\n");
239 } else if (threadModel
== SwitchOnCacheMiss
) {
240 DPRINTF(InOrderCPU
, "Setting Thread Model to "
241 "Switch On Cache Miss\n");
245 threadModel
= Single
;
252 // Bind the fetch & data ports from the resource pool.
253 fetchPortIdx
= resPool
->getPortIdx(params
->fetchMemPort
);
254 if (fetchPortIdx
== 0) {
255 fatal("Unable to find port to fetch instructions from.\n");
258 dataPortIdx
= resPool
->getPortIdx(params
->dataMemPort
);
259 if (dataPortIdx
== 0) {
260 fatal("Unable to find port for data.\n");
263 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
265 lastCommittedPC
[tid
].set(0);
268 // SMT is not supported in FS mode yet.
269 assert(numThreads
== 1);
270 thread
[tid
] = new Thread(this, 0);
272 if (tid
< (ThreadID
)params
->workload
.size()) {
273 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
274 tid
, params
->workload
[tid
]->prog_fname
);
276 new Thread(this, tid
, params
->workload
[tid
]);
278 //Allocate Empty thread so M5 can use later
279 //when scheduling threads to CPU
280 Process
* dummy_proc
= params
->workload
[0];
281 thread
[tid
] = new Thread(this, tid
, dummy_proc
);
284 // Eventually set this with parameters...
288 // Setup the TC that will serve as the interface to the threads/CPU.
289 InOrderThreadContext
*tc
= new InOrderThreadContext
;
291 tc
->thread
= thread
[tid
];
294 // Setup quiesce event.
295 this->thread
[tid
]->quiesceEvent
= new EndQuiesceEvent(tc
);
298 // Give the thread the TC.
299 thread
[tid
]->tc
= tc
;
300 thread
[tid
]->setFuncExeInst(0);
301 globalSeqNum
[tid
] = 1;
303 // Add the TC to the CPU's list of TC's.
304 this->threadContexts
.push_back(tc
);
307 // Initialize TimeBuffer Stage Queues
308 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
309 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
310 stageQueue
[stNum
]->id(stNum
);
314 // Set Up Pipeline Stages
315 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
317 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
319 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
321 pipelineStage
[stNum
]->setCPU(this);
322 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
323 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
325 // Take Care of 1st/Nth stages
327 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
328 if (stNum
< NumStages
- 1)
329 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
332 // Initialize thread specific variables
333 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
334 archRegDepMap
[tid
].setCPU(this);
336 nonSpecInstActive
[tid
] = false;
337 nonSpecSeqNum
[tid
] = 0;
339 squashSeqNum
[tid
] = MaxAddr
;
340 lastSquashCycle
[tid
] = 0;
342 memset(intRegs
[tid
], 0, sizeof(intRegs
[tid
]));
343 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
346 // Define dummy instructions and resource requests to be used.
347 dummyInst
[tid
] = new InOrderDynInst(this,
353 dummyReq
[tid
] = new ResourceRequest(resPool
->getResource(0));
356 // Use this dummy inst to force squashing behind every instruction
358 dummyTrapInst
[tid
] = new InOrderDynInst(this, NULL
, 0, 0, 0);
359 dummyTrapInst
[tid
]->seqNum
= 0;
360 dummyTrapInst
[tid
]->squashSeqNum
= 0;
361 dummyTrapInst
[tid
]->setTid(tid
);
364 trapPending
[tid
] = false;
368 dummyReqInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
369 dummyReqInst
->setSquashed();
370 dummyReqInst
->resetInstCount();
372 dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
373 dummyBufferInst
->setSquashed();
374 dummyBufferInst
->resetInstCount();
376 endOfSkedIt
= skedCache
.end();
377 frontEndSked
= createFrontEndSked();
378 faultSked
= createFaultSked();
380 lastRunningCycle
= curTick();
385 // Schedule First Tick Event, CPU will reschedule itself from here on out.
386 scheduleTickEvent(0);
389 InOrderCPU::~InOrderCPU()
393 SkedCacheIt sked_it
= skedCache
.begin();
394 SkedCacheIt sked_end
= skedCache
.end();
396 while (sked_it
!= sked_end
) {
397 delete (*sked_it
).second
;
403 m5::hash_map
<InOrderCPU::SkedID
, ThePipeline::RSkedPtr
> InOrderCPU::skedCache
;
406 InOrderCPU::createFrontEndSked()
408 RSkedPtr res_sked
= new ResourceSked();
410 StageScheduler
F(res_sked
, stage_num
++);
411 StageScheduler
D(res_sked
, stage_num
++);
414 F
.needs(FetchSeq
, FetchSeqUnit::AssignNextPC
);
415 F
.needs(ICache
, FetchUnit::InitiateFetch
);
418 D
.needs(ICache
, FetchUnit::CompleteFetch
);
419 D
.needs(Decode
, DecodeUnit::DecodeInst
);
420 D
.needs(BPred
, BranchPredictor::PredictBranch
);
421 D
.needs(FetchSeq
, FetchSeqUnit::UpdateTargetPC
);
424 DPRINTF(SkedCache
, "Resource Sked created for instruction Front End\n");
430 InOrderCPU::createFaultSked()
432 RSkedPtr res_sked
= new ResourceSked();
433 StageScheduler
W(res_sked
, NumStages
- 1);
434 W
.needs(Grad
, GraduationUnit::CheckFault
);
435 DPRINTF(SkedCache
, "Resource Sked created for instruction Faults\n");
440 InOrderCPU::createBackEndSked(DynInstPtr inst
)
442 RSkedPtr res_sked
= lookupSked(inst
);
443 if (res_sked
!= NULL
) {
444 DPRINTF(SkedCache
, "Found %s in sked cache.\n",
448 res_sked
= new ResourceSked();
451 int stage_num
= ThePipeline::BackEndStartStage
;
452 StageScheduler
X(res_sked
, stage_num
++);
453 StageScheduler
M(res_sked
, stage_num
++);
454 StageScheduler
W(res_sked
, stage_num
++);
456 if (!inst
->staticInst
) {
457 warn_once("Static Instruction Object Not Set. Can't Create"
458 " Back End Schedule");
463 X
.needs(RegManager
, UseDefUnit::MarkDestRegs
);
464 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
465 if (!idx
|| !inst
->isStore()) {
466 X
.needs(RegManager
, UseDefUnit::ReadSrcReg
, idx
);
470 //@todo: schedule non-spec insts to operate on this cycle
471 // as long as all previous insts are done
472 if ( inst
->isNonSpeculative() ) {
473 // skip execution of non speculative insts until later
474 } else if ( inst
->isMemRef() ) {
475 if ( inst
->isLoad() ) {
476 X
.needs(AGEN
, AGENUnit::GenerateAddr
);
478 } else if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
479 X
.needs(MDU
, MultDivUnit::StartMultDiv
);
481 X
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
485 if (!inst
->isNonSpeculative()) {
486 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
487 M
.needs(MDU
, MultDivUnit::EndMultDiv
);
490 if ( inst
->isLoad() ) {
491 M
.needs(DCache
, CacheUnit::InitiateReadData
);
493 M
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
494 } else if ( inst
->isStore() ) {
495 for (int i
= 1; i
< inst
->numSrcRegs(); i
++ ) {
496 M
.needs(RegManager
, UseDefUnit::ReadSrcReg
, i
);
498 M
.needs(AGEN
, AGENUnit::GenerateAddr
);
499 M
.needs(DCache
, CacheUnit::InitiateWriteData
);
501 M
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
506 if (!inst
->isNonSpeculative()) {
507 if ( inst
->isLoad() ) {
508 W
.needs(DCache
, CacheUnit::CompleteReadData
);
510 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
511 } else if ( inst
->isStore() ) {
512 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
514 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
517 // Finally, Execute Speculative Data
518 if (inst
->isMemRef()) {
519 if (inst
->isLoad()) {
520 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
521 W
.needs(DCache
, CacheUnit::InitiateReadData
);
523 W
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
524 W
.needs(DCache
, CacheUnit::CompleteReadData
);
526 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
527 } else if (inst
->isStore()) {
528 if ( inst
->numSrcRegs() >= 2 ) {
529 W
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
531 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
532 W
.needs(DCache
, CacheUnit::InitiateWriteData
);
534 W
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
535 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
537 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
540 W
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
544 W
.needs(Grad
, GraduationUnit::CheckFault
);
546 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
547 W
.needs(RegManager
, UseDefUnit::WriteDestReg
, idx
);
550 if (inst
->isControl())
551 W
.needs(BPred
, BranchPredictor::UpdatePredictor
);
553 W
.needs(Grad
, GraduationUnit::GraduateInst
);
555 // Insert Back Schedule into our cache of
556 // resource schedules
557 addToSkedCache(inst
, res_sked
);
559 DPRINTF(SkedCache
, "Back End Sked Created for instruction: %s (%08p)\n",
560 inst
->instName(), inst
->getMachInst());
567 InOrderCPU::regStats()
569 /* Register the Resource Pool's stats here.*/
572 /* Register for each Pipeline Stage */
573 for (int stage_num
=0; stage_num
< ThePipeline::NumStages
; stage_num
++) {
574 pipelineStage
[stage_num
]->regStats();
577 /* Register any of the InOrderCPU's stats here.*/
579 .name(name() + ".instsPerContextSwitch")
580 .desc("Instructions Committed Per Context Switch")
581 .prereq(instsPerCtxtSwitch
);
584 .name(name() + ".contextSwitches")
585 .desc("Number of context switches");
588 .name(name() + ".comLoads")
589 .desc("Number of Load instructions committed");
592 .name(name() + ".comStores")
593 .desc("Number of Store instructions committed");
596 .name(name() + ".comBranches")
597 .desc("Number of Branches instructions committed");
600 .name(name() + ".comNops")
601 .desc("Number of Nop instructions committed");
604 .name(name() + ".comNonSpec")
605 .desc("Number of Non-Speculative instructions committed");
608 .name(name() + ".comInts")
609 .desc("Number of Integer instructions committed");
612 .name(name() + ".comFloats")
613 .desc("Number of Floating Point instructions committed");
616 .name(name() + ".timesIdled")
617 .desc("Number of times that the entire CPU went into an idle state and"
618 " unscheduled itself")
622 .name(name() + ".idleCycles")
623 .desc("Number of cycles cpu's stages were not processed");
626 .name(name() + ".runCycles")
627 .desc("Number of cycles cpu stages are processed.");
630 .name(name() + ".activity")
631 .desc("Percentage of cycles cpu is active")
633 activity
= (runCycles
/ numCycles
) * 100;
637 .name(name() + ".threadCycles")
638 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
641 .name(name() + ".smtCycles")
642 .desc("Total number of cycles that the CPU was in SMT-mode");
646 .name(name() + ".committedInsts")
647 .desc("Number of Instructions Simulated (Per-Thread)");
651 .name(name() + ".smtCommittedInsts")
652 .desc("Number of SMT Instructions Simulated (Per-Thread)");
655 .name(name() + ".committedInsts_total")
656 .desc("Number of Instructions Simulated (Total)");
659 .name(name() + ".cpi")
660 .desc("CPI: Cycles Per Instruction (Per-Thread)")
662 cpi
= numCycles
/ committedInsts
;
665 .name(name() + ".smt_cpi")
666 .desc("CPI: Total SMT-CPI")
668 smtCpi
= smtCycles
/ smtCommittedInsts
;
671 .name(name() + ".cpi_total")
672 .desc("CPI: Total CPI of All Threads")
674 totalCpi
= numCycles
/ totalCommittedInsts
;
677 .name(name() + ".ipc")
678 .desc("IPC: Instructions Per Cycle (Per-Thread)")
680 ipc
= committedInsts
/ numCycles
;
683 .name(name() + ".smt_ipc")
684 .desc("IPC: Total SMT-IPC")
686 smtIpc
= smtCommittedInsts
/ smtCycles
;
689 .name(name() + ".ipc_total")
690 .desc("IPC: Total IPC of All Threads")
692 totalIpc
= totalCommittedInsts
/ numCycles
;
701 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
705 checkForInterrupts();
706 bool pipes_idle
= true;
707 //Tick each of the stages
708 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
709 pipelineStage
[stNum
]->tick();
711 pipes_idle
= pipes_idle
&& pipelineStage
[stNum
]->idle
;
719 // Now advance the time buffers one tick
720 timeBuffer
.advance();
721 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
722 stageQueue
[sqNum
]->advance();
724 activityRec
.advance();
726 // Any squashed events, or insts then remove them now
727 cleanUpRemovedEvents();
728 cleanUpRemovedInsts();
730 // Re-schedule CPU for this cycle
731 if (!tickEvent
.scheduled()) {
732 if (_status
== SwitchedOut
) {
734 lastRunningCycle
= curTick();
735 } else if (!activityRec
.active()) {
736 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
737 lastRunningCycle
= curTick();
740 //Tick next_tick = curTick() + cycles(1);
741 //tickEvent.schedule(next_tick);
742 schedule(&tickEvent
, nextCycle(curTick() + 1));
743 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n",
744 nextCycle(curTick() + 1));
749 updateThreadPriority();
756 if (!deferRegistration
) {
757 registerThreadContexts();
760 // Set inSyscall so that the CPU doesn't squash when initially
761 // setting up registers.
762 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
763 thread
[tid
]->inSyscall
= true;
766 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
767 ThreadContext
*src_tc
= threadContexts
[tid
];
768 TheISA::initCPU(src_tc
, src_tc
->contextId());
773 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
774 thread
[tid
]->inSyscall
= false;
776 // Call Initializiation Routine for Resource Pool
781 InOrderCPU::getPort(const std::string
&if_name
, int idx
)
783 return resPool
->getPort(if_name
, idx
);
788 InOrderCPU::hwrei(ThreadID tid
)
790 #if THE_ISA == ALPHA_ISA
791 // Need to clear the lock flag upon returning from an interrupt.
792 setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG
, false, tid
);
794 thread
[tid
]->kernelStats
->hwrei();
795 // FIXME: XXX check for interrupts? XXX
803 InOrderCPU::simPalCheck(int palFunc
, ThreadID tid
)
805 #if THE_ISA == ALPHA_ISA
806 if (this->thread
[tid
]->kernelStats
)
807 this->thread
[tid
]->kernelStats
->callpal(palFunc
,
808 this->threadContexts
[tid
]);
813 if (--System::numSystemsRunning
== 0)
814 exitSimLoop("all cpus halted");
819 if (this->system
->breakpoint())
828 InOrderCPU::checkForInterrupts()
830 for (int i
= 0; i
< threadContexts
.size(); i
++) {
831 ThreadContext
*tc
= threadContexts
[i
];
833 if (interrupts
->checkInterrupts(tc
)) {
834 Fault interrupt
= interrupts
->getInterrupt(tc
);
836 if (interrupt
!= NoFault
) {
837 DPRINTF(Interrupt
, "Processing Intterupt for [tid:%i].\n",
840 ThreadID tid
= tc
->threadId();
841 interrupts
->updateIntrInfo(tc
);
843 // Squash from Last Stage in Pipeline
844 unsigned last_stage
= NumStages
- 1;
845 dummyTrapInst
[tid
]->squashingStage
= last_stage
;
846 pipelineStage
[last_stage
]->setupSquash(dummyTrapInst
[tid
],
849 // By default, setupSquash will always squash from stage + 1
850 pipelineStage
[BackEndStartStage
- 1]->setupSquash(dummyTrapInst
[tid
],
853 // Schedule Squash Through-out Resource Pool
854 resPool
->scheduleEvent(
855 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
,
856 dummyTrapInst
[tid
], 0);
858 // Finally, Setup Trap to happen at end of cycle
859 trapContext(interrupt
, tid
, dummyTrapInst
[tid
]);
866 InOrderCPU::getInterrupts()
868 // Check if there are any outstanding interrupts
869 return interrupts
->getInterrupt(threadContexts
[0]);
874 InOrderCPU::processInterrupts(Fault interrupt
)
876 // Check for interrupts here. For now can copy the code that
877 // exists within isa_fullsys_traits.hh. Also assume that thread 0
878 // is the one that handles the interrupts.
879 // @todo: Possibly consolidate the interrupt checking code.
880 // @todo: Allow other threads to handle interrupts.
882 assert(interrupt
!= NoFault
);
883 interrupts
->updateIntrInfo(threadContexts
[0]);
885 DPRINTF(InOrderCPU
, "Interrupt %s being handled\n", interrupt
->name());
887 // Note: Context ID ok here? Impl. of FS mode needs to revisit this
888 trap(interrupt
, threadContexts
[0]->contextId(), dummyBufferInst
);
893 InOrderCPU::updateMemPorts()
895 // Update all ThreadContext's memory ports (Functional/Virtual
897 ThreadID size
= thread
.size();
898 for (ThreadID i
= 0; i
< size
; ++i
)
899 thread
[i
]->connectMemPorts(thread
[i
]->getTC());
904 InOrderCPU::trapContext(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
906 scheduleCpuEvent(Trap
, fault
, tid
, inst
, delay
);
907 trapPending
[tid
] = true;
911 InOrderCPU::trap(Fault fault
, ThreadID tid
, DynInstPtr inst
)
913 fault
->invoke(tcBase(tid
), inst
->staticInst
);
914 removePipelineStalls(tid
);
918 InOrderCPU::squashFromMemStall(DynInstPtr inst
, ThreadID tid
, int delay
)
920 scheduleCpuEvent(SquashFromMemStall
, NoFault
, tid
, inst
, delay
);
925 InOrderCPU::squashDueToMemStall(int stage_num
, InstSeqNum seq_num
,
928 DPRINTF(InOrderCPU
, "Squashing Pipeline Stages Due to Memory Stall...\n");
930 // Squash all instructions in each stage including
931 // instruction that caused the squash (seq_num - 1)
932 // NOTE: The stage bandwidth needs to be cleared so thats why
933 // the stalling instruction is squashed as well. The stalled
934 // instruction is previously placed in another intermediate buffer
935 // while it's stall is being handled.
936 InstSeqNum squash_seq_num
= seq_num
- 1;
938 for (int stNum
=stage_num
; stNum
>= 0 ; stNum
--) {
939 pipelineStage
[stNum
]->squashDueToMemStall(squash_seq_num
, tid
);
944 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
945 ThreadID tid
, DynInstPtr inst
,
946 unsigned delay
, CPUEventPri event_pri
)
948 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, inst
,
951 Tick sked_tick
= nextCycle(curTick() + ticks(delay
));
953 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
954 eventNames
[c_event
], curTick() + delay
, tid
);
955 schedule(cpu_event
, sked_tick
);
957 cpu_event
->process();
958 cpuEventRemoveList
.push(cpu_event
);
961 // Broadcast event to the Resource Pool
962 // Need to reset tid just in case this is a dummy instruction
964 resPool
->scheduleEvent(c_event
, inst
, 0, 0, tid
);
968 InOrderCPU::isThreadActive(ThreadID tid
)
970 list
<ThreadID
>::iterator isActive
=
971 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
973 return (isActive
!= activeThreads
.end());
977 InOrderCPU::isThreadReady(ThreadID tid
)
979 list
<ThreadID
>::iterator isReady
=
980 std::find(readyThreads
.begin(), readyThreads
.end(), tid
);
982 return (isReady
!= readyThreads
.end());
986 InOrderCPU::isThreadSuspended(ThreadID tid
)
988 list
<ThreadID
>::iterator isSuspended
=
989 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
991 return (isSuspended
!= suspendedThreads
.end());
995 InOrderCPU::activateNextReadyThread()
997 if (readyThreads
.size() >= 1) {
998 ThreadID ready_tid
= readyThreads
.front();
1000 // Activate in Pipeline
1001 activateThread(ready_tid
);
1003 // Activate in Resource Pool
1004 resPool
->activateThread(ready_tid
);
1006 list
<ThreadID
>::iterator ready_it
=
1007 std::find(readyThreads
.begin(), readyThreads
.end(), ready_tid
);
1008 readyThreads
.erase(ready_it
);
1011 "Attempting to activate new thread, but No Ready Threads to"
1014 "Unable to switch to next active thread.\n");
1019 InOrderCPU::activateThread(ThreadID tid
)
1021 if (isThreadSuspended(tid
)) {
1023 "Removing [tid:%i] from suspended threads list.\n", tid
);
1025 list
<ThreadID
>::iterator susp_it
=
1026 std::find(suspendedThreads
.begin(), suspendedThreads
.end(),
1028 suspendedThreads
.erase(susp_it
);
1031 if (threadModel
== SwitchOnCacheMiss
&&
1032 numActiveThreads() == 1) {
1034 "Ignoring activation of [tid:%i], since [tid:%i] is "
1035 "already running.\n", tid
, activeThreadId());
1037 DPRINTF(InOrderCPU
,"Placing [tid:%i] on ready threads list\n",
1040 readyThreads
.push_back(tid
);
1042 } else if (!isThreadActive(tid
)) {
1044 "Adding [tid:%i] to active threads list.\n", tid
);
1045 activeThreads
.push_back(tid
);
1047 activateThreadInPipeline(tid
);
1049 thread
[tid
]->lastActivate
= curTick();
1051 tcBase(tid
)->setStatus(ThreadContext::Active
);
1060 InOrderCPU::activateThreadInPipeline(ThreadID tid
)
1062 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
1063 pipelineStage
[stNum
]->activateThread(tid
);
1068 InOrderCPU::deactivateContext(ThreadID tid
, int delay
)
1070 DPRINTF(InOrderCPU
,"[tid:%i]: Deactivating ...\n", tid
);
1072 scheduleCpuEvent(DeactivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1074 // Be sure to signal that there's some activity so the CPU doesn't
1075 // deschedule itself.
1076 activityRec
.activity();
1082 InOrderCPU::deactivateThread(ThreadID tid
)
1084 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
1086 if (isThreadActive(tid
)) {
1087 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
1089 list
<ThreadID
>::iterator thread_it
=
1090 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
1092 removePipelineStalls(*thread_it
);
1094 activeThreads
.erase(thread_it
);
1096 // Ideally, this should be triggered from the
1097 // suspendContext/Thread functions
1098 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1101 assert(!isThreadActive(tid
));
1105 InOrderCPU::removePipelineStalls(ThreadID tid
)
1107 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
1110 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
1111 pipelineStage
[stNum
]->removeStalls(tid
);
1117 InOrderCPU::updateThreadPriority()
1119 if (activeThreads
.size() > 1)
1121 //DEFAULT TO ROUND ROBIN SCHEME
1122 //e.g. Move highest priority to end of thread list
1123 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
1124 list
<ThreadID
>::iterator list_end
= activeThreads
.end();
1126 unsigned high_thread
= *list_begin
;
1128 activeThreads
.erase(list_begin
);
1130 activeThreads
.push_back(high_thread
);
1135 InOrderCPU::tickThreadStats()
1137 /** Keep track of cycles that each thread is active */
1138 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
1139 while (thread_it
!= activeThreads
.end()) {
1140 threadCycles
[*thread_it
]++;
1144 // Keep track of cycles where SMT is active
1145 if (activeThreads
.size() > 1) {
1151 InOrderCPU::activateContext(ThreadID tid
, int delay
)
1153 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
1156 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1158 // Be sure to signal that there's some activity so the CPU doesn't
1159 // deschedule itself.
1160 activityRec
.activity();
1166 InOrderCPU::activateNextReadyContext(int delay
)
1168 DPRINTF(InOrderCPU
,"Activating next ready thread\n");
1170 scheduleCpuEvent(ActivateNextReadyThread
, NoFault
, 0/*tid*/, dummyInst
[0],
1171 delay
, ActivateNextReadyThread_Pri
);
1173 // Be sure to signal that there's some activity so the CPU doesn't
1174 // deschedule itself.
1175 activityRec
.activity();
1181 InOrderCPU::haltContext(ThreadID tid
, int delay
)
1183 DPRINTF(InOrderCPU
, "[tid:%i]: Calling Halt Context...\n", tid
);
1185 scheduleCpuEvent(HaltThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1187 activityRec
.activity();
1191 InOrderCPU::haltThread(ThreadID tid
)
1193 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Halted Threads List...\n", tid
);
1194 deactivateThread(tid
);
1195 squashThreadInPipeline(tid
);
1196 haltedThreads
.push_back(tid
);
1198 tcBase(tid
)->setStatus(ThreadContext::Halted
);
1200 if (threadModel
== SwitchOnCacheMiss
) {
1201 activateNextReadyContext();
1206 InOrderCPU::suspendContext(ThreadID tid
, int delay
)
1208 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1212 InOrderCPU::suspendThread(ThreadID tid
)
1214 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Suspended Threads List...\n",
1216 deactivateThread(tid
);
1217 suspendedThreads
.push_back(tid
);
1218 thread
[tid
]->lastSuspend
= curTick();
1220 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1224 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
1226 //Squash all instructions in each stage
1227 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
1228 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
1233 InOrderCPU::getPipeStage(int stage_num
)
1235 return pipelineStage
[stage_num
];
1240 InOrderCPU::flattenRegIdx(RegIndex reg_idx
, RegType
®_type
, ThreadID tid
)
1242 if (reg_idx
< FP_Base_DepTag
) {
1244 return isa
[tid
].flattenIntIndex(reg_idx
);
1245 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1246 reg_type
= FloatType
;
1247 reg_idx
-= FP_Base_DepTag
;
1248 return isa
[tid
].flattenFloatIndex(reg_idx
);
1250 reg_type
= MiscType
;
1251 return reg_idx
- TheISA::Ctrl_Base_DepTag
;
1256 InOrderCPU::readIntReg(RegIndex reg_idx
, ThreadID tid
)
1258 DPRINTF(IntRegs
, "[tid:%i]: Reading Int. Reg %i as %x\n",
1259 tid
, reg_idx
, intRegs
[tid
][reg_idx
]);
1261 return intRegs
[tid
][reg_idx
];
1265 InOrderCPU::readFloatReg(RegIndex reg_idx
, ThreadID tid
)
1267 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1268 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1270 return floatRegs
.f
[tid
][reg_idx
];
1274 InOrderCPU::readFloatRegBits(RegIndex reg_idx
, ThreadID tid
)
1276 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1277 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1279 return floatRegs
.i
[tid
][reg_idx
];
1283 InOrderCPU::setIntReg(RegIndex reg_idx
, uint64_t val
, ThreadID tid
)
1285 if (reg_idx
== TheISA::ZeroReg
) {
1286 DPRINTF(IntRegs
, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1287 "(Int. Reg %i) to %x\n", tid
, reg_idx
, val
);
1290 DPRINTF(IntRegs
, "[tid:%i]: Setting Int. Reg %i to %x\n",
1293 intRegs
[tid
][reg_idx
] = val
;
1299 InOrderCPU::setFloatReg(RegIndex reg_idx
, FloatReg val
, ThreadID tid
)
1301 floatRegs
.f
[tid
][reg_idx
] = val
;
1302 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1305 floatRegs
.i
[tid
][reg_idx
],
1306 floatRegs
.f
[tid
][reg_idx
]);
1311 InOrderCPU::setFloatRegBits(RegIndex reg_idx
, FloatRegBits val
, ThreadID tid
)
1313 floatRegs
.i
[tid
][reg_idx
] = val
;
1314 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1317 floatRegs
.i
[tid
][reg_idx
],
1318 floatRegs
.f
[tid
][reg_idx
]);
1322 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
1324 // If Default value is set, then retrieve target thread
1325 if (tid
== InvalidThreadID
) {
1326 tid
= TheISA::getTargetThread(tcBase(tid
));
1329 if (reg_idx
< FP_Base_DepTag
) {
1330 // Integer Register File
1331 return readIntReg(reg_idx
, tid
);
1332 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1333 // Float Register File
1334 reg_idx
-= FP_Base_DepTag
;
1335 return readFloatRegBits(reg_idx
, tid
);
1337 reg_idx
-= Ctrl_Base_DepTag
;
1338 return readMiscReg(reg_idx
, tid
); // Misc. Register File
1342 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
1345 // If Default value is set, then retrieve target thread
1346 if (tid
== InvalidThreadID
) {
1347 tid
= TheISA::getTargetThread(tcBase(tid
));
1350 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
1351 setIntReg(reg_idx
, val
, tid
);
1352 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
1353 reg_idx
-= FP_Base_DepTag
;
1354 setFloatRegBits(reg_idx
, val
, tid
);
1356 reg_idx
-= Ctrl_Base_DepTag
;
1357 setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
1362 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1364 return isa
[tid
].readMiscRegNoEffect(misc_reg
);
1368 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
1370 DPRINTF(InOrderCPU
, "MiscReg: %i\n", misc_reg
);
1371 DPRINTF(InOrderCPU
, "tid: %i\n", tid
);
1372 DPRINTF(InOrderCPU
, "tcBase: %x\n", tcBase(tid
));
1373 DPRINTF(InOrderCPU
, "isa-tid: %x\n", &isa
[tid
]);
1375 return isa
[tid
].readMiscReg(misc_reg
, tcBase(tid
));
1379 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1381 isa
[tid
].setMiscRegNoEffect(misc_reg
, val
);
1385 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1387 isa
[tid
].setMiscReg(misc_reg
, val
, tcBase(tid
));
1392 InOrderCPU::addInst(DynInstPtr inst
)
1394 ThreadID tid
= inst
->readTid();
1396 instList
[tid
].push_back(inst
);
1398 return --(instList
[tid
].end());
1402 InOrderCPU::findInst(InstSeqNum seq_num
, ThreadID tid
)
1404 ListIt it
= instList
[tid
].begin();
1405 ListIt end
= instList
[tid
].end();
1408 if ((*it
)->seqNum
== seq_num
)
1410 else if ((*it
)->seqNum
> seq_num
)
1416 return instList
[tid
].end();
1420 InOrderCPU::updateContextSwitchStats()
1422 // Set Average Stat Here, then reset to 0
1423 instsPerCtxtSwitch
= instsPerSwitch
;
1429 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1431 // Set the nextPC to be fetched if this is the last instruction
1434 // This contributes to the precise state of the CPU
1435 // which can be used when restoring a thread to the CPU after after any
1436 // type of context switching activity (fork, exception, etc.)
1437 TheISA::PCState comm_pc
= inst
->pcState();
1438 lastCommittedPC
[tid
] = comm_pc
;
1439 TheISA::advancePC(comm_pc
, inst
->staticInst
);
1440 pcState(comm_pc
, tid
);
1442 //@todo: may be unnecessary with new-ISA-specific branch handling code
1443 if (inst
->isControl()) {
1444 thread
[tid
]->lastGradIsBranch
= true;
1445 thread
[tid
]->lastBranchPC
= inst
->pcState();
1446 TheISA::advancePC(thread
[tid
]->lastBranchPC
, inst
->staticInst
);
1448 thread
[tid
]->lastGradIsBranch
= false;
1452 // Finalize Trace Data For Instruction
1453 if (inst
->traceData
) {
1454 //inst->traceData->setCycle(curTick());
1455 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1456 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1457 inst
->traceData
->dump();
1458 delete inst
->traceData
;
1459 inst
->traceData
= NULL
;
1462 // Increment active thread's instruction count
1465 // Increment thread-state's instruction count
1466 thread
[tid
]->numInst
++;
1468 // Increment thread-state's instruction stats
1469 thread
[tid
]->numInsts
++;
1471 // Count committed insts per thread stats
1472 committedInsts
[tid
]++;
1474 // Count total insts committed stat
1475 totalCommittedInsts
++;
1477 // Count SMT-committed insts per thread stat
1478 if (numActiveThreads() > 1) {
1479 smtCommittedInsts
[tid
]++;
1482 // Instruction-Mix Stats
1483 if (inst
->isLoad()) {
1485 } else if (inst
->isStore()) {
1487 } else if (inst
->isControl()) {
1489 } else if (inst
->isNop()) {
1491 } else if (inst
->isNonSpeculative()) {
1493 } else if (inst
->isInteger()) {
1495 } else if (inst
->isFloating()) {
1499 // Check for instruction-count-based events.
1500 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numInst
);
1502 // Finally, remove instruction from CPU
1506 // currently unused function, but substitute repetitive code w/this function
1509 InOrderCPU::addToRemoveList(DynInstPtr inst
)
1511 removeInstsThisCycle
= true;
1512 if (!inst
->isRemoveList()) {
1513 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1514 "[sn:%lli] to remove list\n",
1515 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1516 inst
->setRemoveList();
1517 removeList
.push(inst
->getInstListIt());
1519 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1520 "[sn:%lli], already remove list\n",
1521 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1527 InOrderCPU::removeInst(DynInstPtr inst
)
1529 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %s "
1531 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1533 removeInstsThisCycle
= true;
1535 // Remove the instruction.
1536 if (!inst
->isRemoveList()) {
1537 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1538 "[sn:%lli] to remove list\n",
1539 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1540 inst
->setRemoveList();
1541 removeList
.push(inst
->getInstListIt());
1543 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1544 "[sn:%lli], already on remove list\n",
1545 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1551 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1553 //assert(!instList[tid].empty());
1555 removeInstsThisCycle
= true;
1557 ListIt inst_iter
= instList
[tid
].end();
1561 DPRINTF(InOrderCPU
, "Squashing instructions from CPU instruction "
1562 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1563 tid
, seq_num
, (*inst_iter
)->seqNum
);
1565 while ((*inst_iter
)->seqNum
> seq_num
) {
1567 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1569 squashInstIt(inst_iter
, tid
);
1580 InOrderCPU::squashInstIt(const ListIt inst_it
, ThreadID tid
)
1582 DynInstPtr inst
= (*inst_it
);
1583 if (inst
->threadNumber
== tid
) {
1584 DPRINTF(InOrderCPU
, "Squashing instruction, "
1585 "[tid:%i] [sn:%lli] PC %s\n",
1590 inst
->setSquashed();
1591 archRegDepMap
[tid
].remove(inst
);
1593 if (!inst
->isRemoveList()) {
1594 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1595 "[sn:%lli] to remove list\n",
1596 inst
->threadNumber
, inst
->pcState(),
1598 inst
->setRemoveList();
1599 removeList
.push(inst_it
);
1601 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i]"
1602 " PC %s [sn:%lli], already on remove list\n",
1603 inst
->threadNumber
, inst
->pcState(),
1613 InOrderCPU::cleanUpRemovedInsts()
1615 while (!removeList
.empty()) {
1616 DPRINTF(InOrderCPU
, "Removing instruction, "
1617 "[tid:%i] [sn:%lli] PC %s\n",
1618 (*removeList
.front())->threadNumber
,
1619 (*removeList
.front())->seqNum
,
1620 (*removeList
.front())->pcState());
1622 DynInstPtr inst
= *removeList
.front();
1623 ThreadID tid
= inst
->threadNumber
;
1625 // Remove From Register Dependency Map, If Necessary
1626 // archRegDepMap[tid].remove(inst);
1628 // Clear if Non-Speculative
1629 if (inst
->staticInst
&&
1630 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1631 nonSpecInstActive
[tid
] == true) {
1632 nonSpecInstActive
[tid
] = false;
1635 inst
->onInstList
= false;
1637 instList
[tid
].erase(removeList
.front());
1642 removeInstsThisCycle
= false;
1646 InOrderCPU::cleanUpRemovedEvents()
1648 while (!cpuEventRemoveList
.empty()) {
1649 Event
*cpu_event
= cpuEventRemoveList
.front();
1650 cpuEventRemoveList
.pop();
1657 InOrderCPU::dumpInsts()
1661 ListIt inst_list_it
= instList
[0].begin();
1663 cprintf("Dumping Instruction List\n");
1665 while (inst_list_it
!= instList
[0].end()) {
1666 cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1668 num
, (*inst_list_it
)->pcState(),
1669 (*inst_list_it
)->threadNumber
,
1670 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1671 (*inst_list_it
)->isSquashed());
1678 InOrderCPU::wakeCPU()
1680 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1681 DPRINTF(Activity
, "CPU already running.\n");
1685 DPRINTF(Activity
, "Waking up CPU\n");
1687 Tick extra_cycles
= tickToCycles((curTick() - 1) - lastRunningCycle
);
1689 idleCycles
+= extra_cycles
;
1690 for (int stage_num
= 0; stage_num
< NumStages
; stage_num
++) {
1691 pipelineStage
[stage_num
]->idleCycles
+= extra_cycles
;
1694 numCycles
+= extra_cycles
;
1696 schedule(&tickEvent
, nextCycle(curTick()));
1700 // Lots of copied full system code...place into BaseCPU class?
1702 InOrderCPU::wakeup()
1704 if (thread
[0]->status() != ThreadContext::Suspended
)
1709 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1710 threadContexts
[0]->activate();
1716 InOrderCPU::syscallContext(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
1718 //@todo: squash behind syscall
1719 scheduleCpuEvent(Syscall
, fault
, tid
, inst
, delay
, Syscall_Pri
);
1723 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1725 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1727 DPRINTF(Activity
,"Activity: syscall() called.\n");
1729 // Temporarily increase this by one to account for the syscall
1731 ++(this->thread
[tid
]->funcExeInst
);
1733 // Execute the actual syscall.
1734 this->thread
[tid
]->syscall(callnum
);
1736 // Decrease funcExeInst by one as the normal commit will handle
1738 --(this->thread
[tid
]->funcExeInst
);
1740 // Clear Non-Speculative Block Variable
1741 nonSpecInstActive
[tid
] = false;
1746 InOrderCPU::getITBPtr()
1748 CacheUnit
*itb_res
=
1749 dynamic_cast<CacheUnit
*>(resPool
->getResource(fetchPortIdx
));
1750 return itb_res
->tlb();
1755 InOrderCPU::getDTBPtr()
1757 CacheUnit
*dtb_res
=
1758 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1759 return dtb_res
->tlb();
1763 InOrderCPU::read(DynInstPtr inst
, Addr addr
,
1764 uint8_t *data
, unsigned size
, unsigned flags
)
1766 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1767 // you want to run w/out caches?
1768 CacheUnit
*cache_res
=
1769 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1771 return cache_res
->read(inst
, addr
, data
, size
, flags
);
1775 InOrderCPU::write(DynInstPtr inst
, uint8_t *data
, unsigned size
,
1776 Addr addr
, unsigned flags
, uint64_t *write_res
)
1778 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1779 // you want to run w/out caches?
1780 CacheUnit
*cache_res
=
1781 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1782 return cache_res
->write(inst
, data
, size
, addr
, flags
, write_res
);