2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007 MIPS Technologies, Inc.
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Korey Sewell
46 #include "arch/utility.hh"
47 #include "base/bigint.hh"
48 #include "config/the_isa.hh"
49 #include "cpu/inorder/resources/cache_unit.hh"
50 #include "cpu/inorder/resources/resource_list.hh"
51 #include "cpu/inorder/cpu.hh"
52 #include "cpu/inorder/first_stage.hh"
53 #include "cpu/inorder/inorder_dyn_inst.hh"
54 #include "cpu/inorder/pipeline_traits.hh"
55 #include "cpu/inorder/resource_pool.hh"
56 #include "cpu/inorder/thread_context.hh"
57 #include "cpu/inorder/thread_state.hh"
58 #include "cpu/activity.hh"
59 #include "cpu/base.hh"
60 #include "cpu/exetrace.hh"
61 #include "cpu/quiesce_event.hh"
62 #include "cpu/simple_thread.hh"
63 #include "cpu/thread_context.hh"
64 #include "debug/Activity.hh"
65 #include "debug/InOrderCPU.hh"
66 #include "debug/InOrderCachePort.hh"
67 #include "debug/Interrupt.hh"
68 #include "debug/Quiesce.hh"
69 #include "debug/RefCount.hh"
70 #include "debug/SkedCache.hh"
71 #include "params/InOrderCPU.hh"
72 #include "sim/full_system.hh"
73 #include "sim/process.hh"
74 #include "sim/stat_control.hh"
75 #include "sim/system.hh"
77 #if THE_ISA == ALPHA_ISA
78 #include "arch/alpha/osfpal.hh"
82 using namespace TheISA
;
83 using namespace ThePipeline
;
85 InOrderCPU::CachePort::CachePort(CacheUnit
*_cacheUnit
,
86 const std::string
& name
) :
87 MasterPort(_cacheUnit
->name() + name
, _cacheUnit
->cpu
),
92 InOrderCPU::CachePort::recvTimingResp(Packet
*pkt
)
95 DPRINTF(InOrderCachePort
, "Got error packet back for address: %x\n",
98 cacheUnit
->processCacheCompletion(pkt
);
104 InOrderCPU::CachePort::recvRetry()
106 cacheUnit
->recvRetry();
109 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
110 : Event(CPU_Tick_Pri
), cpu(c
)
115 InOrderCPU::TickEvent::process()
122 InOrderCPU::TickEvent::description() const
124 return "InOrderCPU tick event";
127 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
128 Fault fault
, ThreadID _tid
, DynInstPtr inst
,
129 CPUEventPri event_pri
)
130 : Event(event_pri
), cpu(_cpu
)
132 setEvent(e_type
, fault
, _tid
, inst
);
136 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
139 "ActivateNextReadyThread",
145 "SquashFromMemStall",
150 InOrderCPU::CPUEvent::process()
152 switch (cpuEventType
)
155 cpu
->activateThread(tid
);
156 cpu
->resPool
->activateThread(tid
);
159 case ActivateNextReadyThread
:
160 cpu
->activateNextReadyThread();
163 case DeactivateThread
:
164 cpu
->deactivateThread(tid
);
165 cpu
->resPool
->deactivateThread(tid
);
169 cpu
->haltThread(tid
);
170 cpu
->resPool
->deactivateThread(tid
);
174 cpu
->suspendThread(tid
);
175 cpu
->resPool
->suspendThread(tid
);
178 case SquashFromMemStall
:
179 cpu
->squashDueToMemStall(inst
->squashingStage
, inst
->seqNum
, tid
);
180 cpu
->resPool
->squashDueToMemStall(inst
, inst
->squashingStage
,
185 DPRINTF(InOrderCPU
, "Trapping CPU\n");
186 cpu
->trap(fault
, tid
, inst
);
187 cpu
->resPool
->trap(fault
, tid
, inst
);
188 cpu
->trapPending
[tid
] = false;
192 cpu
->syscall(inst
->syscallNum
, tid
);
193 cpu
->resPool
->trap(fault
, tid
, inst
);
197 fatal("Unrecognized Event Type %s", eventNames
[cpuEventType
]);
200 cpu
->cpuEventRemoveList
.push(this);
206 InOrderCPU::CPUEvent::description() const
208 return "InOrderCPU event";
212 InOrderCPU::CPUEvent::scheduleEvent(Cycles delay
)
214 assert(!scheduled() || squashed());
215 cpu
->reschedule(this, cpu
->clockEdge(delay
), true);
219 InOrderCPU::CPUEvent::unscheduleEvent()
225 InOrderCPU::InOrderCPU(Params
*params
)
227 cpu_id(params
->cpu_id
),
231 stageWidth(params
->stageWidth
),
232 resPool(new ResourcePool(this, params
)),
233 isa(numThreads
, NULL
),
235 dataPort(resPool
->getDataUnit(), ".dcache_port"),
236 instPort(resPool
->getInstUnit(), ".icache_port"),
237 removeInstsThisCycle(false),
238 activityRec(params
->name
, NumStages
, 10, params
->activity
),
239 system(params
->system
),
245 stageTracing(params
->stageTracing
),
251 // Resize for Multithreading CPUs
252 thread
.resize(numThreads
);
254 ThreadID active_threads
= params
->workload
.size();
258 active_threads
= params
->workload
.size();
260 if (active_threads
> MaxThreads
) {
261 panic("Workload Size too large. Increase the 'MaxThreads'"
262 "in your InOrder implementation or "
263 "edit your workload size.");
267 if (active_threads
> 1) {
268 threadModel
= (InOrderCPU::ThreadModel
) params
->threadModel
;
270 if (threadModel
== SMT
) {
271 DPRINTF(InOrderCPU
, "Setting Thread Model to SMT.\n");
272 } else if (threadModel
== SwitchOnCacheMiss
) {
273 DPRINTF(InOrderCPU
, "Setting Thread Model to "
274 "Switch On Cache Miss\n");
278 threadModel
= Single
;
282 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
283 isa
[tid
] = params
->isa
[tid
];
285 lastCommittedPC
[tid
].set(0);
288 // SMT is not supported in FS mode yet.
289 assert(numThreads
== 1);
290 thread
[tid
] = new Thread(this, 0, NULL
);
292 if (tid
< (ThreadID
)params
->workload
.size()) {
293 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
294 tid
, params
->workload
[tid
]->progName());
296 new Thread(this, tid
, params
->workload
[tid
]);
298 //Allocate Empty thread so M5 can use later
299 //when scheduling threads to CPU
300 Process
* dummy_proc
= params
->workload
[0];
301 thread
[tid
] = new Thread(this, tid
, dummy_proc
);
304 // Eventually set this with parameters...
308 // Setup the TC that will serve as the interface to the threads/CPU.
309 InOrderThreadContext
*tc
= new InOrderThreadContext
;
311 tc
->thread
= thread
[tid
];
313 // Setup quiesce event.
314 this->thread
[tid
]->quiesceEvent
= new EndQuiesceEvent(tc
);
316 // Give the thread the TC.
317 thread
[tid
]->tc
= tc
;
318 thread
[tid
]->setFuncExeInst(0);
319 globalSeqNum
[tid
] = 1;
321 // Add the TC to the CPU's list of TC's.
322 this->threadContexts
.push_back(tc
);
325 // Initialize TimeBuffer Stage Queues
326 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
327 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
328 stageQueue
[stNum
]->id(stNum
);
332 // Set Up Pipeline Stages
333 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
335 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
337 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
339 pipelineStage
[stNum
]->setCPU(this);
340 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
341 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
343 // Take Care of 1st/Nth stages
345 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
346 if (stNum
< NumStages
- 1)
347 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
350 // Initialize thread specific variables
351 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
352 archRegDepMap
[tid
].setCPU(this);
354 nonSpecInstActive
[tid
] = false;
355 nonSpecSeqNum
[tid
] = 0;
357 squashSeqNum
[tid
] = MaxAddr
;
358 lastSquashCycle
[tid
] = 0;
360 memset(intRegs
[tid
], 0, sizeof(intRegs
[tid
]));
361 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
364 // Define dummy instructions and resource requests to be used.
365 dummyInst
[tid
] = new InOrderDynInst(this,
371 dummyReq
[tid
] = new ResourceRequest(resPool
->getResource(0));
375 // Use this dummy inst to force squashing behind every instruction
377 dummyTrapInst
[tid
] = new InOrderDynInst(this, NULL
, 0, 0, 0);
378 dummyTrapInst
[tid
]->seqNum
= 0;
379 dummyTrapInst
[tid
]->squashSeqNum
= 0;
380 dummyTrapInst
[tid
]->setTid(tid
);
383 trapPending
[tid
] = false;
387 // InOrderCPU always requires an interrupt controller.
388 if (!params
->switched_out
&& !interrupts
) {
389 fatal("InOrderCPU %s has no interrupt controller.\n"
390 "Ensure createInterruptController() is called.\n", name());
393 dummyReqInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
394 dummyReqInst
->setSquashed();
395 dummyReqInst
->resetInstCount();
397 dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
398 dummyBufferInst
->setSquashed();
399 dummyBufferInst
->resetInstCount();
401 endOfSkedIt
= skedCache
.end();
402 frontEndSked
= createFrontEndSked();
403 faultSked
= createFaultSked();
405 lastRunningCycle
= curCycle();
410 // Schedule First Tick Event, CPU will reschedule itself from here on out.
411 scheduleTickEvent(Cycles(0));
414 InOrderCPU::~InOrderCPU()
418 SkedCacheIt sked_it
= skedCache
.begin();
419 SkedCacheIt sked_end
= skedCache
.end();
421 while (sked_it
!= sked_end
) {
422 delete (*sked_it
).second
;
428 m5::hash_map
<InOrderCPU::SkedID
, ThePipeline::RSkedPtr
> InOrderCPU::skedCache
;
431 InOrderCPU::createFrontEndSked()
433 RSkedPtr res_sked
= new ResourceSked();
435 StageScheduler
F(res_sked
, stage_num
++);
436 StageScheduler
D(res_sked
, stage_num
++);
439 F
.needs(FetchSeq
, FetchSeqUnit::AssignNextPC
);
440 F
.needs(ICache
, FetchUnit::InitiateFetch
);
443 D
.needs(ICache
, FetchUnit::CompleteFetch
);
444 D
.needs(Decode
, DecodeUnit::DecodeInst
);
445 D
.needs(BPred
, BranchPredictor::PredictBranch
);
446 D
.needs(FetchSeq
, FetchSeqUnit::UpdateTargetPC
);
449 DPRINTF(SkedCache
, "Resource Sked created for instruction Front End\n");
455 InOrderCPU::createFaultSked()
457 RSkedPtr res_sked
= new ResourceSked();
458 StageScheduler
W(res_sked
, NumStages
- 1);
459 W
.needs(Grad
, GraduationUnit::CheckFault
);
460 DPRINTF(SkedCache
, "Resource Sked created for instruction Faults\n");
465 InOrderCPU::createBackEndSked(DynInstPtr inst
)
467 RSkedPtr res_sked
= lookupSked(inst
);
468 if (res_sked
!= NULL
) {
469 DPRINTF(SkedCache
, "Found %s in sked cache.\n",
473 res_sked
= new ResourceSked();
476 int stage_num
= ThePipeline::BackEndStartStage
;
477 StageScheduler
X(res_sked
, stage_num
++);
478 StageScheduler
M(res_sked
, stage_num
++);
479 StageScheduler
W(res_sked
, stage_num
++);
481 if (!inst
->staticInst
) {
482 warn_once("Static Instruction Object Not Set. Can't Create"
483 " Back End Schedule");
488 X
.needs(RegManager
, UseDefUnit::MarkDestRegs
);
489 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
490 if (!idx
|| !inst
->isStore()) {
491 X
.needs(RegManager
, UseDefUnit::ReadSrcReg
, idx
);
495 //@todo: schedule non-spec insts to operate on this cycle
496 // as long as all previous insts are done
497 if ( inst
->isNonSpeculative() ) {
498 // skip execution of non speculative insts until later
499 } else if ( inst
->isMemRef() ) {
500 if ( inst
->isLoad() ) {
501 X
.needs(AGEN
, AGENUnit::GenerateAddr
);
503 } else if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
504 X
.needs(MDU
, MultDivUnit::StartMultDiv
);
506 X
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
510 if (!inst
->isNonSpeculative()) {
511 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
512 M
.needs(MDU
, MultDivUnit::EndMultDiv
);
515 if ( inst
->isLoad() ) {
516 M
.needs(DCache
, CacheUnit::InitiateReadData
);
518 M
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
519 } else if ( inst
->isStore() ) {
520 for (int i
= 1; i
< inst
->numSrcRegs(); i
++ ) {
521 M
.needs(RegManager
, UseDefUnit::ReadSrcReg
, i
);
523 M
.needs(AGEN
, AGENUnit::GenerateAddr
);
524 M
.needs(DCache
, CacheUnit::InitiateWriteData
);
526 M
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
531 if (!inst
->isNonSpeculative()) {
532 if ( inst
->isLoad() ) {
533 W
.needs(DCache
, CacheUnit::CompleteReadData
);
535 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
536 } else if ( inst
->isStore() ) {
537 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
539 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
542 // Finally, Execute Speculative Data
543 if (inst
->isMemRef()) {
544 if (inst
->isLoad()) {
545 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
546 W
.needs(DCache
, CacheUnit::InitiateReadData
);
548 W
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
549 W
.needs(DCache
, CacheUnit::CompleteReadData
);
551 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
552 } else if (inst
->isStore()) {
553 if ( inst
->numSrcRegs() >= 2 ) {
554 W
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
556 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
557 W
.needs(DCache
, CacheUnit::InitiateWriteData
);
559 W
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
560 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
562 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
565 W
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
569 W
.needs(Grad
, GraduationUnit::CheckFault
);
571 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
572 W
.needs(RegManager
, UseDefUnit::WriteDestReg
, idx
);
575 if (inst
->isControl())
576 W
.needs(BPred
, BranchPredictor::UpdatePredictor
);
578 W
.needs(Grad
, GraduationUnit::GraduateInst
);
580 // Insert Back Schedule into our cache of
581 // resource schedules
582 addToSkedCache(inst
, res_sked
);
584 DPRINTF(SkedCache
, "Back End Sked Created for instruction: %s (%08p)\n",
585 inst
->instName(), inst
->getMachInst());
592 InOrderCPU::regStats()
594 /* Register the Resource Pool's stats here.*/
597 /* Register for each Pipeline Stage */
598 for (int stage_num
=0; stage_num
< ThePipeline::NumStages
; stage_num
++) {
599 pipelineStage
[stage_num
]->regStats();
602 /* Register any of the InOrderCPU's stats here.*/
604 .name(name() + ".instsPerContextSwitch")
605 .desc("Instructions Committed Per Context Switch")
606 .prereq(instsPerCtxtSwitch
);
609 .name(name() + ".contextSwitches")
610 .desc("Number of context switches");
613 .name(name() + ".comLoads")
614 .desc("Number of Load instructions committed");
617 .name(name() + ".comStores")
618 .desc("Number of Store instructions committed");
621 .name(name() + ".comBranches")
622 .desc("Number of Branches instructions committed");
625 .name(name() + ".comNops")
626 .desc("Number of Nop instructions committed");
629 .name(name() + ".comNonSpec")
630 .desc("Number of Non-Speculative instructions committed");
633 .name(name() + ".comInts")
634 .desc("Number of Integer instructions committed");
637 .name(name() + ".comFloats")
638 .desc("Number of Floating Point instructions committed");
641 .name(name() + ".timesIdled")
642 .desc("Number of times that the entire CPU went into an idle state and"
643 " unscheduled itself")
647 .name(name() + ".idleCycles")
648 .desc("Number of cycles cpu's stages were not processed");
651 .name(name() + ".runCycles")
652 .desc("Number of cycles cpu stages are processed.");
655 .name(name() + ".activity")
656 .desc("Percentage of cycles cpu is active")
658 activity
= (runCycles
/ numCycles
) * 100;
662 .name(name() + ".threadCycles")
663 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
666 .name(name() + ".smtCycles")
667 .desc("Total number of cycles that the CPU was in SMT-mode");
671 .name(name() + ".committedInsts")
672 .desc("Number of Instructions committed (Per-Thread)");
676 .name(name() + ".committedOps")
677 .desc("Number of Ops committed (Per-Thread)");
681 .name(name() + ".smtCommittedInsts")
682 .desc("Number of SMT Instructions committed (Per-Thread)");
685 .name(name() + ".committedInsts_total")
686 .desc("Number of Instructions committed (Total)");
689 .name(name() + ".cpi")
690 .desc("CPI: Cycles Per Instruction (Per-Thread)")
692 cpi
= numCycles
/ committedInsts
;
695 .name(name() + ".smt_cpi")
696 .desc("CPI: Total SMT-CPI")
698 smtCpi
= smtCycles
/ smtCommittedInsts
;
701 .name(name() + ".cpi_total")
702 .desc("CPI: Total CPI of All Threads")
704 totalCpi
= numCycles
/ totalCommittedInsts
;
707 .name(name() + ".ipc")
708 .desc("IPC: Instructions Per Cycle (Per-Thread)")
710 ipc
= committedInsts
/ numCycles
;
713 .name(name() + ".smt_ipc")
714 .desc("IPC: Total SMT-IPC")
716 smtIpc
= smtCommittedInsts
/ smtCycles
;
719 .name(name() + ".ipc_total")
720 .desc("IPC: Total IPC of All Threads")
722 totalIpc
= totalCommittedInsts
/ numCycles
;
731 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
735 checkForInterrupts();
737 bool pipes_idle
= true;
738 //Tick each of the stages
739 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
740 pipelineStage
[stNum
]->tick();
742 pipes_idle
= pipes_idle
&& pipelineStage
[stNum
]->idle
;
750 // Now advance the time buffers one tick
751 timeBuffer
.advance();
752 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
753 stageQueue
[sqNum
]->advance();
755 activityRec
.advance();
757 // Any squashed events, or insts then remove them now
758 cleanUpRemovedEvents();
759 cleanUpRemovedInsts();
761 // Re-schedule CPU for this cycle
762 if (!tickEvent
.scheduled()) {
763 if (_status
== SwitchedOut
) {
765 lastRunningCycle
= curCycle();
766 } else if (!activityRec
.active()) {
767 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
768 lastRunningCycle
= curCycle();
771 //Tick next_tick = curTick() + cycles(1);
772 //tickEvent.schedule(next_tick);
773 schedule(&tickEvent
, clockEdge(Cycles(1)));
774 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n",
775 clockEdge(Cycles(1)));
780 updateThreadPriority();
789 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
790 // Set noSquashFromTC so that the CPU doesn't squash when initially
791 // setting up registers.
792 thread
[tid
]->noSquashFromTC
= true;
793 // Initialise the ThreadContext's memory proxies
794 thread
[tid
]->initMemProxies(thread
[tid
]->getTC());
797 if (FullSystem
&& !params()->switched_out
) {
798 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
799 ThreadContext
*src_tc
= threadContexts
[tid
];
800 TheISA::initCPU(src_tc
, src_tc
->contextId());
804 // Clear noSquashFromTC.
805 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
806 thread
[tid
]->noSquashFromTC
= false;
808 // Call Initializiation Routine for Resource Pool
813 InOrderCPU::verifyMemoryMode() const
815 if (!system
->isTimingMode()) {
816 fatal("The in-order CPU requires the memory system to be in "
822 InOrderCPU::hwrei(ThreadID tid
)
824 #if THE_ISA == ALPHA_ISA
825 // Need to clear the lock flag upon returning from an interrupt.
826 setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG
, false, tid
);
828 thread
[tid
]->kernelStats
->hwrei();
829 // FIXME: XXX check for interrupts? XXX
837 InOrderCPU::simPalCheck(int palFunc
, ThreadID tid
)
839 #if THE_ISA == ALPHA_ISA
840 if (this->thread
[tid
]->kernelStats
)
841 this->thread
[tid
]->kernelStats
->callpal(palFunc
,
842 this->threadContexts
[tid
]);
847 if (--System::numSystemsRunning
== 0)
848 exitSimLoop("all cpus halted");
853 if (this->system
->breakpoint())
862 InOrderCPU::checkForInterrupts()
864 for (int i
= 0; i
< threadContexts
.size(); i
++) {
865 ThreadContext
*tc
= threadContexts
[i
];
867 if (interrupts
->checkInterrupts(tc
)) {
868 Fault interrupt
= interrupts
->getInterrupt(tc
);
870 if (interrupt
!= NoFault
) {
871 DPRINTF(Interrupt
, "Processing Intterupt for [tid:%i].\n",
874 ThreadID tid
= tc
->threadId();
875 interrupts
->updateIntrInfo(tc
);
877 // Squash from Last Stage in Pipeline
878 unsigned last_stage
= NumStages
- 1;
879 dummyTrapInst
[tid
]->squashingStage
= last_stage
;
880 pipelineStage
[last_stage
]->setupSquash(dummyTrapInst
[tid
],
883 // By default, setupSquash will always squash from stage + 1
884 pipelineStage
[BackEndStartStage
- 1]->setupSquash(dummyTrapInst
[tid
],
887 // Schedule Squash Through-out Resource Pool
888 resPool
->scheduleEvent(
889 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
,
890 dummyTrapInst
[tid
], Cycles(0));
892 // Finally, Setup Trap to happen at end of cycle
893 trapContext(interrupt
, tid
, dummyTrapInst
[tid
]);
900 InOrderCPU::getInterrupts()
902 // Check if there are any outstanding interrupts
903 return interrupts
->getInterrupt(threadContexts
[0]);
907 InOrderCPU::processInterrupts(Fault interrupt
)
909 // Check for interrupts here. For now can copy the code that
910 // exists within isa_fullsys_traits.hh. Also assume that thread 0
911 // is the one that handles the interrupts.
912 // @todo: Possibly consolidate the interrupt checking code.
913 // @todo: Allow other threads to handle interrupts.
915 assert(interrupt
!= NoFault
);
916 interrupts
->updateIntrInfo(threadContexts
[0]);
918 DPRINTF(InOrderCPU
, "Interrupt %s being handled\n", interrupt
->name());
920 // Note: Context ID ok here? Impl. of FS mode needs to revisit this
921 trap(interrupt
, threadContexts
[0]->contextId(), dummyBufferInst
);
925 InOrderCPU::trapContext(Fault fault
, ThreadID tid
, DynInstPtr inst
,
928 scheduleCpuEvent(Trap
, fault
, tid
, inst
, delay
);
929 trapPending
[tid
] = true;
933 InOrderCPU::trap(Fault fault
, ThreadID tid
, DynInstPtr inst
)
935 fault
->invoke(tcBase(tid
), inst
->staticInst
);
936 removePipelineStalls(tid
);
940 InOrderCPU::squashFromMemStall(DynInstPtr inst
, ThreadID tid
,
943 scheduleCpuEvent(SquashFromMemStall
, NoFault
, tid
, inst
, delay
);
948 InOrderCPU::squashDueToMemStall(int stage_num
, InstSeqNum seq_num
,
951 DPRINTF(InOrderCPU
, "Squashing Pipeline Stages Due to Memory Stall...\n");
953 // Squash all instructions in each stage including
954 // instruction that caused the squash (seq_num - 1)
955 // NOTE: The stage bandwidth needs to be cleared so thats why
956 // the stalling instruction is squashed as well. The stalled
957 // instruction is previously placed in another intermediate buffer
958 // while it's stall is being handled.
959 InstSeqNum squash_seq_num
= seq_num
- 1;
961 for (int stNum
=stage_num
; stNum
>= 0 ; stNum
--) {
962 pipelineStage
[stNum
]->squashDueToMemStall(squash_seq_num
, tid
);
967 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
968 ThreadID tid
, DynInstPtr inst
,
969 Cycles delay
, CPUEventPri event_pri
)
971 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, inst
,
974 Tick sked_tick
= clockEdge(delay
);
975 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
976 eventNames
[c_event
], curTick() + delay
, tid
);
977 schedule(cpu_event
, sked_tick
);
979 // Broadcast event to the Resource Pool
980 // Need to reset tid just in case this is a dummy instruction
982 // @todo: Is this really right? Should the delay not be passed on?
983 resPool
->scheduleEvent(c_event
, inst
, Cycles(0), 0, tid
);
987 InOrderCPU::isThreadActive(ThreadID tid
)
989 list
<ThreadID
>::iterator isActive
=
990 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
992 return (isActive
!= activeThreads
.end());
996 InOrderCPU::isThreadReady(ThreadID tid
)
998 list
<ThreadID
>::iterator isReady
=
999 std::find(readyThreads
.begin(), readyThreads
.end(), tid
);
1001 return (isReady
!= readyThreads
.end());
1005 InOrderCPU::isThreadSuspended(ThreadID tid
)
1007 list
<ThreadID
>::iterator isSuspended
=
1008 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
1010 return (isSuspended
!= suspendedThreads
.end());
1014 InOrderCPU::activateNextReadyThread()
1016 if (readyThreads
.size() >= 1) {
1017 ThreadID ready_tid
= readyThreads
.front();
1019 // Activate in Pipeline
1020 activateThread(ready_tid
);
1022 // Activate in Resource Pool
1023 resPool
->activateThread(ready_tid
);
1025 list
<ThreadID
>::iterator ready_it
=
1026 std::find(readyThreads
.begin(), readyThreads
.end(), ready_tid
);
1027 readyThreads
.erase(ready_it
);
1030 "Attempting to activate new thread, but No Ready Threads to"
1033 "Unable to switch to next active thread.\n");
1038 InOrderCPU::activateThread(ThreadID tid
)
1040 if (isThreadSuspended(tid
)) {
1042 "Removing [tid:%i] from suspended threads list.\n", tid
);
1044 list
<ThreadID
>::iterator susp_it
=
1045 std::find(suspendedThreads
.begin(), suspendedThreads
.end(),
1047 suspendedThreads
.erase(susp_it
);
1050 if (threadModel
== SwitchOnCacheMiss
&&
1051 numActiveThreads() == 1) {
1053 "Ignoring activation of [tid:%i], since [tid:%i] is "
1054 "already running.\n", tid
, activeThreadId());
1056 DPRINTF(InOrderCPU
,"Placing [tid:%i] on ready threads list\n",
1059 readyThreads
.push_back(tid
);
1061 } else if (!isThreadActive(tid
)) {
1063 "Adding [tid:%i] to active threads list.\n", tid
);
1064 activeThreads
.push_back(tid
);
1066 activateThreadInPipeline(tid
);
1068 thread
[tid
]->lastActivate
= curTick();
1070 tcBase(tid
)->setStatus(ThreadContext::Active
);
1079 InOrderCPU::activateThreadInPipeline(ThreadID tid
)
1081 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
1082 pipelineStage
[stNum
]->activateThread(tid
);
1087 InOrderCPU::deactivateContext(ThreadID tid
, Cycles delay
)
1089 DPRINTF(InOrderCPU
,"[tid:%i]: Deactivating ...\n", tid
);
1091 scheduleCpuEvent(DeactivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1093 // Be sure to signal that there's some activity so the CPU doesn't
1094 // deschedule itself.
1095 activityRec
.activity();
1101 InOrderCPU::deactivateThread(ThreadID tid
)
1103 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
1105 if (isThreadActive(tid
)) {
1106 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
1108 list
<ThreadID
>::iterator thread_it
=
1109 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
1111 removePipelineStalls(*thread_it
);
1113 activeThreads
.erase(thread_it
);
1115 // Ideally, this should be triggered from the
1116 // suspendContext/Thread functions
1117 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1120 assert(!isThreadActive(tid
));
1124 InOrderCPU::removePipelineStalls(ThreadID tid
)
1126 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
1129 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
1130 pipelineStage
[stNum
]->removeStalls(tid
);
1136 InOrderCPU::updateThreadPriority()
1138 if (activeThreads
.size() > 1)
1140 //DEFAULT TO ROUND ROBIN SCHEME
1141 //e.g. Move highest priority to end of thread list
1142 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
1144 unsigned high_thread
= *list_begin
;
1146 activeThreads
.erase(list_begin
);
1148 activeThreads
.push_back(high_thread
);
1153 InOrderCPU::tickThreadStats()
1155 /** Keep track of cycles that each thread is active */
1156 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
1157 while (thread_it
!= activeThreads
.end()) {
1158 threadCycles
[*thread_it
]++;
1162 // Keep track of cycles where SMT is active
1163 if (activeThreads
.size() > 1) {
1169 InOrderCPU::activateContext(ThreadID tid
, Cycles delay
)
1171 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
1174 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1176 // Be sure to signal that there's some activity so the CPU doesn't
1177 // deschedule itself.
1178 activityRec
.activity();
1184 InOrderCPU::activateNextReadyContext(Cycles delay
)
1186 DPRINTF(InOrderCPU
,"Activating next ready thread\n");
1188 scheduleCpuEvent(ActivateNextReadyThread
, NoFault
, 0/*tid*/, dummyInst
[0],
1189 delay
, ActivateNextReadyThread_Pri
);
1191 // Be sure to signal that there's some activity so the CPU doesn't
1192 // deschedule itself.
1193 activityRec
.activity();
1199 InOrderCPU::haltContext(ThreadID tid
)
1201 DPRINTF(InOrderCPU
, "[tid:%i]: Calling Halt Context...\n", tid
);
1203 scheduleCpuEvent(HaltThread
, NoFault
, tid
, dummyInst
[tid
]);
1205 activityRec
.activity();
1209 InOrderCPU::haltThread(ThreadID tid
)
1211 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Halted Threads List...\n", tid
);
1212 deactivateThread(tid
);
1213 squashThreadInPipeline(tid
);
1214 haltedThreads
.push_back(tid
);
1216 tcBase(tid
)->setStatus(ThreadContext::Halted
);
1218 if (threadModel
== SwitchOnCacheMiss
) {
1219 activateNextReadyContext();
1224 InOrderCPU::suspendContext(ThreadID tid
)
1226 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, dummyInst
[tid
]);
1230 InOrderCPU::suspendThread(ThreadID tid
)
1232 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Suspended Threads List...\n",
1234 deactivateThread(tid
);
1235 suspendedThreads
.push_back(tid
);
1236 thread
[tid
]->lastSuspend
= curTick();
1238 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1242 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
1244 //Squash all instructions in each stage
1245 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
1246 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
1251 InOrderCPU::getPipeStage(int stage_num
)
1253 return pipelineStage
[stage_num
];
1258 InOrderCPU::flattenRegIdx(RegIndex reg_idx
, RegType
®_type
, ThreadID tid
)
1260 if (reg_idx
< FP_Base_DepTag
) {
1262 return isa
[tid
]->flattenIntIndex(reg_idx
);
1263 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1264 reg_type
= FloatType
;
1265 reg_idx
-= FP_Base_DepTag
;
1266 return isa
[tid
]->flattenFloatIndex(reg_idx
);
1268 reg_type
= MiscType
;
1269 return reg_idx
- TheISA::Ctrl_Base_DepTag
;
1274 InOrderCPU::readIntReg(RegIndex reg_idx
, ThreadID tid
)
1276 DPRINTF(IntRegs
, "[tid:%i]: Reading Int. Reg %i as %x\n",
1277 tid
, reg_idx
, intRegs
[tid
][reg_idx
]);
1279 return intRegs
[tid
][reg_idx
];
1283 InOrderCPU::readFloatReg(RegIndex reg_idx
, ThreadID tid
)
1285 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1286 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1288 return floatRegs
.f
[tid
][reg_idx
];
1292 InOrderCPU::readFloatRegBits(RegIndex reg_idx
, ThreadID tid
)
1294 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1295 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1297 return floatRegs
.i
[tid
][reg_idx
];
1301 InOrderCPU::setIntReg(RegIndex reg_idx
, uint64_t val
, ThreadID tid
)
1303 if (reg_idx
== TheISA::ZeroReg
) {
1304 DPRINTF(IntRegs
, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1305 "(Int. Reg %i) to %x\n", tid
, reg_idx
, val
);
1308 DPRINTF(IntRegs
, "[tid:%i]: Setting Int. Reg %i to %x\n",
1311 intRegs
[tid
][reg_idx
] = val
;
1317 InOrderCPU::setFloatReg(RegIndex reg_idx
, FloatReg val
, ThreadID tid
)
1319 floatRegs
.f
[tid
][reg_idx
] = val
;
1320 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1323 floatRegs
.i
[tid
][reg_idx
],
1324 floatRegs
.f
[tid
][reg_idx
]);
1329 InOrderCPU::setFloatRegBits(RegIndex reg_idx
, FloatRegBits val
, ThreadID tid
)
1331 floatRegs
.i
[tid
][reg_idx
] = val
;
1332 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1335 floatRegs
.i
[tid
][reg_idx
],
1336 floatRegs
.f
[tid
][reg_idx
]);
1340 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
1342 // If Default value is set, then retrieve target thread
1343 if (tid
== InvalidThreadID
) {
1344 tid
= TheISA::getTargetThread(tcBase(tid
));
1347 if (reg_idx
< FP_Base_DepTag
) {
1348 // Integer Register File
1349 return readIntReg(reg_idx
, tid
);
1350 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1351 // Float Register File
1352 reg_idx
-= FP_Base_DepTag
;
1353 return readFloatRegBits(reg_idx
, tid
);
1355 reg_idx
-= Ctrl_Base_DepTag
;
1356 return readMiscReg(reg_idx
, tid
); // Misc. Register File
1360 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
1363 // If Default value is set, then retrieve target thread
1364 if (tid
== InvalidThreadID
) {
1365 tid
= TheISA::getTargetThread(tcBase(tid
));
1368 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
1369 setIntReg(reg_idx
, val
, tid
);
1370 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
1371 reg_idx
-= FP_Base_DepTag
;
1372 setFloatRegBits(reg_idx
, val
, tid
);
1374 reg_idx
-= Ctrl_Base_DepTag
;
1375 setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
1380 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1382 return isa
[tid
]->readMiscRegNoEffect(misc_reg
);
1386 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
1388 return isa
[tid
]->readMiscReg(misc_reg
, tcBase(tid
));
1392 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1394 isa
[tid
]->setMiscRegNoEffect(misc_reg
, val
);
1398 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1400 isa
[tid
]->setMiscReg(misc_reg
, val
, tcBase(tid
));
1405 InOrderCPU::addInst(DynInstPtr inst
)
1407 ThreadID tid
= inst
->readTid();
1409 instList
[tid
].push_back(inst
);
1411 return --(instList
[tid
].end());
1415 InOrderCPU::findInst(InstSeqNum seq_num
, ThreadID tid
)
1417 ListIt it
= instList
[tid
].begin();
1418 ListIt end
= instList
[tid
].end();
1421 if ((*it
)->seqNum
== seq_num
)
1423 else if ((*it
)->seqNum
> seq_num
)
1429 return instList
[tid
].end();
1433 InOrderCPU::updateContextSwitchStats()
1435 // Set Average Stat Here, then reset to 0
1436 instsPerCtxtSwitch
= instsPerSwitch
;
1442 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1444 // Set the nextPC to be fetched if this is the last instruction
1447 // This contributes to the precise state of the CPU
1448 // which can be used when restoring a thread to the CPU after after any
1449 // type of context switching activity (fork, exception, etc.)
1450 TheISA::PCState comm_pc
= inst
->pcState();
1451 lastCommittedPC
[tid
] = comm_pc
;
1452 TheISA::advancePC(comm_pc
, inst
->staticInst
);
1453 pcState(comm_pc
, tid
);
1455 //@todo: may be unnecessary with new-ISA-specific branch handling code
1456 if (inst
->isControl()) {
1457 thread
[tid
]->lastGradIsBranch
= true;
1458 thread
[tid
]->lastBranchPC
= inst
->pcState();
1459 TheISA::advancePC(thread
[tid
]->lastBranchPC
, inst
->staticInst
);
1461 thread
[tid
]->lastGradIsBranch
= false;
1465 // Finalize Trace Data For Instruction
1466 if (inst
->traceData
) {
1467 //inst->traceData->setCycle(curTick());
1468 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1469 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1470 inst
->traceData
->dump();
1471 delete inst
->traceData
;
1472 inst
->traceData
= NULL
;
1475 // Increment active thread's instruction count
1478 // Increment thread-state's instruction count
1479 thread
[tid
]->numInst
++;
1480 thread
[tid
]->numOp
++;
1482 // Increment thread-state's instruction stats
1483 thread
[tid
]->numInsts
++;
1484 thread
[tid
]->numOps
++;
1486 // Count committed insts per thread stats
1487 if (!inst
->isMicroop() || inst
->isLastMicroop()) {
1488 committedInsts
[tid
]++;
1490 // Count total insts committed stat
1491 totalCommittedInsts
++;
1494 committedOps
[tid
]++;
1496 // Count SMT-committed insts per thread stat
1497 if (numActiveThreads() > 1) {
1498 if (!inst
->isMicroop() || inst
->isLastMicroop())
1499 smtCommittedInsts
[tid
]++;
1502 // Instruction-Mix Stats
1503 if (inst
->isLoad()) {
1505 } else if (inst
->isStore()) {
1507 } else if (inst
->isControl()) {
1509 } else if (inst
->isNop()) {
1511 } else if (inst
->isNonSpeculative()) {
1513 } else if (inst
->isInteger()) {
1515 } else if (inst
->isFloating()) {
1519 // Check for instruction-count-based events.
1520 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numOp
);
1522 // Finally, remove instruction from CPU
1526 // currently unused function, but substitute repetitive code w/this function
1529 InOrderCPU::addToRemoveList(DynInstPtr inst
)
1531 removeInstsThisCycle
= true;
1532 if (!inst
->isRemoveList()) {
1533 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1534 "[sn:%lli] to remove list\n",
1535 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1536 inst
->setRemoveList();
1537 removeList
.push(inst
->getInstListIt());
1539 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1540 "[sn:%lli], already remove list\n",
1541 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1547 InOrderCPU::removeInst(DynInstPtr inst
)
1549 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %s "
1551 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1553 removeInstsThisCycle
= true;
1555 // Remove the instruction.
1556 if (!inst
->isRemoveList()) {
1557 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1558 "[sn:%lli] to remove list\n",
1559 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1560 inst
->setRemoveList();
1561 removeList
.push(inst
->getInstListIt());
1563 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1564 "[sn:%lli], already on remove list\n",
1565 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1571 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1573 //assert(!instList[tid].empty());
1575 removeInstsThisCycle
= true;
1577 ListIt inst_iter
= instList
[tid
].end();
1581 DPRINTF(InOrderCPU
, "Squashing instructions from CPU instruction "
1582 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1583 tid
, seq_num
, (*inst_iter
)->seqNum
);
1585 while ((*inst_iter
)->seqNum
> seq_num
) {
1587 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1589 squashInstIt(inst_iter
, tid
);
1600 InOrderCPU::squashInstIt(const ListIt inst_it
, ThreadID tid
)
1602 DynInstPtr inst
= (*inst_it
);
1603 if (inst
->threadNumber
== tid
) {
1604 DPRINTF(InOrderCPU
, "Squashing instruction, "
1605 "[tid:%i] [sn:%lli] PC %s\n",
1610 inst
->setSquashed();
1611 archRegDepMap
[tid
].remove(inst
);
1613 if (!inst
->isRemoveList()) {
1614 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1615 "[sn:%lli] to remove list\n",
1616 inst
->threadNumber
, inst
->pcState(),
1618 inst
->setRemoveList();
1619 removeList
.push(inst_it
);
1621 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i]"
1622 " PC %s [sn:%lli], already on remove list\n",
1623 inst
->threadNumber
, inst
->pcState(),
1633 InOrderCPU::cleanUpRemovedInsts()
1635 while (!removeList
.empty()) {
1636 DPRINTF(InOrderCPU
, "Removing instruction, "
1637 "[tid:%i] [sn:%lli] PC %s\n",
1638 (*removeList
.front())->threadNumber
,
1639 (*removeList
.front())->seqNum
,
1640 (*removeList
.front())->pcState());
1642 DynInstPtr inst
= *removeList
.front();
1643 ThreadID tid
= inst
->threadNumber
;
1645 // Remove From Register Dependency Map, If Necessary
1646 // archRegDepMap[tid].remove(inst);
1648 // Clear if Non-Speculative
1649 if (inst
->staticInst
&&
1650 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1651 nonSpecInstActive
[tid
] == true) {
1652 nonSpecInstActive
[tid
] = false;
1655 inst
->onInstList
= false;
1657 instList
[tid
].erase(removeList
.front());
1662 removeInstsThisCycle
= false;
1666 InOrderCPU::cleanUpRemovedEvents()
1668 while (!cpuEventRemoveList
.empty()) {
1669 Event
*cpu_event
= cpuEventRemoveList
.front();
1670 cpuEventRemoveList
.pop();
1677 InOrderCPU::dumpInsts()
1681 ListIt inst_list_it
= instList
[0].begin();
1683 cprintf("Dumping Instruction List\n");
1685 while (inst_list_it
!= instList
[0].end()) {
1686 cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1688 num
, (*inst_list_it
)->pcState(),
1689 (*inst_list_it
)->threadNumber
,
1690 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1691 (*inst_list_it
)->isSquashed());
1698 InOrderCPU::wakeCPU()
1700 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1701 DPRINTF(Activity
, "CPU already running.\n");
1705 DPRINTF(Activity
, "Waking up CPU\n");
1707 Tick extra_cycles
= curCycle() - lastRunningCycle
;
1708 if (extra_cycles
!= 0)
1711 idleCycles
+= extra_cycles
;
1712 for (int stage_num
= 0; stage_num
< NumStages
; stage_num
++) {
1713 pipelineStage
[stage_num
]->idleCycles
+= extra_cycles
;
1716 numCycles
+= extra_cycles
;
1718 schedule(&tickEvent
, clockEdge());
1721 // Lots of copied full system code...place into BaseCPU class?
1723 InOrderCPU::wakeup()
1725 if (thread
[0]->status() != ThreadContext::Suspended
)
1730 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1731 threadContexts
[0]->activate();
1735 InOrderCPU::syscallContext(Fault fault
, ThreadID tid
, DynInstPtr inst
,
1738 // Syscall must be non-speculative, so squash from last stage
1739 unsigned squash_stage
= NumStages
- 1;
1740 inst
->setSquashInfo(squash_stage
);
1742 // Squash In Pipeline Stage
1743 pipelineStage
[squash_stage
]->setupSquash(inst
, tid
);
1745 // Schedule Squash Through-out Resource Pool
1746 resPool
->scheduleEvent(
1747 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
, inst
,
1749 scheduleCpuEvent(Syscall
, fault
, tid
, inst
, delay
, Syscall_Pri
);
1753 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1755 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1757 DPRINTF(Activity
,"Activity: syscall() called.\n");
1759 // Temporarily increase this by one to account for the syscall
1761 ++(this->thread
[tid
]->funcExeInst
);
1763 // Execute the actual syscall.
1764 this->thread
[tid
]->syscall(callnum
);
1766 // Decrease funcExeInst by one as the normal commit will handle
1768 --(this->thread
[tid
]->funcExeInst
);
1770 // Clear Non-Speculative Block Variable
1771 nonSpecInstActive
[tid
] = false;
1775 InOrderCPU::getITBPtr()
1777 CacheUnit
*itb_res
= resPool
->getInstUnit();
1778 return itb_res
->tlb();
1783 InOrderCPU::getDTBPtr()
1785 return resPool
->getDataUnit()->tlb();
1789 InOrderCPU::getDecoderPtr(unsigned tid
)
1791 return resPool
->getInstUnit()->decoder
[tid
];
1795 InOrderCPU::read(DynInstPtr inst
, Addr addr
,
1796 uint8_t *data
, unsigned size
, unsigned flags
)
1798 return resPool
->getDataUnit()->read(inst
, addr
, data
, size
, flags
);
1802 InOrderCPU::write(DynInstPtr inst
, uint8_t *data
, unsigned size
,
1803 Addr addr
, unsigned flags
, uint64_t *write_res
)
1805 return resPool
->getDataUnit()->write(inst
, data
, size
, addr
, flags
,