src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <algorithm>
  33
  34 #include "arch/utility.hh"
  35 #include "config/full_system.hh"
  36 #include "config/the_isa.hh"
  37 #include "cpu/activity.hh"
  38 #include "cpu/base.hh"
  39 #include "cpu/exetrace.hh"
  40 #include "cpu/inorder/cpu.hh"
  41 #include "cpu/inorder/first_stage.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource_pool.hh"
  45 #include "cpu/inorder/resources/resource_list.hh"
  46 #include "cpu/inorder/thread_context.hh"
  47 #include "cpu/inorder/thread_state.hh"
  48 #include "cpu/simple_thread.hh"
  49 #include "cpu/thread_context.hh"
  50 #include "mem/translating_port.hh"
  51 #include "params/InOrderCPU.hh"
  52 #include "sim/process.hh"
  53 #include "sim/stat_control.hh"
  54
  55 #if FULL_SYSTEM
  56 #include "cpu/quiesce_event.hh"
  57 #include "sim/system.hh"
  58 #endif
  59
  60 #if THE_ISA == ALPHA_ISA
  61 #include "arch/alpha/osfpal.hh"
  62 #endif
  63
  64 using namespace std;
  65 using namespace TheISA;
  66 using namespace ThePipeline;
  67
  68 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
  69   : Event(CPU_Tick_Pri), cpu(c)
  70 { }
  71
  72
  73 void
  74 InOrderCPU::TickEvent::process()
  75 {
  76     cpu->tick();
  77 }
  78
  79
  80 const char *
  81 InOrderCPU::TickEvent::description()
  82 {
  83     return "InOrderCPU tick event";
  84 }
  85
  86 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
  87                                Fault fault, ThreadID _tid, DynInstPtr inst,
  88                                unsigned event_pri_offset)
  89     : Event(Event::Priority((unsigned int)CPU_Tick_Pri + event_pri_offset)),
  90       cpu(_cpu)
  91 {
  92     setEvent(e_type, fault, _tid, inst);
  93 }
  94
  95
  96 std::string InOrderCPU::eventNames[NumCPUEvents] =
  97 {
  98     "ActivateThread",
  99     "ActivateNextReadyThread",
 100     "DeactivateThread",
 101     "HaltThread",
 102     "SuspendThread",
 103     "Trap",
 104     "InstGraduated",
 105     "SquashFromMemStall",
 106     "UpdatePCs"
 107 };
 108
 109 void
 110 InOrderCPU::CPUEvent::process()
 111 {
 112     switch (cpuEventType)
 113     {
 114       case ActivateThread:
 115         cpu->activateThread(tid);
 116         break;
 117
 118       case ActivateNextReadyThread:
 119         cpu->activateNextReadyThread();
 120         break;
 121
 122       case DeactivateThread:
 123         cpu->deactivateThread(tid);
 124         break;
 125
 126       case HaltThread:
 127         cpu->haltThread(tid);
 128         break;
 129
 130       case SuspendThread:
 131         cpu->suspendThread(tid);
 132         break;
 133
 134       case SquashFromMemStall:
 135         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 136         break;
 137
 138       case Trap:
 139         cpu->trapCPU(fault, tid);
 140         break;
 141
 142       default:
 143         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 144     }
 145
 146     cpu->cpuEventRemoveList.push(this);
 147 }
 148
 149
 150
 151 const char *
 152 InOrderCPU::CPUEvent::description()
 153 {
 154     return "InOrderCPU event";
 155 }
 156
 157 void
 158 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 159 {
 160     if (squashed())
 161       mainEventQueue.reschedule(this,curTick + cpu->ticks(delay));
 162     else if (!scheduled())
 163       mainEventQueue.schedule(this,curTick + cpu->ticks(delay));
 164 }
 165
 166 void
 167 InOrderCPU::CPUEvent::unscheduleEvent()
 168 {
 169     if (scheduled())
 170         squash();
 171 }
 172
 173 InOrderCPU::InOrderCPU(Params *params)
 174     : BaseCPU(params),
 175       cpu_id(params->cpu_id),
 176       coreType("default"),
 177       _status(Idle),
 178       tickEvent(this),
 179       timeBuffer(2 , 2),
 180       removeInstsThisCycle(false),
 181       activityRec(params->name, NumStages, 10, params->activity),
 182 #if FULL_SYSTEM
 183       system(params->system),
 184       physmem(system->physmem),
 185 #endif // FULL_SYSTEM
 186 #ifdef DEBUG
 187       cpuEventNum(0),
 188       resReqCount(0),
 189 #endif // DEBUG
 190       switchCount(0),
 191       deferRegistration(false/*params->deferRegistration*/),
 192       stageTracing(params->stageTracing),
 193       instsPerSwitch(0)
 194 {
 195     ThreadID active_threads;
 196     cpu_params = params;
 197
 198     resPool = new ResourcePool(this, params);
 199
 200     // Resize for Multithreading CPUs
 201     thread.resize(numThreads);
 202
 203 #if FULL_SYSTEM
 204     active_threads = 1;
 205 #else
 206     active_threads = params->workload.size();
 207
 208     if (active_threads > MaxThreads) {
 209         panic("Workload Size too large. Increase the 'MaxThreads'"
 210               "in your InOrder implementation or "
 211               "edit your workload size.");
 212     }
 213
 214
 215     if (active_threads > 1) {
 216         threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 217
 218         if (threadModel == SMT) {
 219             DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 220         } else if (threadModel == SwitchOnCacheMiss) {
 221             DPRINTF(InOrderCPU, "Setting Thread Model to "
 222                     "Switch On Cache Miss\n");
 223         }
 224
 225     } else {
 226         threadModel = Single;
 227     }
 228
 229
 230
 231 #endif
 232
 233     // Bind the fetch & data ports from the resource pool.
 234     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
 235     if (fetchPortIdx == 0) {
 236         fatal("Unable to find port to fetch instructions from.\n");
 237     }
 238
 239     dataPortIdx = resPool->getPortIdx(params->dataMemPort);
 240     if (dataPortIdx == 0) {
 241         fatal("Unable to find port for data.\n");
 242     }
 243
 244     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 245 #if FULL_SYSTEM
 246         // SMT is not supported in FS mode yet.
 247         assert(numThreads == 1);
 248         thread[tid] = new Thread(this, 0);
 249 #else
 250         if (tid < (ThreadID)params->workload.size()) {
 251             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 252                     tid, params->workload[tid]->prog_fname);
 253             thread[tid] =
 254                 new Thread(this, tid, params->workload[tid]);
 255         } else {
 256             //Allocate Empty thread so M5 can use later
 257             //when scheduling threads to CPU
 258             Process* dummy_proc = params->workload[0];
 259             thread[tid] = new Thread(this, tid, dummy_proc);
 260         }
 261
 262         // Eventually set this with parameters...
 263         asid[tid] = tid;
 264 #endif
 265
 266         // Setup the TC that will serve as the interface to the threads/CPU.
 267         InOrderThreadContext *tc = new InOrderThreadContext;
 268         tc->cpu = this;
 269         tc->thread = thread[tid];
 270
 271         // Give the thread the TC.
 272         thread[tid]->tc = tc;
 273         thread[tid]->setFuncExeInst(0);
 274         globalSeqNum[tid] = 1;
 275
 276         // Add the TC to the CPU's list of TC's.
 277         this->threadContexts.push_back(tc);
 278     }
 279
 280     // Initialize TimeBuffer Stage Queues
 281     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 282         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 283         stageQueue[stNum]->id(stNum);
 284     }
 285
 286
 287     // Set Up Pipeline Stages
 288     for (int stNum=0; stNum < NumStages; stNum++) {
 289         if (stNum == 0)
 290             pipelineStage[stNum] = new FirstStage(params, stNum);
 291         else
 292             pipelineStage[stNum] = new PipelineStage(params, stNum);
 293
 294         pipelineStage[stNum]->setCPU(this);
 295         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 296         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 297
 298         // Take Care of 1st/Nth stages
 299         if (stNum > 0)
 300             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 301         if (stNum < NumStages - 1)
 302             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 303     }
 304
 305     // Initialize thread specific variables
 306     for (ThreadID tid = 0; tid < numThreads; tid++) {
 307         archRegDepMap[tid].setCPU(this);
 308
 309         nonSpecInstActive[tid] = false;
 310         nonSpecSeqNum[tid] = 0;
 311
 312         squashSeqNum[tid] = MaxAddr;
 313         lastSquashCycle[tid] = 0;
 314
 315         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 316         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 317         isa[tid].clear();
 318
 319         isa[tid].expandForMultithreading(numThreads, 1/*numVirtProcs*/);
 320
 321         // Define dummy instructions and resource requests to be used.
 322         dummyInst[tid] = new InOrderDynInst(this,
 323                                             thread[tid],
 324                                             0,
 325                                             tid,
 326                                             asid[tid]);
 327
 328         dummyReq[tid] = new ResourceRequest(resPool->getResource(0),
 329                                             dummyInst[tid],
 330                                             0,
 331                                             0,
 332                                             0,
 333                                             0);
 334     }
 335
 336     lastRunningCycle = curTick;
 337
 338     // Reset CPU to reset state.
 339 #if FULL_SYSTEM
 340     Fault resetFault = new ResetFault();
 341     resetFault->invoke(tcBase());
 342 #else
 343     reset();
 344 #endif
 345
 346     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 347     scheduleTickEvent(0);
 348 }
 349
 350 InOrderCPU::~InOrderCPU()
 351 {
 352     delete resPool;
 353 }
 354
 355
 356 void
 357 InOrderCPU::regStats()
 358 {
 359     /* Register the Resource Pool's stats here.*/
 360     resPool->regStats();
 361
 362 #ifdef DEBUG
 363     maxResReqCount
 364         .name(name() + ".maxResReqCount")
 365         .desc("Maximum number of live resource requests in CPU")
 366         .prereq(maxResReqCount);
 367 #endif
 368
 369     /* Register for each Pipeline Stage */
 370     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 371         pipelineStage[stage_num]->regStats();
 372     }
 373
 374     /* Register any of the InOrderCPU's stats here.*/
 375     instsPerCtxtSwitch
 376         .name(name() + ".instsPerContextSwitch")
 377         .desc("Instructions Committed Per Context Switch")
 378         .prereq(instsPerCtxtSwitch);
 379
 380     numCtxtSwitches
 381         .name(name() + ".contextSwitches")
 382         .desc("Number of context switches");
 383
 384     timesIdled
 385         .name(name() + ".timesIdled")
 386         .desc("Number of times that the entire CPU went into an idle state and"
 387               " unscheduled itself")
 388         .prereq(timesIdled);
 389
 390     idleCycles
 391         .name(name() + ".idleCycles")
 392         .desc("Number of cycles cpu's stages were not processed");
 393
 394     runCycles
 395         .name(name() + ".runCycles")
 396         .desc("Number of cycles cpu stages are processed.");
 397
 398     activity
 399         .name(name() + ".activity")
 400         .desc("Percentage of cycles cpu is active")
 401         .precision(6);
 402     activity = (runCycles / numCycles) * 100;
 403
 404     threadCycles
 405         .init(numThreads)
 406         .name(name() + ".threadCycles")
 407         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 408
 409     smtCycles
 410         .name(name() + ".smtCycles")
 411         .desc("Total number of cycles that the CPU was in SMT-mode");
 412
 413     committedInsts
 414         .init(numThreads)
 415         .name(name() + ".committedInsts")
 416         .desc("Number of Instructions Simulated (Per-Thread)");
 417
 418     smtCommittedInsts
 419         .init(numThreads)
 420         .name(name() + ".smtCommittedInsts")
 421         .desc("Number of SMT Instructions Simulated (Per-Thread)");
 422
 423     totalCommittedInsts
 424         .name(name() + ".committedInsts_total")
 425         .desc("Number of Instructions Simulated (Total)");
 426
 427     cpi
 428         .name(name() + ".cpi")
 429         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 430         .precision(6);
 431     cpi = threadCycles / committedInsts;
 432
 433     smtCpi
 434         .name(name() + ".smt_cpi")
 435         .desc("CPI: Total SMT-CPI")
 436         .precision(6);
 437     smtCpi = smtCycles / smtCommittedInsts;
 438
 439     totalCpi
 440         .name(name() + ".cpi_total")
 441         .desc("CPI: Total CPI of All Threads")
 442         .precision(6);
 443     totalCpi = numCycles / totalCommittedInsts;
 444
 445     ipc
 446         .name(name() + ".ipc")
 447         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 448         .precision(6);
 449     ipc =  committedInsts / threadCycles;
 450
 451     smtIpc
 452         .name(name() + ".smt_ipc")
 453         .desc("IPC: Total SMT-IPC")
 454         .precision(6);
 455     smtIpc = smtCommittedInsts / smtCycles;
 456
 457     totalIpc
 458         .name(name() + ".ipc_total")
 459         .desc("IPC: Total IPC of All Threads")
 460         .precision(6);
 461         totalIpc =  totalCommittedInsts / numCycles;
 462
 463     BaseCPU::regStats();
 464 }
 465
 466
 467 void
 468 InOrderCPU::tick()
 469 {
 470     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 471
 472     ++numCycles;
 473
 474     bool pipes_idle = true;
 475
 476     //Tick each of the stages
 477     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 478         pipelineStage[stNum]->tick();
 479
 480         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 481     }
 482
 483     if (pipes_idle)
 484         idleCycles++;
 485     else
 486         runCycles++;
 487
 488     // Now advance the time buffers one tick
 489     timeBuffer.advance();
 490     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 491         stageQueue[sqNum]->advance();
 492     }
 493     activityRec.advance();
 494
 495     // Any squashed requests, events, or insts then remove them now
 496     cleanUpRemovedReqs();
 497     cleanUpRemovedEvents();
 498     cleanUpRemovedInsts();
 499
 500     // Re-schedule CPU for this cycle
 501     if (!tickEvent.scheduled()) {
 502         if (_status == SwitchedOut) {
 503             // increment stat
 504             lastRunningCycle = curTick;
 505         } else if (!activityRec.active()) {
 506             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 507             lastRunningCycle = curTick;
 508             timesIdled++;
 509         } else {
 510             //Tick next_tick = curTick + cycles(1);
 511             //tickEvent.schedule(next_tick);
 512             mainEventQueue.schedule(&tickEvent, nextCycle(curTick + 1));
 513             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 514                     nextCycle(curTick + 1));
 515         }
 516     }
 517
 518     tickThreadStats();
 519     updateThreadPriority();
 520 }
 521
 522
 523 void
 524 InOrderCPU::init()
 525 {
 526     if (!deferRegistration) {
 527         registerThreadContexts();
 528     }
 529
 530     // Set inSyscall so that the CPU doesn't squash when initially
 531     // setting up registers.
 532     for (ThreadID tid = 0; tid < numThreads; ++tid)
 533         thread[tid]->inSyscall = true;
 534
 535 #if FULL_SYSTEM
 536     for (ThreadID tid = 0; tid < numThreads; tid++) {
 537         ThreadContext *src_tc = threadContexts[tid];
 538         TheISA::initCPU(src_tc, src_tc->contextId());
 539     }
 540 #endif
 541
 542     // Clear inSyscall.
 543     for (ThreadID tid = 0; tid < numThreads; ++tid)
 544         thread[tid]->inSyscall = false;
 545
 546     // Call Initializiation Routine for Resource Pool
 547     resPool->init();
 548 }
 549
 550 void
 551 InOrderCPU::reset()
 552 {
 553     for (int i = 0; i < numThreads; i++) {
 554         isa[i].reset(coreType, numThreads,
 555                      1/*numVirtProcs*/, dynamic_cast<BaseCPU*>(this));
 556     }
 557 }
 558
 559 Port*
 560 InOrderCPU::getPort(const std::string &if_name, int idx)
 561 {
 562     return resPool->getPort(if_name, idx);
 563 }
 564
 565 #if FULL_SYSTEM
 566 Fault
 567 InOrderCPU::hwrei(ThreadID tid)
 568 {
 569     panic("hwrei: Unimplemented");
 570
 571     return NoFault;
 572 }
 573
 574
 575 bool
 576 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 577 {
 578     panic("simPalCheck: Unimplemented");
 579
 580     return true;
 581 }
 582
 583
 584 Fault
 585 InOrderCPU::getInterrupts()
 586 {
 587     // Check if there are any outstanding interrupts
 588     return this->interrupts->getInterrupt(this->threadContexts[0]);
 589 }
 590
 591
 592 void
 593 InOrderCPU::processInterrupts(Fault interrupt)
 594 {
 595     // Check for interrupts here.  For now can copy the code that
 596     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 597     // is the one that handles the interrupts.
 598     // @todo: Possibly consolidate the interrupt checking code.
 599     // @todo: Allow other threads to handle interrupts.
 600
 601     assert(interrupt != NoFault);
 602     this->interrupts->updateIntrInfo(this->threadContexts[0]);
 603
 604     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 605     this->trap(interrupt, 0);
 606 }
 607
 608
 609 void
 610 InOrderCPU::updateMemPorts()
 611 {
 612     // Update all ThreadContext's memory ports (Functional/Virtual
 613     // Ports)
 614     ThreadID size = thread.size();
 615     for (ThreadID i = 0; i < size; ++i)
 616         thread[i]->connectMemPorts(thread[i]->getTC());
 617 }
 618 #endif
 619
 620 void
 621 InOrderCPU::trap(Fault fault, ThreadID tid, int delay)
 622 {
 623     //@ Squash Pipeline during TRAP
 624     scheduleCpuEvent(Trap, fault, tid, dummyInst[tid], delay);
 625 }
 626
 627 void
 628 InOrderCPU::trapCPU(Fault fault, ThreadID tid)
 629 {
 630     fault->invoke(tcBase(tid));
 631 }
 632
 633 void
 634 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 635 {
 636     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 637 }
 638
 639
 640 void
 641 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid)
 642 {
 643     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 644
 645     // Squash all instructions in each stage including
 646     // instruction that caused the squash (seq_num - 1)
 647     // NOTE: The stage bandwidth needs to be cleared so thats why
 648     //       the stalling instruction is squashed as well. The stalled
 649     //       instruction is previously placed in another intermediate buffer
 650     //       while it's stall is being handled.
 651     InstSeqNum squash_seq_num = seq_num - 1;
 652
 653     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 654         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 655     }
 656 }
 657
 658 void
 659 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 660                              ThreadID tid, DynInstPtr inst,
 661                              unsigned delay, unsigned event_pri_offset)
 662 {
 663     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 664                                        event_pri_offset);
 665
 666     if (delay >= 0) {
 667         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 668                 eventNames[c_event], curTick + delay, tid);
 669         mainEventQueue.schedule(cpu_event,curTick + delay);
 670     } else {
 671         cpu_event->process();
 672         cpuEventRemoveList.push(cpu_event);
 673     }
 674
 675     // Broadcast event to the Resource Pool
 676     // Need to reset tid just in case this is a dummy instruction
 677     inst->setTid(tid);
 678     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 679 }
 680
 681 bool
 682 InOrderCPU::isThreadActive(ThreadID tid)
 683 {
 684   list<ThreadID>::iterator isActive =
 685       std::find(activeThreads.begin(), activeThreads.end(), tid);
 686
 687     return (isActive != activeThreads.end());
 688 }
 689
 690 bool
 691 InOrderCPU::isThreadReady(ThreadID tid)
 692 {
 693   list<ThreadID>::iterator isReady =
 694       std::find(readyThreads.begin(), readyThreads.end(), tid);
 695
 696     return (isReady != readyThreads.end());
 697 }
 698
 699 bool
 700 InOrderCPU::isThreadSuspended(ThreadID tid)
 701 {
 702   list<ThreadID>::iterator isSuspended =
 703       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
 704
 705     return (isSuspended != suspendedThreads.end());
 706 }
 707
 708 void
 709 InOrderCPU::activateNextReadyThread()
 710 {
 711     if (readyThreads.size() >= 1) {
 712         ThreadID ready_tid = readyThreads.front();
 713
 714         // Activate in Pipeline
 715         activateThread(ready_tid);
 716
 717         // Activate in Resource Pool
 718         resPool->activateAll(ready_tid);
 719
 720         list<ThreadID>::iterator ready_it =
 721             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
 722         readyThreads.erase(ready_it);
 723     } else {
 724         DPRINTF(InOrderCPU,
 725                 "Attempting to activate new thread, but No Ready Threads to"
 726                 "activate.\n");
 727         DPRINTF(InOrderCPU,
 728                 "Unable to switch to next active thread.\n");
 729     }
 730 }
 731
 732 void
 733 InOrderCPU::activateThread(ThreadID tid)
 734 {
 735     if (isThreadSuspended(tid)) {
 736         DPRINTF(InOrderCPU,
 737                 "Removing [tid:%i] from suspended threads list.\n", tid);
 738
 739         list<ThreadID>::iterator susp_it =
 740             std::find(suspendedThreads.begin(), suspendedThreads.end(),
 741                       tid);
 742         suspendedThreads.erase(susp_it);
 743     }
 744
 745     if (threadModel == SwitchOnCacheMiss &&
 746         numActiveThreads() == 1) {
 747         DPRINTF(InOrderCPU,
 748                 "Ignoring activation of [tid:%i], since [tid:%i] is "
 749                 "already running.\n", tid, activeThreadId());
 750
 751         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
 752                 tid);
 753
 754         readyThreads.push_back(tid);
 755
 756     } else if (!isThreadActive(tid)) {
 757         DPRINTF(InOrderCPU,
 758                 "Adding [tid:%i] to active threads list.\n", tid);
 759         activeThreads.push_back(tid);
 760
 761         activateThreadInPipeline(tid);
 762
 763         thread[tid]->lastActivate = curTick;
 764
 765         tcBase(tid)->setStatus(ThreadContext::Active);
 766
 767         wakeCPU();
 768
 769         numCtxtSwitches++;
 770     }
 771 }
 772
 773 void
 774 InOrderCPU::activateThreadInPipeline(ThreadID tid)
 775 {
 776     for (int stNum=0; stNum < NumStages; stNum++) {
 777         pipelineStage[stNum]->activateThread(tid);
 778     }
 779 }
 780
 781 void
 782 InOrderCPU::deactivateContext(ThreadID tid, int delay)
 783 {
 784     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
 785
 786     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
 787
 788     // Be sure to signal that there's some activity so the CPU doesn't
 789     // deschedule itself.
 790     activityRec.activity();
 791
 792     _status = Running;
 793 }
 794
 795 void
 796 InOrderCPU::deactivateThread(ThreadID tid)
 797 {
 798     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
 799
 800     if (isThreadActive(tid)) {
 801         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
 802                 tid);
 803         list<ThreadID>::iterator thread_it =
 804             std::find(activeThreads.begin(), activeThreads.end(), tid);
 805
 806         removePipelineStalls(*thread_it);
 807
 808         activeThreads.erase(thread_it);
 809
 810         // Ideally, this should be triggered from the
 811         // suspendContext/Thread functions
 812         tcBase(tid)->setStatus(ThreadContext::Suspended);
 813     }
 814
 815     assert(!isThreadActive(tid));
 816 }
 817
 818 void
 819 InOrderCPU::removePipelineStalls(ThreadID tid)
 820 {
 821     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
 822             tid);
 823
 824     for (int stNum = 0; stNum < NumStages ; stNum++) {
 825         pipelineStage[stNum]->removeStalls(tid);
 826     }
 827
 828 }
 829
 830 void
 831 InOrderCPU::updateThreadPriority()
 832 {
 833     if (activeThreads.size() > 1)
 834     {
 835         //DEFAULT TO ROUND ROBIN SCHEME
 836         //e.g. Move highest priority to end of thread list
 837         list<ThreadID>::iterator list_begin = activeThreads.begin();
 838         list<ThreadID>::iterator list_end   = activeThreads.end();
 839
 840         unsigned high_thread = *list_begin;
 841
 842         activeThreads.erase(list_begin);
 843
 844         activeThreads.push_back(high_thread);
 845     }
 846 }
 847
 848 inline void
 849 InOrderCPU::tickThreadStats()
 850 {
 851     /** Keep track of cycles that each thread is active */
 852     list<ThreadID>::iterator thread_it = activeThreads.begin();
 853     while (thread_it != activeThreads.end()) {
 854         threadCycles[*thread_it]++;
 855         thread_it++;
 856     }
 857
 858     // Keep track of cycles where SMT is active
 859     if (activeThreads.size() > 1) {
 860         smtCycles++;
 861     }
 862 }
 863
 864 void
 865 InOrderCPU::activateContext(ThreadID tid, int delay)
 866 {
 867     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
 868
 869
 870     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
 871
 872     // Be sure to signal that there's some activity so the CPU doesn't
 873     // deschedule itself.
 874     activityRec.activity();
 875
 876     _status = Running;
 877 }
 878
 879 void
 880 InOrderCPU::activateNextReadyContext(int delay)
 881 {
 882     DPRINTF(InOrderCPU,"Activating next ready thread\n");
 883
 884     // NOTE: Add 5 to the event priority so that we always activate
 885     // threads after we've finished deactivating, squashing,etc.
 886     // other threads
 887     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
 888                      delay, 5);
 889
 890     // Be sure to signal that there's some activity so the CPU doesn't
 891     // deschedule itself.
 892     activityRec.activity();
 893
 894     _status = Running;
 895 }
 896
 897 void
 898 InOrderCPU::haltContext(ThreadID tid, int delay)
 899 {
 900     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
 901
 902     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
 903
 904     activityRec.activity();
 905 }
 906
 907 void
 908 InOrderCPU::haltThread(ThreadID tid)
 909 {
 910     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
 911     deactivateThread(tid);
 912     squashThreadInPipeline(tid);
 913     haltedThreads.push_back(tid);
 914
 915     tcBase(tid)->setStatus(ThreadContext::Halted);
 916
 917     if (threadModel == SwitchOnCacheMiss) {
 918         activateNextReadyContext();
 919     }
 920 }
 921
 922 void
 923 InOrderCPU::suspendContext(ThreadID tid, int delay)
 924 {
 925     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
 926 }
 927
 928 void
 929 InOrderCPU::suspendThread(ThreadID tid)
 930 {
 931     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n", tid);
 932     deactivateThread(tid);
 933     suspendedThreads.push_back(tid);
 934     thread[tid]->lastSuspend = curTick;
 935
 936     tcBase(tid)->setStatus(ThreadContext::Suspended);
 937 }
 938
 939 void
 940 InOrderCPU::squashThreadInPipeline(ThreadID tid)
 941 {
 942     //Squash all instructions in each stage
 943     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 944         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
 945     }
 946 }
 947
 948 PipelineStage*
 949 InOrderCPU::getPipeStage(int stage_num)
 950 {
 951     return pipelineStage[stage_num];
 952 }
 953
 954 uint64_t
 955 InOrderCPU::readPC(ThreadID tid)
 956 {
 957     return PC[tid];
 958 }
 959
 960
 961 void
 962 InOrderCPU::setPC(Addr new_PC, ThreadID tid)
 963 {
 964     PC[tid] = new_PC;
 965 }
 966
 967
 968 uint64_t
 969 InOrderCPU::readNextPC(ThreadID tid)
 970 {
 971     return nextPC[tid];
 972 }
 973
 974
 975 void
 976 InOrderCPU::setNextPC(uint64_t new_NPC, ThreadID tid)
 977 {
 978     nextPC[tid] = new_NPC;
 979 }
 980
 981
 982 uint64_t
 983 InOrderCPU::readNextNPC(ThreadID tid)
 984 {
 985     return nextNPC[tid];
 986 }
 987
 988
 989 void
 990 InOrderCPU::setNextNPC(uint64_t new_NNPC, ThreadID tid)
 991 {
 992     nextNPC[tid] = new_NNPC;
 993 }
 994
 995 uint64_t
 996 InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
 997 {
 998     return intRegs[tid][reg_idx];
 999 }
1000
1001 FloatReg
1002 InOrderCPU::readFloatReg(int reg_idx, ThreadID tid)
1003 {
1004     return floatRegs.f[tid][reg_idx];
1005 }
1006
1007 FloatRegBits
1008 InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
1009 {;
1010     return floatRegs.i[tid][reg_idx];
1011 }
1012
1013 void
1014 InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
1015 {
1016     intRegs[tid][reg_idx] = val;
1017 }
1018
1019
1020 void
1021 InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid)
1022 {
1023     floatRegs.f[tid][reg_idx] = val;
1024 }
1025
1026
1027 void
1028 InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid)
1029 {
1030     floatRegs.i[tid][reg_idx] = val;
1031 }
1032
1033 uint64_t
1034 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1035 {
1036     // If Default value is set, then retrieve target thread
1037     if (tid == InvalidThreadID) {
1038         tid = TheISA::getTargetThread(tcBase(tid));
1039     }
1040
1041     if (reg_idx < FP_Base_DepTag) {
1042         // Integer Register File
1043         return readIntReg(reg_idx, tid);
1044     } else if (reg_idx < Ctrl_Base_DepTag) {
1045         // Float Register File
1046         reg_idx -= FP_Base_DepTag;
1047         return readFloatRegBits(reg_idx, tid);
1048     } else {
1049         reg_idx -= Ctrl_Base_DepTag;
1050         return readMiscReg(reg_idx, tid);  // Misc. Register File
1051     }
1052 }
1053 void
1054 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1055                               ThreadID tid)
1056 {
1057     // If Default value is set, then retrieve target thread
1058     if (tid == InvalidThreadID) {
1059         tid = TheISA::getTargetThread(tcBase(tid));
1060     }
1061
1062     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1063         setIntReg(reg_idx, val, tid);
1064     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1065         reg_idx -= FP_Base_DepTag;
1066         setFloatRegBits(reg_idx, val, tid);
1067     } else {
1068         reg_idx -= Ctrl_Base_DepTag;
1069         setMiscReg(reg_idx, val, tid); // Misc. Register File
1070     }
1071 }
1072
1073 MiscReg
1074 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1075 {
1076     return isa[tid].readMiscRegNoEffect(misc_reg);
1077 }
1078
1079 MiscReg
1080 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1081 {
1082     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1083 }
1084
1085 void
1086 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1087 {
1088     isa[tid].setMiscRegNoEffect(misc_reg, val);
1089 }
1090
1091 void
1092 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1093 {
1094     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1095 }
1096
1097
1098 InOrderCPU::ListIt
1099 InOrderCPU::addInst(DynInstPtr &inst)
1100 {
1101     ThreadID tid = inst->readTid();
1102
1103     instList[tid].push_back(inst);
1104
1105     return --(instList[tid].end());
1106 }
1107
1108 void
1109 InOrderCPU::updateContextSwitchStats()
1110 {
1111     // Set Average Stat Here, then reset to 0
1112     instsPerCtxtSwitch = instsPerSwitch;
1113     instsPerSwitch = 0;
1114 }
1115
1116
1117 void
1118 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1119 {
1120     // Set the CPU's PCs - This contributes to the precise state of the CPU
1121     // which can be used when restoring a thread to the CPU after after any
1122     // type of context switching activity (fork, exception, etc.)
1123     setPC(inst->readPC(), tid);
1124     setNextPC(inst->readNextPC(), tid);
1125     setNextNPC(inst->readNextNPC(), tid);
1126
1127     if (inst->isControl()) {
1128         thread[tid]->lastGradIsBranch = true;
1129         thread[tid]->lastBranchPC = inst->readPC();
1130         thread[tid]->lastBranchNextPC = inst->readNextPC();
1131         thread[tid]->lastBranchNextNPC = inst->readNextNPC();
1132     } else {
1133         thread[tid]->lastGradIsBranch = false;
1134     }
1135
1136
1137     // Finalize Trace Data For Instruction
1138     if (inst->traceData) {
1139         //inst->traceData->setCycle(curTick);
1140         inst->traceData->setFetchSeq(inst->seqNum);
1141         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1142         inst->traceData->dump();
1143         delete inst->traceData;
1144         inst->traceData = NULL;
1145     }
1146
1147     // Increment active thread's instruction count
1148     instsPerSwitch++;
1149
1150     // Increment thread-state's instruction count
1151     thread[tid]->numInst++;
1152
1153     // Increment thread-state's instruction stats
1154     thread[tid]->numInsts++;
1155
1156     // Count committed insts per thread stats
1157     committedInsts[tid]++;
1158
1159     // Count total insts committed stat
1160     totalCommittedInsts++;
1161
1162     // Count SMT-committed insts per thread stat
1163     if (numActiveThreads() > 1) {
1164         smtCommittedInsts[tid]++;
1165     }
1166
1167     // Check for instruction-count-based events.
1168     comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1169
1170     // Broadcast to other resources an instruction
1171     // has been completed
1172     resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
1173                            0, 0, tid);
1174
1175     // Finally, remove instruction from CPU
1176     removeInst(inst);
1177 }
1178
1179 void
1180 InOrderCPU::addToRemoveList(DynInstPtr &inst)
1181 {
1182     removeInstsThisCycle = true;
1183
1184     removeList.push(inst->getInstListIt());
1185 }
1186
1187 void
1188 InOrderCPU::removeInst(DynInstPtr &inst)
1189 {
1190     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %#x "
1191             "[sn:%lli]\n",
1192             inst->threadNumber, inst->readPC(), inst->seqNum);
1193
1194     removeInstsThisCycle = true;
1195
1196     // Remove the instruction.
1197     removeList.push(inst->getInstListIt());
1198 }
1199
1200 void
1201 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1202 {
1203     //assert(!instList[tid].empty());
1204
1205     removeInstsThisCycle = true;
1206
1207     ListIt inst_iter = instList[tid].end();
1208
1209     inst_iter--;
1210
1211     DPRINTF(InOrderCPU, "Deleting instructions from CPU instruction "
1212             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1213             tid, seq_num, (*inst_iter)->seqNum);
1214
1215     while ((*inst_iter)->seqNum > seq_num) {
1216
1217         bool break_loop = (inst_iter == instList[tid].begin());
1218
1219         squashInstIt(inst_iter, tid);
1220
1221         inst_iter--;
1222
1223         if (break_loop)
1224             break;
1225     }
1226 }
1227
1228
1229 inline void
1230 InOrderCPU::squashInstIt(const ListIt &instIt, ThreadID tid)
1231 {
1232     if ((*instIt)->threadNumber == tid) {
1233         DPRINTF(InOrderCPU, "Squashing instruction, "
1234                 "[tid:%i] [sn:%lli] PC %#x\n",
1235                 (*instIt)->threadNumber,
1236                 (*instIt)->seqNum,
1237                 (*instIt)->readPC());
1238
1239         (*instIt)->setSquashed();
1240
1241         removeList.push(instIt);
1242     }
1243 }
1244
1245
1246 void
1247 InOrderCPU::cleanUpRemovedInsts()
1248 {
1249     while (!removeList.empty()) {
1250         DPRINTF(InOrderCPU, "Removing instruction, "
1251                 "[tid:%i] [sn:%lli] PC %#x\n",
1252                 (*removeList.front())->threadNumber,
1253                 (*removeList.front())->seqNum,
1254                 (*removeList.front())->readPC());
1255
1256         DynInstPtr inst = *removeList.front();
1257         ThreadID tid = inst->threadNumber;
1258
1259         // Make Sure Resource Schedule Is Emptied Out
1260         ThePipeline::ResSchedule *inst_sched = &inst->resSched;
1261         while (!inst_sched->empty()) {
1262             ThePipeline::ScheduleEntry* sch_entry = inst_sched->top();
1263             inst_sched->pop();
1264             delete sch_entry;
1265         }
1266
1267         // Remove From Register Dependency Map, If Necessary
1268         archRegDepMap[(*removeList.front())->threadNumber].
1269             remove((*removeList.front()));
1270
1271
1272         // Clear if Non-Speculative
1273         if (inst->staticInst &&
1274               inst->seqNum == nonSpecSeqNum[tid] &&
1275                 nonSpecInstActive[tid] == true) {
1276             nonSpecInstActive[tid] = false;
1277         }
1278
1279         instList[tid].erase(removeList.front());
1280
1281         removeList.pop();
1282
1283         DPRINTF(RefCount, "pop from remove list: [sn:%i]: Refcount = %i.\n",
1284                 inst->seqNum,
1285                 0/*inst->curCount()*/);
1286
1287     }
1288
1289     removeInstsThisCycle = false;
1290 }
1291
1292 void
1293 InOrderCPU::cleanUpRemovedReqs()
1294 {
1295     while (!reqRemoveList.empty()) {
1296         ResourceRequest *res_req = reqRemoveList.front();
1297
1298         DPRINTF(RefCount, "[tid:%i]: Removing Request, "
1299                 "[sn:%lli] [slot:%i] [stage_num:%i] [res:%s] [refcount:%i].\n",
1300                 res_req->inst->threadNumber,
1301                 res_req->inst->seqNum,
1302                 res_req->getSlot(),
1303                 res_req->getStageNum(),
1304                 res_req->res->name(),
1305                 0/*res_req->inst->curCount()*/);
1306
1307         reqRemoveList.pop();
1308
1309         delete res_req;
1310
1311         DPRINTF(RefCount, "after remove request: [sn:%i]: Refcount = %i.\n",
1312                 res_req->inst->seqNum,
1313                 0/*res_req->inst->curCount()*/);
1314     }
1315 }
1316
1317 void
1318 InOrderCPU::cleanUpRemovedEvents()
1319 {
1320     while (!cpuEventRemoveList.empty()) {
1321         Event *cpu_event = cpuEventRemoveList.front();
1322         cpuEventRemoveList.pop();
1323         delete cpu_event;
1324     }
1325 }
1326
1327
1328 void
1329 InOrderCPU::dumpInsts()
1330 {
1331     int num = 0;
1332
1333     ListIt inst_list_it = instList[0].begin();
1334
1335     cprintf("Dumping Instruction List\n");
1336
1337     while (inst_list_it != instList[0].end()) {
1338         cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1339                 "Squashed:%i\n\n",
1340                 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
1341                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1342                 (*inst_list_it)->isSquashed());
1343         inst_list_it++;
1344         ++num;
1345     }
1346 }
1347
1348 void
1349 InOrderCPU::wakeCPU()
1350 {
1351     if (/*activityRec.active() || */tickEvent.scheduled()) {
1352         DPRINTF(Activity, "CPU already running.\n");
1353         return;
1354     }
1355
1356     DPRINTF(Activity, "Waking up CPU\n");
1357
1358     Tick extra_cycles = tickToCycles((curTick - 1) - lastRunningCycle);
1359
1360     idleCycles += extra_cycles;
1361     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1362         pipelineStage[stage_num]->idleCycles += extra_cycles;
1363     }
1364
1365     numCycles += extra_cycles;
1366
1367     mainEventQueue.schedule(&tickEvent, curTick);
1368 }
1369
1370 #if FULL_SYSTEM
1371
1372 void
1373 InOrderCPU::wakeup()
1374 {
1375     if (this->thread[0]->status() != ThreadContext::Suspended)
1376         return;
1377
1378     this->wakeCPU();
1379
1380     DPRINTF(Quiesce, "Suspended Processor woken\n");
1381     this->threadContexts[0]->activate();
1382 }
1383 #endif
1384
1385 #if !FULL_SYSTEM
1386 void
1387 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1388 {
1389     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1390
1391     DPRINTF(Activity,"Activity: syscall() called.\n");
1392
1393     // Temporarily increase this by one to account for the syscall
1394     // instruction.
1395     ++(this->thread[tid]->funcExeInst);
1396
1397     // Execute the actual syscall.
1398     this->thread[tid]->syscall(callnum);
1399
1400     // Decrease funcExeInst by one as the normal commit will handle
1401     // incrementing it.
1402     --(this->thread[tid]->funcExeInst);
1403
1404     // Clear Non-Speculative Block Variable
1405     nonSpecInstActive[tid] = false;
1406 }
1407 #endif
1408
1409 void
1410 InOrderCPU::prefetch(DynInstPtr inst)
1411 {
1412     Resource *mem_res = resPool->getResource(dataPortIdx);
1413     return mem_res->prefetch(inst);
1414 }
1415
1416 void
1417 InOrderCPU::writeHint(DynInstPtr inst)
1418 {
1419     Resource *mem_res = resPool->getResource(dataPortIdx);
1420     return mem_res->writeHint(inst);
1421 }
1422
1423
1424 TheISA::TLB*
1425 InOrderCPU::getITBPtr()
1426 {
1427     CacheUnit *itb_res =
1428         dynamic_cast<CacheUnit*>(resPool->getResource(fetchPortIdx));
1429     return itb_res->tlb();
1430 }
1431
1432
1433 TheISA::TLB*
1434 InOrderCPU::getDTBPtr()
1435 {
1436     CacheUnit *dtb_res =
1437         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1438     return dtb_res->tlb();
1439 }
1440
1441 template <class T>
1442 Fault
1443 InOrderCPU::read(DynInstPtr inst, Addr addr, T &data, unsigned flags)
1444 {
1445     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1446     //       you want to run w/out caches?
1447     CacheUnit *cache_res =
1448         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1449
1450     return cache_res->read(inst, addr, data, flags);
1451 }
1452
1453 #ifndef DOXYGEN_SHOULD_SKIP_THIS
1454
1455 template
1456 Fault
1457 InOrderCPU::read(DynInstPtr inst, Addr addr, Twin32_t &data, unsigned flags);
1458
1459 template
1460 Fault
1461 InOrderCPU::read(DynInstPtr inst, Addr addr, Twin64_t &data, unsigned flags);
1462
1463 template
1464 Fault
1465 InOrderCPU::read(DynInstPtr inst, Addr addr, uint64_t &data, unsigned flags);
1466
1467 template
1468 Fault
1469 InOrderCPU::read(DynInstPtr inst, Addr addr, uint32_t &data, unsigned flags);
1470
1471 template
1472 Fault
1473 InOrderCPU::read(DynInstPtr inst, Addr addr, uint16_t &data, unsigned flags);
1474
1475 template
1476 Fault
1477 InOrderCPU::read(DynInstPtr inst, Addr addr, uint8_t &data, unsigned flags);
1478
1479 #endif //DOXYGEN_SHOULD_SKIP_THIS
1480
1481 template<>
1482 Fault
1483 InOrderCPU::read(DynInstPtr inst, Addr addr, double &data, unsigned flags)
1484 {
1485     return read(inst, addr, *(uint64_t*)&data, flags);
1486 }
1487
1488 template<>
1489 Fault
1490 InOrderCPU::read(DynInstPtr inst, Addr addr, float &data, unsigned flags)
1491 {
1492     return read(inst, addr, *(uint32_t*)&data, flags);
1493 }
1494
1495
1496 template<>
1497 Fault
1498 InOrderCPU::read(DynInstPtr inst, Addr addr, int32_t &data, unsigned flags)
1499 {
1500     return read(inst, addr, (uint32_t&)data, flags);
1501 }
1502
1503 template <class T>
1504 Fault
1505 InOrderCPU::write(DynInstPtr inst, T data, Addr addr, unsigned flags,
1506                   uint64_t *write_res)
1507 {
1508     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1509     //       you want to run w/out caches?
1510     CacheUnit *cache_res =
1511         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1512     return cache_res->write(inst, data, addr, flags, write_res);
1513 }
1514
1515 #ifndef DOXYGEN_SHOULD_SKIP_THIS
1516
1517 template
1518 Fault
1519 InOrderCPU::write(DynInstPtr inst, Twin32_t data, Addr addr,
1520                        unsigned flags, uint64_t *res);
1521
1522 template
1523 Fault
1524 InOrderCPU::write(DynInstPtr inst, Twin64_t data, Addr addr,
1525                        unsigned flags, uint64_t *res);
1526
1527 template
1528 Fault
1529 InOrderCPU::write(DynInstPtr inst, uint64_t data, Addr addr,
1530                        unsigned flags, uint64_t *res);
1531
1532 template
1533 Fault
1534 InOrderCPU::write(DynInstPtr inst, uint32_t data, Addr addr,
1535                        unsigned flags, uint64_t *res);
1536
1537 template
1538 Fault
1539 InOrderCPU::write(DynInstPtr inst, uint16_t data, Addr addr,
1540                        unsigned flags, uint64_t *res);
1541
1542 template
1543 Fault
1544 InOrderCPU::write(DynInstPtr inst, uint8_t data, Addr addr,
1545                        unsigned flags, uint64_t *res);
1546
1547 #endif //DOXYGEN_SHOULD_SKIP_THIS
1548
1549 template<>
1550 Fault
1551 InOrderCPU::write(DynInstPtr inst, double data, Addr addr, unsigned flags,
1552                   uint64_t *res)
1553 {
1554     return write(inst, *(uint64_t*)&data, addr, flags, res);
1555 }
1556
1557 template<>
1558 Fault
1559 InOrderCPU::write(DynInstPtr inst, float data, Addr addr, unsigned flags,
1560                   uint64_t *res)
1561 {
1562     return write(inst, *(uint32_t*)&data, addr, flags, res);
1563 }
1564
1565
1566 template<>
1567 Fault
1568 InOrderCPU::write(DynInstPtr inst, int32_t data, Addr addr, unsigned flags,
1569                   uint64_t *res)
1570 {
1571     return write(inst, (uint32_t)data, addr, flags, res);
1572 }