src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <algorithm>
  33
  34 #include "arch/utility.hh"
  35 #include "base/bigint.hh"
  36 #include "config/full_system.hh"
  37 #include "config/the_isa.hh"
  38 #include "cpu/inorder/resources/resource_list.hh"
  39 #include "cpu/inorder/cpu.hh"
  40 #include "cpu/inorder/first_stage.hh"
  41 #include "cpu/inorder/inorder_dyn_inst.hh"
  42 #include "cpu/inorder/pipeline_traits.hh"
  43 #include "cpu/inorder/resource_pool.hh"
  44 #include "cpu/inorder/thread_context.hh"
  45 #include "cpu/inorder/thread_state.hh"
  46 #include "cpu/activity.hh"
  47 #include "cpu/base.hh"
  48 #include "cpu/exetrace.hh"
  49 #include "cpu/simple_thread.hh"
  50 #include "cpu/thread_context.hh"
  51 #include "debug/Activity.hh"
  52 #include "debug/InOrderCPU.hh"
  53 #include "debug/RefCount.hh"
  54 #include "debug/SkedCache.hh"
  55 #include "mem/translating_port.hh"
  56 #include "params/InOrderCPU.hh"
  57 #include "sim/process.hh"
  58 #include "sim/stat_control.hh"
  59
  60 #if FULL_SYSTEM
  61 #include "cpu/quiesce_event.hh"
  62 #include "sim/system.hh"
  63 #endif
  64
  65 #if THE_ISA == ALPHA_ISA
  66 #include "arch/alpha/osfpal.hh"
  67 #endif
  68
  69 using namespace std;
  70 using namespace TheISA;
  71 using namespace ThePipeline;
  72
  73 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
  74   : Event(CPU_Tick_Pri), cpu(c)
  75 { }
  76
  77
  78 void
  79 InOrderCPU::TickEvent::process()
  80 {
  81     cpu->tick();
  82 }
  83
  84
  85 const char *
  86 InOrderCPU::TickEvent::description()
  87 {
  88     return "InOrderCPU tick event";
  89 }
  90
  91 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
  92                                Fault fault, ThreadID _tid, DynInstPtr inst,
  93                                unsigned event_pri_offset)
  94     : Event(Event::Priority((unsigned int)CPU_Tick_Pri + event_pri_offset)),
  95       cpu(_cpu)
  96 {
  97     setEvent(e_type, fault, _tid, inst);
  98 }
  99
 100
 101 std::string InOrderCPU::eventNames[NumCPUEvents] =
 102 {
 103     "ActivateThread",
 104     "ActivateNextReadyThread",
 105     "DeactivateThread",
 106     "HaltThread",
 107     "SuspendThread",
 108     "Trap",
 109     "InstGraduated",
 110     "SquashFromMemStall",
 111     "UpdatePCs"
 112 };
 113
 114 void
 115 InOrderCPU::CPUEvent::process()
 116 {
 117     switch (cpuEventType)
 118     {
 119       case ActivateThread:
 120         cpu->activateThread(tid);
 121         break;
 122
 123       case ActivateNextReadyThread:
 124         cpu->activateNextReadyThread();
 125         break;
 126
 127       case DeactivateThread:
 128         cpu->deactivateThread(tid);
 129         break;
 130
 131       case HaltThread:
 132         cpu->haltThread(tid);
 133         break;
 134
 135       case SuspendThread:
 136         cpu->suspendThread(tid);
 137         break;
 138
 139       case SquashFromMemStall:
 140         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 141         break;
 142
 143       case Trap:
 144         DPRINTF(InOrderCPU, "Trapping CPU\n");
 145         cpu->trapCPU(fault, tid, inst);
 146         break;
 147
 148       default:
 149         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 150     }
 151
 152     cpu->cpuEventRemoveList.push(this);
 153 }
 154
 155
 156
 157 const char *
 158 InOrderCPU::CPUEvent::description()
 159 {
 160     return "InOrderCPU event";
 161 }
 162
 163 void
 164 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 165 {
 166     assert(!scheduled() || squashed());
 167     cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
 168 }
 169
 170 void
 171 InOrderCPU::CPUEvent::unscheduleEvent()
 172 {
 173     if (scheduled())
 174         squash();
 175 }
 176
 177 InOrderCPU::InOrderCPU(Params *params)
 178     : BaseCPU(params),
 179       cpu_id(params->cpu_id),
 180       coreType("default"),
 181       _status(Idle),
 182       tickEvent(this),
 183       stageWidth(params->stageWidth),
 184       timeBuffer(2 , 2),
 185       removeInstsThisCycle(false),
 186       activityRec(params->name, NumStages, 10, params->activity),
 187 #if FULL_SYSTEM
 188       system(params->system),
 189       physmem(system->physmem),
 190 #endif // FULL_SYSTEM
 191 #ifdef DEBUG
 192       cpuEventNum(0),
 193       resReqCount(0),
 194 #endif // DEBUG
 195       switchCount(0),
 196       deferRegistration(false/*params->deferRegistration*/),
 197       stageTracing(params->stageTracing),
 198       instsPerSwitch(0)
 199 {
 200     ThreadID active_threads;
 201     cpu_params = params;
 202
 203     resPool = new ResourcePool(this, params);
 204
 205     // Resize for Multithreading CPUs
 206     thread.resize(numThreads);
 207
 208 #if FULL_SYSTEM
 209     active_threads = 1;
 210 #else
 211     active_threads = params->workload.size();
 212
 213     if (active_threads > MaxThreads) {
 214         panic("Workload Size too large. Increase the 'MaxThreads'"
 215               "in your InOrder implementation or "
 216               "edit your workload size.");
 217     }
 218
 219
 220     if (active_threads > 1) {
 221         threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 222
 223         if (threadModel == SMT) {
 224             DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 225         } else if (threadModel == SwitchOnCacheMiss) {
 226             DPRINTF(InOrderCPU, "Setting Thread Model to "
 227                     "Switch On Cache Miss\n");
 228         }
 229
 230     } else {
 231         threadModel = Single;
 232     }
 233
 234
 235
 236 #endif
 237
 238     // Bind the fetch & data ports from the resource pool.
 239     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
 240     if (fetchPortIdx == 0) {
 241         fatal("Unable to find port to fetch instructions from.\n");
 242     }
 243
 244     dataPortIdx = resPool->getPortIdx(params->dataMemPort);
 245     if (dataPortIdx == 0) {
 246         fatal("Unable to find port for data.\n");
 247     }
 248
 249     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 250 #if FULL_SYSTEM
 251         // SMT is not supported in FS mode yet.
 252         assert(numThreads == 1);
 253         thread[tid] = new Thread(this, 0);
 254 #else
 255         if (tid < (ThreadID)params->workload.size()) {
 256             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 257                     tid, params->workload[tid]->prog_fname);
 258             thread[tid] =
 259                 new Thread(this, tid, params->workload[tid]);
 260         } else {
 261             //Allocate Empty thread so M5 can use later
 262             //when scheduling threads to CPU
 263             Process* dummy_proc = params->workload[0];
 264             thread[tid] = new Thread(this, tid, dummy_proc);
 265         }
 266
 267         // Eventually set this with parameters...
 268         asid[tid] = tid;
 269 #endif
 270
 271         // Setup the TC that will serve as the interface to the threads/CPU.
 272         InOrderThreadContext *tc = new InOrderThreadContext;
 273         tc->cpu = this;
 274         tc->thread = thread[tid];
 275
 276         // Give the thread the TC.
 277         thread[tid]->tc = tc;
 278         thread[tid]->setFuncExeInst(0);
 279         globalSeqNum[tid] = 1;
 280
 281         // Add the TC to the CPU's list of TC's.
 282         this->threadContexts.push_back(tc);
 283     }
 284
 285     // Initialize TimeBuffer Stage Queues
 286     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 287         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 288         stageQueue[stNum]->id(stNum);
 289     }
 290
 291
 292     // Set Up Pipeline Stages
 293     for (int stNum=0; stNum < NumStages; stNum++) {
 294         if (stNum == 0)
 295             pipelineStage[stNum] = new FirstStage(params, stNum);
 296         else
 297             pipelineStage[stNum] = new PipelineStage(params, stNum);
 298
 299         pipelineStage[stNum]->setCPU(this);
 300         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 301         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 302
 303         // Take Care of 1st/Nth stages
 304         if (stNum > 0)
 305             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 306         if (stNum < NumStages - 1)
 307             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 308     }
 309
 310     // Initialize thread specific variables
 311     for (ThreadID tid = 0; tid < numThreads; tid++) {
 312         archRegDepMap[tid].setCPU(this);
 313
 314         nonSpecInstActive[tid] = false;
 315         nonSpecSeqNum[tid] = 0;
 316
 317         squashSeqNum[tid] = MaxAddr;
 318         lastSquashCycle[tid] = 0;
 319
 320         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 321         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 322         isa[tid].clear();
 323
 324         // Define dummy instructions and resource requests to be used.
 325         dummyInst[tid] = new InOrderDynInst(this,
 326                                             thread[tid],
 327                                             0,
 328                                             tid,
 329                                             asid[tid]);
 330
 331         dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
 332     }
 333
 334     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 335     dummyReqInst->setSquashed();
 336     dummyReqInst->resetInstCount();
 337
 338     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 339     dummyBufferInst->setSquashed();
 340     dummyBufferInst->resetInstCount();
 341
 342     endOfSkedIt = skedCache.end();
 343     frontEndSked = createFrontEndSked();
 344
 345     lastRunningCycle = curTick();
 346
 347     // Reset CPU to reset state.
 348 #if FULL_SYSTEM
 349     Fault resetFault = new ResetFault();
 350     resetFault->invoke(tcBase());
 351 #endif
 352
 353
 354     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 355     scheduleTickEvent(0);
 356 }
 357
 358 InOrderCPU::~InOrderCPU()
 359 {
 360     delete resPool;
 361
 362     SkedCacheIt sked_it = skedCache.begin();
 363     SkedCacheIt sked_end = skedCache.end();
 364
 365     while (sked_it != sked_end) {
 366         delete (*sked_it).second;
 367         sked_it++;
 368     }
 369     skedCache.clear();
 370 }
 371
 372 m5::hash_map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
 373
 374 RSkedPtr
 375 InOrderCPU::createFrontEndSked()
 376 {
 377     RSkedPtr res_sked = new ResourceSked();
 378     int stage_num = 0;
 379     StageScheduler F(res_sked, stage_num++);
 380     StageScheduler D(res_sked, stage_num++);
 381
 382     // FETCH
 383     F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
 384     F.needs(ICache, FetchUnit::InitiateFetch);
 385
 386     // DECODE
 387     D.needs(ICache, FetchUnit::CompleteFetch);
 388     D.needs(Decode, DecodeUnit::DecodeInst);
 389     D.needs(BPred, BranchPredictor::PredictBranch);
 390     D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
 391
 392
 393     DPRINTF(SkedCache, "Resource Sked created for instruction \"front_end\"\n");
 394
 395     return res_sked;
 396 }
 397
 398 RSkedPtr
 399 InOrderCPU::createBackEndSked(DynInstPtr inst)
 400 {
 401     RSkedPtr res_sked = lookupSked(inst);
 402     if (res_sked != NULL) {
 403         DPRINTF(SkedCache, "Found %s in sked cache.\n",
 404                 inst->instName());
 405         return res_sked;
 406     } else {
 407         res_sked = new ResourceSked();
 408     }
 409
 410     int stage_num = ThePipeline::BackEndStartStage;
 411     StageScheduler X(res_sked, stage_num++);
 412     StageScheduler M(res_sked, stage_num++);
 413     StageScheduler W(res_sked, stage_num++);
 414
 415     if (!inst->staticInst) {
 416         warn_once("Static Instruction Object Not Set. Can't Create"
 417                   " Back End Schedule");
 418         return NULL;
 419     }
 420
 421     // EXECUTE
 422     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 423         if (!idx || !inst->isStore()) {
 424             X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
 425         }
 426     }
 427
 428     if ( inst->isNonSpeculative() ) {
 429         // skip execution of non speculative insts until later
 430     } else if ( inst->isMemRef() ) {
 431         if ( inst->isLoad() ) {
 432             X.needs(AGEN, AGENUnit::GenerateAddr);
 433         }
 434     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 435         X.needs(MDU, MultDivUnit::StartMultDiv);
 436     } else {
 437         X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 438     }
 439
 440     if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 441         X.needs(MDU, MultDivUnit::EndMultDiv);
 442     }
 443
 444     // MEMORY
 445     if ( inst->isLoad() ) {
 446         M.needs(DCache, CacheUnit::InitiateReadData);
 447     } else if ( inst->isStore() ) {
 448         if ( inst->numSrcRegs() >= 2 ) {
 449             M.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 450         }
 451         M.needs(AGEN, AGENUnit::GenerateAddr);
 452         M.needs(DCache, CacheUnit::InitiateWriteData);
 453     }
 454
 455
 456     // WRITEBACK
 457     if ( inst->isLoad() ) {
 458         W.needs(DCache, CacheUnit::CompleteReadData);
 459     } else if ( inst->isStore() ) {
 460         W.needs(DCache, CacheUnit::CompleteWriteData);
 461     }
 462
 463     if ( inst->isNonSpeculative() ) {
 464         if ( inst->isMemRef() ) fatal("Non-Speculative Memory Instruction");
 465         W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 466     }
 467
 468     W.needs(Grad, GraduationUnit::GraduateInst);
 469
 470     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 471         W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
 472     }
 473
 474     // Insert Back Schedule into our cache of
 475     // resource schedules
 476     addToSkedCache(inst, res_sked);
 477
 478     DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
 479             inst->instName(), inst->getMachInst());
 480     res_sked->print();
 481
 482     return res_sked;
 483 }
 484
 485 void
 486 InOrderCPU::regStats()
 487 {
 488     /* Register the Resource Pool's stats here.*/
 489     resPool->regStats();
 490
 491     /* Register for each Pipeline Stage */
 492     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 493         pipelineStage[stage_num]->regStats();
 494     }
 495
 496     /* Register any of the InOrderCPU's stats here.*/
 497     instsPerCtxtSwitch
 498         .name(name() + ".instsPerContextSwitch")
 499         .desc("Instructions Committed Per Context Switch")
 500         .prereq(instsPerCtxtSwitch);
 501
 502     numCtxtSwitches
 503         .name(name() + ".contextSwitches")
 504         .desc("Number of context switches");
 505
 506     comLoads
 507         .name(name() + ".comLoads")
 508         .desc("Number of Load instructions committed");
 509
 510     comStores
 511         .name(name() + ".comStores")
 512         .desc("Number of Store instructions committed");
 513
 514     comBranches
 515         .name(name() + ".comBranches")
 516         .desc("Number of Branches instructions committed");
 517
 518     comNops
 519         .name(name() + ".comNops")
 520         .desc("Number of Nop instructions committed");
 521
 522     comNonSpec
 523         .name(name() + ".comNonSpec")
 524         .desc("Number of Non-Speculative instructions committed");
 525
 526     comInts
 527         .name(name() + ".comInts")
 528         .desc("Number of Integer instructions committed");
 529
 530     comFloats
 531         .name(name() + ".comFloats")
 532         .desc("Number of Floating Point instructions committed");
 533
 534     timesIdled
 535         .name(name() + ".timesIdled")
 536         .desc("Number of times that the entire CPU went into an idle state and"
 537               " unscheduled itself")
 538         .prereq(timesIdled);
 539
 540     idleCycles
 541         .name(name() + ".idleCycles")
 542         .desc("Number of cycles cpu's stages were not processed");
 543
 544     runCycles
 545         .name(name() + ".runCycles")
 546         .desc("Number of cycles cpu stages are processed.");
 547
 548     activity
 549         .name(name() + ".activity")
 550         .desc("Percentage of cycles cpu is active")
 551         .precision(6);
 552     activity = (runCycles / numCycles) * 100;
 553
 554     threadCycles
 555         .init(numThreads)
 556         .name(name() + ".threadCycles")
 557         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 558
 559     smtCycles
 560         .name(name() + ".smtCycles")
 561         .desc("Total number of cycles that the CPU was in SMT-mode");
 562
 563     committedInsts
 564         .init(numThreads)
 565         .name(name() + ".committedInsts")
 566         .desc("Number of Instructions Simulated (Per-Thread)");
 567
 568     smtCommittedInsts
 569         .init(numThreads)
 570         .name(name() + ".smtCommittedInsts")
 571         .desc("Number of SMT Instructions Simulated (Per-Thread)");
 572
 573     totalCommittedInsts
 574         .name(name() + ".committedInsts_total")
 575         .desc("Number of Instructions Simulated (Total)");
 576
 577     cpi
 578         .name(name() + ".cpi")
 579         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 580         .precision(6);
 581     cpi = numCycles / committedInsts;
 582
 583     smtCpi
 584         .name(name() + ".smt_cpi")
 585         .desc("CPI: Total SMT-CPI")
 586         .precision(6);
 587     smtCpi = smtCycles / smtCommittedInsts;
 588
 589     totalCpi
 590         .name(name() + ".cpi_total")
 591         .desc("CPI: Total CPI of All Threads")
 592         .precision(6);
 593     totalCpi = numCycles / totalCommittedInsts;
 594
 595     ipc
 596         .name(name() + ".ipc")
 597         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 598         .precision(6);
 599     ipc =  committedInsts / numCycles;
 600
 601     smtIpc
 602         .name(name() + ".smt_ipc")
 603         .desc("IPC: Total SMT-IPC")
 604         .precision(6);
 605     smtIpc = smtCommittedInsts / smtCycles;
 606
 607     totalIpc
 608         .name(name() + ".ipc_total")
 609         .desc("IPC: Total IPC of All Threads")
 610         .precision(6);
 611         totalIpc =  totalCommittedInsts / numCycles;
 612
 613     BaseCPU::regStats();
 614 }
 615
 616
 617 void
 618 InOrderCPU::tick()
 619 {
 620     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 621
 622     ++numCycles;
 623
 624     bool pipes_idle = true;
 625
 626     //Tick each of the stages
 627     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 628         pipelineStage[stNum]->tick();
 629
 630         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 631     }
 632
 633     if (pipes_idle)
 634         idleCycles++;
 635     else
 636         runCycles++;
 637
 638     // Now advance the time buffers one tick
 639     timeBuffer.advance();
 640     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 641         stageQueue[sqNum]->advance();
 642     }
 643     activityRec.advance();
 644
 645     // Any squashed events, or insts then remove them now
 646     cleanUpRemovedEvents();
 647     cleanUpRemovedInsts();
 648
 649     // Re-schedule CPU for this cycle
 650     if (!tickEvent.scheduled()) {
 651         if (_status == SwitchedOut) {
 652             // increment stat
 653             lastRunningCycle = curTick();
 654         } else if (!activityRec.active()) {
 655             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 656             lastRunningCycle = curTick();
 657             timesIdled++;
 658         } else {
 659             //Tick next_tick = curTick() + cycles(1);
 660             //tickEvent.schedule(next_tick);
 661             schedule(&tickEvent, nextCycle(curTick() + 1));
 662             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 663                     nextCycle(curTick() + 1));
 664         }
 665     }
 666
 667     tickThreadStats();
 668     updateThreadPriority();
 669 }
 670
 671
 672 void
 673 InOrderCPU::init()
 674 {
 675     if (!deferRegistration) {
 676         registerThreadContexts();
 677     }
 678
 679     // Set inSyscall so that the CPU doesn't squash when initially
 680     // setting up registers.
 681     for (ThreadID tid = 0; tid < numThreads; ++tid)
 682         thread[tid]->inSyscall = true;
 683
 684 #if FULL_SYSTEM
 685     for (ThreadID tid = 0; tid < numThreads; tid++) {
 686         ThreadContext *src_tc = threadContexts[tid];
 687         TheISA::initCPU(src_tc, src_tc->contextId());
 688     }
 689 #endif
 690
 691     // Clear inSyscall.
 692     for (ThreadID tid = 0; tid < numThreads; ++tid)
 693         thread[tid]->inSyscall = false;
 694
 695     // Call Initializiation Routine for Resource Pool
 696     resPool->init();
 697 }
 698
 699 Port*
 700 InOrderCPU::getPort(const std::string &if_name, int idx)
 701 {
 702     return resPool->getPort(if_name, idx);
 703 }
 704
 705 #if FULL_SYSTEM
 706 Fault
 707 InOrderCPU::hwrei(ThreadID tid)
 708 {
 709     panic("hwrei: Unimplemented");
 710
 711     return NoFault;
 712 }
 713
 714
 715 bool
 716 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 717 {
 718     panic("simPalCheck: Unimplemented");
 719
 720     return true;
 721 }
 722
 723
 724 Fault
 725 InOrderCPU::getInterrupts()
 726 {
 727     // Check if there are any outstanding interrupts
 728     return interrupts->getInterrupt(threadContexts[0]);
 729 }
 730
 731
 732 void
 733 InOrderCPU::processInterrupts(Fault interrupt)
 734 {
 735     // Check for interrupts here.  For now can copy the code that
 736     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 737     // is the one that handles the interrupts.
 738     // @todo: Possibly consolidate the interrupt checking code.
 739     // @todo: Allow other threads to handle interrupts.
 740
 741     assert(interrupt != NoFault);
 742     interrupts->updateIntrInfo(threadContexts[0]);
 743
 744     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 745
 746     // Note: Context ID ok here? Impl. of FS mode needs to revisit this
 747     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 748 }
 749
 750
 751 void
 752 InOrderCPU::updateMemPorts()
 753 {
 754     // Update all ThreadContext's memory ports (Functional/Virtual
 755     // Ports)
 756     ThreadID size = thread.size();
 757     for (ThreadID i = 0; i < size; ++i)
 758         thread[i]->connectMemPorts(thread[i]->getTC());
 759 }
 760 #endif
 761
 762 void
 763 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 764 {
 765     //@ Squash Pipeline during TRAP
 766     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 767 }
 768
 769 void
 770 InOrderCPU::trapCPU(Fault fault, ThreadID tid, DynInstPtr inst)
 771 {
 772     fault->invoke(tcBase(tid), inst->staticInst);
 773 }
 774
 775 void
 776 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 777 {
 778     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 779 }
 780
 781
 782 void
 783 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 784                                 ThreadID tid)
 785 {
 786     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 787
 788     // Squash all instructions in each stage including
 789     // instruction that caused the squash (seq_num - 1)
 790     // NOTE: The stage bandwidth needs to be cleared so thats why
 791     //       the stalling instruction is squashed as well. The stalled
 792     //       instruction is previously placed in another intermediate buffer
 793     //       while it's stall is being handled.
 794     InstSeqNum squash_seq_num = seq_num - 1;
 795
 796     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 797         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 798     }
 799 }
 800
 801 void
 802 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 803                              ThreadID tid, DynInstPtr inst,
 804                              unsigned delay, unsigned event_pri_offset)
 805 {
 806     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 807                                        event_pri_offset);
 808
 809     Tick sked_tick = nextCycle(curTick() + ticks(delay));
 810     if (delay >= 0) {
 811         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 812                 eventNames[c_event], curTick() + delay, tid);
 813         schedule(cpu_event, sked_tick);
 814     } else {
 815         cpu_event->process();
 816         cpuEventRemoveList.push(cpu_event);
 817     }
 818
 819     // Broadcast event to the Resource Pool
 820     // Need to reset tid just in case this is a dummy instruction
 821     inst->setTid(tid);
 822     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 823 }
 824
 825 bool
 826 InOrderCPU::isThreadActive(ThreadID tid)
 827 {
 828   list<ThreadID>::iterator isActive =
 829       std::find(activeThreads.begin(), activeThreads.end(), tid);
 830
 831     return (isActive != activeThreads.end());
 832 }
 833
 834 bool
 835 InOrderCPU::isThreadReady(ThreadID tid)
 836 {
 837   list<ThreadID>::iterator isReady =
 838       std::find(readyThreads.begin(), readyThreads.end(), tid);
 839
 840     return (isReady != readyThreads.end());
 841 }
 842
 843 bool
 844 InOrderCPU::isThreadSuspended(ThreadID tid)
 845 {
 846   list<ThreadID>::iterator isSuspended =
 847       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
 848
 849     return (isSuspended != suspendedThreads.end());
 850 }
 851
 852 void
 853 InOrderCPU::activateNextReadyThread()
 854 {
 855     if (readyThreads.size() >= 1) {
 856         ThreadID ready_tid = readyThreads.front();
 857
 858         // Activate in Pipeline
 859         activateThread(ready_tid);
 860
 861         // Activate in Resource Pool
 862         resPool->activateAll(ready_tid);
 863
 864         list<ThreadID>::iterator ready_it =
 865             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
 866         readyThreads.erase(ready_it);
 867     } else {
 868         DPRINTF(InOrderCPU,
 869                 "Attempting to activate new thread, but No Ready Threads to"
 870                 "activate.\n");
 871         DPRINTF(InOrderCPU,
 872                 "Unable to switch to next active thread.\n");
 873     }
 874 }
 875
 876 void
 877 InOrderCPU::activateThread(ThreadID tid)
 878 {
 879     if (isThreadSuspended(tid)) {
 880         DPRINTF(InOrderCPU,
 881                 "Removing [tid:%i] from suspended threads list.\n", tid);
 882
 883         list<ThreadID>::iterator susp_it =
 884             std::find(suspendedThreads.begin(), suspendedThreads.end(),
 885                       tid);
 886         suspendedThreads.erase(susp_it);
 887     }
 888
 889     if (threadModel == SwitchOnCacheMiss &&
 890         numActiveThreads() == 1) {
 891         DPRINTF(InOrderCPU,
 892                 "Ignoring activation of [tid:%i], since [tid:%i] is "
 893                 "already running.\n", tid, activeThreadId());
 894
 895         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
 896                 tid);
 897
 898         readyThreads.push_back(tid);
 899
 900     } else if (!isThreadActive(tid)) {
 901         DPRINTF(InOrderCPU,
 902                 "Adding [tid:%i] to active threads list.\n", tid);
 903         activeThreads.push_back(tid);
 904
 905         activateThreadInPipeline(tid);
 906
 907         thread[tid]->lastActivate = curTick();
 908
 909         tcBase(tid)->setStatus(ThreadContext::Active);
 910
 911         wakeCPU();
 912
 913         numCtxtSwitches++;
 914     }
 915 }
 916
 917 void
 918 InOrderCPU::activateThreadInPipeline(ThreadID tid)
 919 {
 920     for (int stNum=0; stNum < NumStages; stNum++) {
 921         pipelineStage[stNum]->activateThread(tid);
 922     }
 923 }
 924
 925 void
 926 InOrderCPU::deactivateContext(ThreadID tid, int delay)
 927 {
 928     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
 929
 930     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
 931
 932     // Be sure to signal that there's some activity so the CPU doesn't
 933     // deschedule itself.
 934     activityRec.activity();
 935
 936     _status = Running;
 937 }
 938
 939 void
 940 InOrderCPU::deactivateThread(ThreadID tid)
 941 {
 942     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
 943
 944     if (isThreadActive(tid)) {
 945         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
 946                 tid);
 947         list<ThreadID>::iterator thread_it =
 948             std::find(activeThreads.begin(), activeThreads.end(), tid);
 949
 950         removePipelineStalls(*thread_it);
 951
 952         activeThreads.erase(thread_it);
 953
 954         // Ideally, this should be triggered from the
 955         // suspendContext/Thread functions
 956         tcBase(tid)->setStatus(ThreadContext::Suspended);
 957     }
 958
 959     assert(!isThreadActive(tid));
 960 }
 961
 962 void
 963 InOrderCPU::removePipelineStalls(ThreadID tid)
 964 {
 965     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
 966             tid);
 967
 968     for (int stNum = 0; stNum < NumStages ; stNum++) {
 969         pipelineStage[stNum]->removeStalls(tid);
 970     }
 971
 972 }
 973
 974 void
 975 InOrderCPU::updateThreadPriority()
 976 {
 977     if (activeThreads.size() > 1)
 978     {
 979         //DEFAULT TO ROUND ROBIN SCHEME
 980         //e.g. Move highest priority to end of thread list
 981         list<ThreadID>::iterator list_begin = activeThreads.begin();
 982         list<ThreadID>::iterator list_end   = activeThreads.end();
 983
 984         unsigned high_thread = *list_begin;
 985
 986         activeThreads.erase(list_begin);
 987
 988         activeThreads.push_back(high_thread);
 989     }
 990 }
 991
 992 inline void
 993 InOrderCPU::tickThreadStats()
 994 {
 995     /** Keep track of cycles that each thread is active */
 996     list<ThreadID>::iterator thread_it = activeThreads.begin();
 997     while (thread_it != activeThreads.end()) {
 998         threadCycles[*thread_it]++;
 999         thread_it++;
1000     }
1001
1002     // Keep track of cycles where SMT is active
1003     if (activeThreads.size() > 1) {
1004         smtCycles++;
1005     }
1006 }
1007
1008 void
1009 InOrderCPU::activateContext(ThreadID tid, int delay)
1010 {
1011     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
1012
1013
1014     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
1015
1016     // Be sure to signal that there's some activity so the CPU doesn't
1017     // deschedule itself.
1018     activityRec.activity();
1019
1020     _status = Running;
1021 }
1022
1023 void
1024 InOrderCPU::activateNextReadyContext(int delay)
1025 {
1026     DPRINTF(InOrderCPU,"Activating next ready thread\n");
1027
1028     // NOTE: Add 5 to the event priority so that we always activate
1029     // threads after we've finished deactivating, squashing,etc.
1030     // other threads
1031     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
1032                      delay, 5);
1033
1034     // Be sure to signal that there's some activity so the CPU doesn't
1035     // deschedule itself.
1036     activityRec.activity();
1037
1038     _status = Running;
1039 }
1040
1041 void
1042 InOrderCPU::haltContext(ThreadID tid, int delay)
1043 {
1044     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
1045
1046     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
1047
1048     activityRec.activity();
1049 }
1050
1051 void
1052 InOrderCPU::haltThread(ThreadID tid)
1053 {
1054     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
1055     deactivateThread(tid);
1056     squashThreadInPipeline(tid);
1057     haltedThreads.push_back(tid);
1058
1059     tcBase(tid)->setStatus(ThreadContext::Halted);
1060
1061     if (threadModel == SwitchOnCacheMiss) {
1062         activateNextReadyContext();
1063     }
1064 }
1065
1066 void
1067 InOrderCPU::suspendContext(ThreadID tid, int delay)
1068 {
1069     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
1070 }
1071
1072 void
1073 InOrderCPU::suspendThread(ThreadID tid)
1074 {
1075     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
1076             tid);
1077     deactivateThread(tid);
1078     suspendedThreads.push_back(tid);
1079     thread[tid]->lastSuspend = curTick();
1080
1081     tcBase(tid)->setStatus(ThreadContext::Suspended);
1082 }
1083
1084 void
1085 InOrderCPU::squashThreadInPipeline(ThreadID tid)
1086 {
1087     //Squash all instructions in each stage
1088     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
1089         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
1090     }
1091 }
1092
1093 PipelineStage*
1094 InOrderCPU::getPipeStage(int stage_num)
1095 {
1096     return pipelineStage[stage_num];
1097 }
1098
1099 RegIndex
1100 InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
1101 {
1102     if (reg_idx < FP_Base_DepTag) {
1103         reg_type = IntType;
1104         return isa[tid].flattenIntIndex(reg_idx);
1105     } else if (reg_idx < Ctrl_Base_DepTag) {
1106         reg_type = FloatType;
1107         reg_idx -= FP_Base_DepTag;
1108         return isa[tid].flattenFloatIndex(reg_idx);
1109     } else {
1110         reg_type = MiscType;
1111         return reg_idx - TheISA::Ctrl_Base_DepTag;
1112     }
1113 }
1114
1115 uint64_t
1116 InOrderCPU::readIntReg(RegIndex reg_idx, ThreadID tid)
1117 {
1118     DPRINTF(IntRegs, "[tid:%i]: Reading Int. Reg %i as %x\n",
1119             tid, reg_idx, intRegs[tid][reg_idx]);
1120
1121     return intRegs[tid][reg_idx];
1122 }
1123
1124 FloatReg
1125 InOrderCPU::readFloatReg(RegIndex reg_idx, ThreadID tid)
1126 {
1127     return floatRegs.f[tid][reg_idx];
1128 }
1129
1130 FloatRegBits
1131 InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
1132 {;
1133     return floatRegs.i[tid][reg_idx];
1134 }
1135
1136 void
1137 InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid)
1138 {
1139     if (reg_idx == TheISA::ZeroReg) {
1140         DPRINTF(IntRegs, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1141                 "(Int. Reg %i) to %x\n", tid, reg_idx, val);
1142         return;
1143     } else {
1144         DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
1145                 tid, reg_idx, val);
1146
1147         intRegs[tid][reg_idx] = val;
1148     }
1149 }
1150
1151
1152 void
1153 InOrderCPU::setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid)
1154 {
1155     floatRegs.f[tid][reg_idx] = val;
1156 }
1157
1158
1159 void
1160 InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid)
1161 {
1162     floatRegs.i[tid][reg_idx] = val;
1163 }
1164
1165 uint64_t
1166 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1167 {
1168     // If Default value is set, then retrieve target thread
1169     if (tid == InvalidThreadID) {
1170         tid = TheISA::getTargetThread(tcBase(tid));
1171     }
1172
1173     if (reg_idx < FP_Base_DepTag) {
1174         // Integer Register File
1175         return readIntReg(reg_idx, tid);
1176     } else if (reg_idx < Ctrl_Base_DepTag) {
1177         // Float Register File
1178         reg_idx -= FP_Base_DepTag;
1179         return readFloatRegBits(reg_idx, tid);
1180     } else {
1181         reg_idx -= Ctrl_Base_DepTag;
1182         return readMiscReg(reg_idx, tid);  // Misc. Register File
1183     }
1184 }
1185 void
1186 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1187                               ThreadID tid)
1188 {
1189     // If Default value is set, then retrieve target thread
1190     if (tid == InvalidThreadID) {
1191         tid = TheISA::getTargetThread(tcBase(tid));
1192     }
1193
1194     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1195         setIntReg(reg_idx, val, tid);
1196     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1197         reg_idx -= FP_Base_DepTag;
1198         setFloatRegBits(reg_idx, val, tid);
1199     } else {
1200         reg_idx -= Ctrl_Base_DepTag;
1201         setMiscReg(reg_idx, val, tid); // Misc. Register File
1202     }
1203 }
1204
1205 MiscReg
1206 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1207 {
1208     return isa[tid].readMiscRegNoEffect(misc_reg);
1209 }
1210
1211 MiscReg
1212 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1213 {
1214     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1215 }
1216
1217 void
1218 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1219 {
1220     isa[tid].setMiscRegNoEffect(misc_reg, val);
1221 }
1222
1223 void
1224 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1225 {
1226     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1227 }
1228
1229
1230 InOrderCPU::ListIt
1231 InOrderCPU::addInst(DynInstPtr inst)
1232 {
1233     ThreadID tid = inst->readTid();
1234
1235     instList[tid].push_back(inst);
1236
1237     return --(instList[tid].end());
1238 }
1239
1240 void
1241 InOrderCPU::updateContextSwitchStats()
1242 {
1243     // Set Average Stat Here, then reset to 0
1244     instsPerCtxtSwitch = instsPerSwitch;
1245     instsPerSwitch = 0;
1246 }
1247
1248
1249 void
1250 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1251 {
1252     // Set the CPU's PCs - This contributes to the precise state of the CPU
1253     // which can be used when restoring a thread to the CPU after after any
1254     // type of context switching activity (fork, exception, etc.)
1255     pcState(inst->pcState(), tid);
1256
1257     if (inst->isControl()) {
1258         thread[tid]->lastGradIsBranch = true;
1259         thread[tid]->lastBranchPC = inst->pcState();
1260         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1261     } else {
1262         thread[tid]->lastGradIsBranch = false;
1263     }
1264
1265
1266     // Finalize Trace Data For Instruction
1267     if (inst->traceData) {
1268         //inst->traceData->setCycle(curTick());
1269         inst->traceData->setFetchSeq(inst->seqNum);
1270         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1271         inst->traceData->dump();
1272         delete inst->traceData;
1273         inst->traceData = NULL;
1274     }
1275
1276     // Increment active thread's instruction count
1277     instsPerSwitch++;
1278
1279     // Increment thread-state's instruction count
1280     thread[tid]->numInst++;
1281
1282     // Increment thread-state's instruction stats
1283     thread[tid]->numInsts++;
1284
1285     // Count committed insts per thread stats
1286     committedInsts[tid]++;
1287
1288     // Count total insts committed stat
1289     totalCommittedInsts++;
1290
1291     // Count SMT-committed insts per thread stat
1292     if (numActiveThreads() > 1) {
1293         smtCommittedInsts[tid]++;
1294     }
1295
1296     // Instruction-Mix Stats
1297     if (inst->isLoad()) {
1298         comLoads++;
1299     } else if (inst->isStore()) {
1300         comStores++;
1301     } else if (inst->isControl()) {
1302         comBranches++;
1303     } else if (inst->isNop()) {
1304         comNops++;
1305     } else if (inst->isNonSpeculative()) {
1306         comNonSpec++;
1307     } else if (inst->isInteger()) {
1308         comInts++;
1309     } else if (inst->isFloating()) {
1310         comFloats++;
1311     }
1312
1313     // Check for instruction-count-based events.
1314     comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1315
1316     // Broadcast to other resources an instruction
1317     // has been completed
1318     resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
1319                            0, 0, tid);
1320
1321     // Finally, remove instruction from CPU
1322     removeInst(inst);
1323 }
1324
1325 // currently unused function, but substitute repetitive code w/this function
1326 // call
1327 void
1328 InOrderCPU::addToRemoveList(DynInstPtr inst)
1329 {
1330     removeInstsThisCycle = true;
1331     if (!inst->isRemoveList()) {
1332         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1333                 "[sn:%lli] to remove list\n",
1334                 inst->threadNumber, inst->pcState(), inst->seqNum);
1335         inst->setRemoveList();
1336         removeList.push(inst->getInstListIt());
1337     }  else {
1338         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1339                 "[sn:%lli], already remove list\n",
1340                 inst->threadNumber, inst->pcState(), inst->seqNum);
1341     }
1342
1343 }
1344
1345 void
1346 InOrderCPU::removeInst(DynInstPtr inst)
1347 {
1348     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1349             "[sn:%lli]\n",
1350             inst->threadNumber, inst->pcState(), inst->seqNum);
1351
1352     removeInstsThisCycle = true;
1353
1354     // Remove the instruction.
1355     if (!inst->isRemoveList()) {
1356         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1357                 "[sn:%lli] to remove list\n",
1358                 inst->threadNumber, inst->pcState(), inst->seqNum);
1359         inst->setRemoveList();
1360         removeList.push(inst->getInstListIt());
1361     } else {
1362         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1363                 "[sn:%lli], already on remove list\n",
1364                 inst->threadNumber, inst->pcState(), inst->seqNum);
1365     }
1366
1367 }
1368
1369 void
1370 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1371 {
1372     //assert(!instList[tid].empty());
1373
1374     removeInstsThisCycle = true;
1375
1376     ListIt inst_iter = instList[tid].end();
1377
1378     inst_iter--;
1379
1380     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1381             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1382             tid, seq_num, (*inst_iter)->seqNum);
1383
1384     while ((*inst_iter)->seqNum > seq_num) {
1385
1386         bool break_loop = (inst_iter == instList[tid].begin());
1387
1388         squashInstIt(inst_iter, tid);
1389
1390         inst_iter--;
1391
1392         if (break_loop)
1393             break;
1394     }
1395 }
1396
1397
1398 inline void
1399 InOrderCPU::squashInstIt(const ListIt &instIt, ThreadID tid)
1400 {
1401     if ((*instIt)->threadNumber == tid) {
1402         DPRINTF(InOrderCPU, "Squashing instruction, "
1403                 "[tid:%i] [sn:%lli] PC %s\n",
1404                 (*instIt)->threadNumber,
1405                 (*instIt)->seqNum,
1406                 (*instIt)->pcState());
1407
1408         (*instIt)->setSquashed();
1409
1410         if (!(*instIt)->isRemoveList()) {
1411             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1412                     "[sn:%lli] to remove list\n",
1413                     (*instIt)->threadNumber, (*instIt)->pcState(),
1414                     (*instIt)->seqNum);
1415             (*instIt)->setRemoveList();
1416             removeList.push(instIt);
1417         } else {
1418             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1419                     " PC %s [sn:%lli], already on remove list\n",
1420                     (*instIt)->threadNumber, (*instIt)->pcState(),
1421                     (*instIt)->seqNum);
1422         }
1423
1424     }
1425
1426 }
1427
1428
1429 void
1430 InOrderCPU::cleanUpRemovedInsts()
1431 {
1432     while (!removeList.empty()) {
1433         DPRINTF(InOrderCPU, "Removing instruction, "
1434                 "[tid:%i] [sn:%lli] PC %s\n",
1435                 (*removeList.front())->threadNumber,
1436                 (*removeList.front())->seqNum,
1437                (*removeList.front())->pcState());
1438
1439         DynInstPtr inst = *removeList.front();
1440         ThreadID tid = inst->threadNumber;
1441
1442         // Remove From Register Dependency Map, If Necessary
1443         archRegDepMap[tid].remove(inst);
1444
1445         // Clear if Non-Speculative
1446         if (inst->staticInst &&
1447             inst->seqNum == nonSpecSeqNum[tid] &&
1448             nonSpecInstActive[tid] == true) {
1449             nonSpecInstActive[tid] = false;
1450         }
1451
1452         inst->onInstList = false;
1453
1454         instList[tid].erase(removeList.front());
1455
1456         removeList.pop();
1457     }
1458
1459     removeInstsThisCycle = false;
1460 }
1461
1462 void
1463 InOrderCPU::cleanUpRemovedEvents()
1464 {
1465     while (!cpuEventRemoveList.empty()) {
1466         Event *cpu_event = cpuEventRemoveList.front();
1467         cpuEventRemoveList.pop();
1468         delete cpu_event;
1469     }
1470 }
1471
1472
1473 void
1474 InOrderCPU::dumpInsts()
1475 {
1476     int num = 0;
1477
1478     ListIt inst_list_it = instList[0].begin();
1479
1480     cprintf("Dumping Instruction List\n");
1481
1482     while (inst_list_it != instList[0].end()) {
1483         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1484                 "Squashed:%i\n\n",
1485                 num, (*inst_list_it)->pcState(),
1486                 (*inst_list_it)->threadNumber,
1487                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1488                 (*inst_list_it)->isSquashed());
1489         inst_list_it++;
1490         ++num;
1491     }
1492 }
1493
1494 void
1495 InOrderCPU::wakeCPU()
1496 {
1497     if (/*activityRec.active() || */tickEvent.scheduled()) {
1498         DPRINTF(Activity, "CPU already running.\n");
1499         return;
1500     }
1501
1502     DPRINTF(Activity, "Waking up CPU\n");
1503
1504     Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
1505
1506     idleCycles += extra_cycles;
1507     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1508         pipelineStage[stage_num]->idleCycles += extra_cycles;
1509     }
1510
1511     numCycles += extra_cycles;
1512
1513     schedule(&tickEvent, nextCycle(curTick()));
1514 }
1515
1516 #if FULL_SYSTEM
1517
1518 void
1519 InOrderCPU::wakeup()
1520 {
1521     if (thread[0]->status() != ThreadContext::Suspended)
1522         return;
1523
1524     wakeCPU();
1525
1526     DPRINTF(Quiesce, "Suspended Processor woken\n");
1527     threadContexts[0]->activate();
1528 }
1529 #endif
1530
1531 #if !FULL_SYSTEM
1532 void
1533 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1534 {
1535     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1536
1537     DPRINTF(Activity,"Activity: syscall() called.\n");
1538
1539     // Temporarily increase this by one to account for the syscall
1540     // instruction.
1541     ++(this->thread[tid]->funcExeInst);
1542
1543     // Execute the actual syscall.
1544     this->thread[tid]->syscall(callnum);
1545
1546     // Decrease funcExeInst by one as the normal commit will handle
1547     // incrementing it.
1548     --(this->thread[tid]->funcExeInst);
1549
1550     // Clear Non-Speculative Block Variable
1551     nonSpecInstActive[tid] = false;
1552 }
1553 #endif
1554
1555 TheISA::TLB*
1556 InOrderCPU::getITBPtr()
1557 {
1558     CacheUnit *itb_res =
1559         dynamic_cast<CacheUnit*>(resPool->getResource(fetchPortIdx));
1560     return itb_res->tlb();
1561 }
1562
1563
1564 TheISA::TLB*
1565 InOrderCPU::getDTBPtr()
1566 {
1567     CacheUnit *dtb_res =
1568         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1569     return dtb_res->tlb();
1570 }
1571
1572 Fault
1573 InOrderCPU::read(DynInstPtr inst, Addr addr,
1574                  uint8_t *data, unsigned size, unsigned flags)
1575 {
1576     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1577     //       you want to run w/out caches?
1578     CacheUnit *cache_res =
1579         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1580
1581     return cache_res->read(inst, addr, data, size, flags);
1582 }
1583
1584 Fault
1585 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1586                   Addr addr, unsigned flags, uint64_t *write_res)
1587 {
1588     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1589     //       you want to run w/out caches?
1590     CacheUnit *cache_res =
1591         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1592     return cache_res->write(inst, data, size, addr, flags, write_res);
1593 }