2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "arch/utility.hh"
35 #include "base/bigint.hh"
36 #include "config/full_system.hh"
37 #include "config/the_isa.hh"
38 #include "cpu/inorder/resources/resource_list.hh"
39 #include "cpu/inorder/cpu.hh"
40 #include "cpu/inorder/first_stage.hh"
41 #include "cpu/inorder/inorder_dyn_inst.hh"
42 #include "cpu/inorder/pipeline_traits.hh"
43 #include "cpu/inorder/resource_pool.hh"
44 #include "cpu/inorder/thread_context.hh"
45 #include "cpu/inorder/thread_state.hh"
46 #include "cpu/activity.hh"
47 #include "cpu/base.hh"
48 #include "cpu/exetrace.hh"
49 #include "cpu/simple_thread.hh"
50 #include "cpu/thread_context.hh"
51 #include "debug/Activity.hh"
52 #include "debug/InOrderCPU.hh"
53 #include "debug/RefCount.hh"
54 #include "debug/SkedCache.hh"
55 #include "mem/translating_port.hh"
56 #include "params/InOrderCPU.hh"
57 #include "sim/process.hh"
58 #include "sim/stat_control.hh"
61 #include "cpu/quiesce_event.hh"
62 #include "sim/system.hh"
65 #if THE_ISA == ALPHA_ISA
66 #include "arch/alpha/osfpal.hh"
70 using namespace TheISA
;
71 using namespace ThePipeline
;
73 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
74 : Event(CPU_Tick_Pri
), cpu(c
)
79 InOrderCPU::TickEvent::process()
86 InOrderCPU::TickEvent::description()
88 return "InOrderCPU tick event";
91 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
92 Fault fault
, ThreadID _tid
, DynInstPtr inst
,
93 CPUEventPri event_pri
)
94 : Event(event_pri
), cpu(_cpu
)
96 setEvent(e_type
, fault
, _tid
, inst
);
100 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
103 "ActivateNextReadyThread",
109 "SquashFromMemStall",
114 InOrderCPU::CPUEvent::process()
116 switch (cpuEventType
)
119 cpu
->activateThread(tid
);
120 cpu
->resPool
->activateThread(tid
);
123 case ActivateNextReadyThread
:
124 cpu
->activateNextReadyThread();
127 case DeactivateThread
:
128 cpu
->deactivateThread(tid
);
129 cpu
->resPool
->deactivateThread(tid
);
133 cpu
->haltThread(tid
);
134 cpu
->resPool
->deactivateThread(tid
);
138 cpu
->suspendThread(tid
);
139 cpu
->resPool
->suspendThread(tid
);
142 case SquashFromMemStall
:
143 cpu
->squashDueToMemStall(inst
->squashingStage
, inst
->seqNum
, tid
);
144 cpu
->resPool
->squashDueToMemStall(inst
, inst
->squashingStage
,
149 DPRINTF(InOrderCPU
, "Trapping CPU\n");
150 cpu
->trap(fault
, tid
, inst
);
151 cpu
->resPool
->trap(fault
, tid
, inst
);
156 cpu
->syscall(inst
->syscallNum
, tid
);
157 cpu
->resPool
->trap(fault
, tid
, inst
);
161 fatal("Unrecognized Event Type %s", eventNames
[cpuEventType
]);
164 cpu
->cpuEventRemoveList
.push(this);
170 InOrderCPU::CPUEvent::description()
172 return "InOrderCPU event";
176 InOrderCPU::CPUEvent::scheduleEvent(int delay
)
178 assert(!scheduled() || squashed());
179 cpu
->reschedule(this, cpu
->nextCycle(curTick() + cpu
->ticks(delay
)), true);
183 InOrderCPU::CPUEvent::unscheduleEvent()
189 InOrderCPU::InOrderCPU(Params
*params
)
191 cpu_id(params
->cpu_id
),
195 stageWidth(params
->stageWidth
),
197 removeInstsThisCycle(false),
198 activityRec(params
->name
, NumStages
, 10, params
->activity
),
201 system(params
->system
),
202 #endif // FULL_SYSTEM
208 deferRegistration(false/*params->deferRegistration*/),
209 stageTracing(params
->stageTracing
),
213 ThreadID active_threads
;
216 resPool
= new ResourcePool(this, params
);
218 // Resize for Multithreading CPUs
219 thread
.resize(numThreads
);
224 active_threads
= params
->workload
.size();
226 if (active_threads
> MaxThreads
) {
227 panic("Workload Size too large. Increase the 'MaxThreads'"
228 "in your InOrder implementation or "
229 "edit your workload size.");
233 if (active_threads
> 1) {
234 threadModel
= (InOrderCPU::ThreadModel
) params
->threadModel
;
236 if (threadModel
== SMT
) {
237 DPRINTF(InOrderCPU
, "Setting Thread Model to SMT.\n");
238 } else if (threadModel
== SwitchOnCacheMiss
) {
239 DPRINTF(InOrderCPU
, "Setting Thread Model to "
240 "Switch On Cache Miss\n");
244 threadModel
= Single
;
251 // Bind the fetch & data ports from the resource pool.
252 fetchPortIdx
= resPool
->getPortIdx(params
->fetchMemPort
);
253 if (fetchPortIdx
== 0) {
254 fatal("Unable to find port to fetch instructions from.\n");
257 dataPortIdx
= resPool
->getPortIdx(params
->dataMemPort
);
258 if (dataPortIdx
== 0) {
259 fatal("Unable to find port for data.\n");
262 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
264 lastCommittedPC
[tid
].set(0);
267 // SMT is not supported in FS mode yet.
268 assert(numThreads
== 1);
269 thread
[tid
] = new Thread(this, 0);
271 if (tid
< (ThreadID
)params
->workload
.size()) {
272 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
273 tid
, params
->workload
[tid
]->prog_fname
);
275 new Thread(this, tid
, params
->workload
[tid
]);
277 //Allocate Empty thread so M5 can use later
278 //when scheduling threads to CPU
279 Process
* dummy_proc
= params
->workload
[0];
280 thread
[tid
] = new Thread(this, tid
, dummy_proc
);
283 // Eventually set this with parameters...
287 // Setup the TC that will serve as the interface to the threads/CPU.
288 InOrderThreadContext
*tc
= new InOrderThreadContext
;
290 tc
->thread
= thread
[tid
];
293 // Setup quiesce event.
294 this->thread
[tid
]->quiesceEvent
= new EndQuiesceEvent(tc
);
297 // Give the thread the TC.
298 thread
[tid
]->tc
= tc
;
299 thread
[tid
]->setFuncExeInst(0);
300 globalSeqNum
[tid
] = 1;
302 // Add the TC to the CPU's list of TC's.
303 this->threadContexts
.push_back(tc
);
306 // Initialize TimeBuffer Stage Queues
307 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
308 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
309 stageQueue
[stNum
]->id(stNum
);
313 // Set Up Pipeline Stages
314 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
316 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
318 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
320 pipelineStage
[stNum
]->setCPU(this);
321 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
322 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
324 // Take Care of 1st/Nth stages
326 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
327 if (stNum
< NumStages
- 1)
328 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
331 // Initialize thread specific variables
332 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
333 archRegDepMap
[tid
].setCPU(this);
335 nonSpecInstActive
[tid
] = false;
336 nonSpecSeqNum
[tid
] = 0;
338 squashSeqNum
[tid
] = MaxAddr
;
339 lastSquashCycle
[tid
] = 0;
341 memset(intRegs
[tid
], 0, sizeof(intRegs
[tid
]));
342 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
345 // Define dummy instructions and resource requests to be used.
346 dummyInst
[tid
] = new InOrderDynInst(this,
352 dummyReq
[tid
] = new ResourceRequest(resPool
->getResource(0));
355 // Use this dummy inst to force squashing behind every instruction
357 dummyTrapInst
[tid
] = new InOrderDynInst(this, NULL
, 0, 0, 0);
358 dummyTrapInst
[tid
]->seqNum
= 0;
359 dummyTrapInst
[tid
]->squashSeqNum
= 0;
360 dummyTrapInst
[tid
]->setTid(tid
);
365 dummyReqInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
366 dummyReqInst
->setSquashed();
367 dummyReqInst
->resetInstCount();
369 dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
370 dummyBufferInst
->setSquashed();
371 dummyBufferInst
->resetInstCount();
373 endOfSkedIt
= skedCache
.end();
374 frontEndSked
= createFrontEndSked();
376 lastRunningCycle
= curTick();
381 // Schedule First Tick Event, CPU will reschedule itself from here on out.
382 scheduleTickEvent(0);
385 InOrderCPU::~InOrderCPU()
389 SkedCacheIt sked_it
= skedCache
.begin();
390 SkedCacheIt sked_end
= skedCache
.end();
392 while (sked_it
!= sked_end
) {
393 delete (*sked_it
).second
;
399 m5::hash_map
<InOrderCPU::SkedID
, ThePipeline::RSkedPtr
> InOrderCPU::skedCache
;
402 InOrderCPU::createFrontEndSked()
404 RSkedPtr res_sked
= new ResourceSked();
406 StageScheduler
F(res_sked
, stage_num
++);
407 StageScheduler
D(res_sked
, stage_num
++);
410 F
.needs(FetchSeq
, FetchSeqUnit::AssignNextPC
);
411 F
.needs(ICache
, FetchUnit::InitiateFetch
);
414 D
.needs(ICache
, FetchUnit::CompleteFetch
);
415 D
.needs(Decode
, DecodeUnit::DecodeInst
);
416 D
.needs(BPred
, BranchPredictor::PredictBranch
);
417 D
.needs(FetchSeq
, FetchSeqUnit::UpdateTargetPC
);
420 DPRINTF(SkedCache
, "Resource Sked created for instruction \"front_end\"\n");
426 InOrderCPU::createBackEndSked(DynInstPtr inst
)
428 RSkedPtr res_sked
= lookupSked(inst
);
429 if (res_sked
!= NULL
) {
430 DPRINTF(SkedCache
, "Found %s in sked cache.\n",
434 res_sked
= new ResourceSked();
437 int stage_num
= ThePipeline::BackEndStartStage
;
438 StageScheduler
X(res_sked
, stage_num
++);
439 StageScheduler
M(res_sked
, stage_num
++);
440 StageScheduler
W(res_sked
, stage_num
++);
442 if (!inst
->staticInst
) {
443 warn_once("Static Instruction Object Not Set. Can't Create"
444 " Back End Schedule");
449 X
.needs(RegManager
, UseDefUnit::MarkDestRegs
);
450 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
451 if (!idx
|| !inst
->isStore()) {
452 X
.needs(RegManager
, UseDefUnit::ReadSrcReg
, idx
);
456 //@todo: schedule non-spec insts to operate on this cycle
457 // as long as all previous insts are done
458 if ( inst
->isNonSpeculative() ) {
459 // skip execution of non speculative insts until later
460 } else if ( inst
->isMemRef() ) {
461 if ( inst
->isLoad() ) {
462 X
.needs(AGEN
, AGENUnit::GenerateAddr
);
464 } else if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
465 X
.needs(MDU
, MultDivUnit::StartMultDiv
);
467 X
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
471 if (!inst
->isNonSpeculative()) {
472 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
473 M
.needs(MDU
, MultDivUnit::EndMultDiv
);
476 if ( inst
->isLoad() ) {
477 M
.needs(DCache
, CacheUnit::InitiateReadData
);
479 M
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
480 } else if ( inst
->isStore() ) {
481 for (int i
= 1; i
< inst
->numSrcRegs(); i
++ ) {
482 M
.needs(RegManager
, UseDefUnit::ReadSrcReg
, i
);
484 M
.needs(AGEN
, AGENUnit::GenerateAddr
);
485 M
.needs(DCache
, CacheUnit::InitiateWriteData
);
487 M
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
492 if (!inst
->isNonSpeculative()) {
493 if ( inst
->isLoad() ) {
494 W
.needs(DCache
, CacheUnit::CompleteReadData
);
496 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
497 } else if ( inst
->isStore() ) {
498 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
500 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
503 // Finally, Execute Speculative Data
504 if (inst
->isMemRef()) {
505 if (inst
->isLoad()) {
506 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
507 W
.needs(DCache
, CacheUnit::InitiateReadData
);
509 W
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
510 W
.needs(DCache
, CacheUnit::CompleteReadData
);
512 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
513 } else if (inst
->isStore()) {
514 if ( inst
->numSrcRegs() >= 2 ) {
515 W
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
517 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
518 W
.needs(DCache
, CacheUnit::InitiateWriteData
);
520 W
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
521 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
523 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
526 W
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
530 W
.needs(Grad
, GraduationUnit::CheckFault
);
532 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
533 W
.needs(RegManager
, UseDefUnit::WriteDestReg
, idx
);
536 if (inst
->isControl())
537 W
.needs(BPred
, BranchPredictor::UpdatePredictor
);
539 W
.needs(Grad
, GraduationUnit::GraduateInst
);
541 // Insert Back Schedule into our cache of
542 // resource schedules
543 addToSkedCache(inst
, res_sked
);
545 DPRINTF(SkedCache
, "Back End Sked Created for instruction: %s (%08p)\n",
546 inst
->instName(), inst
->getMachInst());
553 InOrderCPU::regStats()
555 /* Register the Resource Pool's stats here.*/
558 /* Register for each Pipeline Stage */
559 for (int stage_num
=0; stage_num
< ThePipeline::NumStages
; stage_num
++) {
560 pipelineStage
[stage_num
]->regStats();
563 /* Register any of the InOrderCPU's stats here.*/
565 .name(name() + ".instsPerContextSwitch")
566 .desc("Instructions Committed Per Context Switch")
567 .prereq(instsPerCtxtSwitch
);
570 .name(name() + ".contextSwitches")
571 .desc("Number of context switches");
574 .name(name() + ".comLoads")
575 .desc("Number of Load instructions committed");
578 .name(name() + ".comStores")
579 .desc("Number of Store instructions committed");
582 .name(name() + ".comBranches")
583 .desc("Number of Branches instructions committed");
586 .name(name() + ".comNops")
587 .desc("Number of Nop instructions committed");
590 .name(name() + ".comNonSpec")
591 .desc("Number of Non-Speculative instructions committed");
594 .name(name() + ".comInts")
595 .desc("Number of Integer instructions committed");
598 .name(name() + ".comFloats")
599 .desc("Number of Floating Point instructions committed");
602 .name(name() + ".timesIdled")
603 .desc("Number of times that the entire CPU went into an idle state and"
604 " unscheduled itself")
608 .name(name() + ".idleCycles")
609 .desc("Number of cycles cpu's stages were not processed");
612 .name(name() + ".runCycles")
613 .desc("Number of cycles cpu stages are processed.");
616 .name(name() + ".activity")
617 .desc("Percentage of cycles cpu is active")
619 activity
= (runCycles
/ numCycles
) * 100;
623 .name(name() + ".threadCycles")
624 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
627 .name(name() + ".smtCycles")
628 .desc("Total number of cycles that the CPU was in SMT-mode");
632 .name(name() + ".committedInsts")
633 .desc("Number of Instructions Simulated (Per-Thread)");
637 .name(name() + ".smtCommittedInsts")
638 .desc("Number of SMT Instructions Simulated (Per-Thread)");
641 .name(name() + ".committedInsts_total")
642 .desc("Number of Instructions Simulated (Total)");
645 .name(name() + ".cpi")
646 .desc("CPI: Cycles Per Instruction (Per-Thread)")
648 cpi
= numCycles
/ committedInsts
;
651 .name(name() + ".smt_cpi")
652 .desc("CPI: Total SMT-CPI")
654 smtCpi
= smtCycles
/ smtCommittedInsts
;
657 .name(name() + ".cpi_total")
658 .desc("CPI: Total CPI of All Threads")
660 totalCpi
= numCycles
/ totalCommittedInsts
;
663 .name(name() + ".ipc")
664 .desc("IPC: Instructions Per Cycle (Per-Thread)")
666 ipc
= committedInsts
/ numCycles
;
669 .name(name() + ".smt_ipc")
670 .desc("IPC: Total SMT-IPC")
672 smtIpc
= smtCommittedInsts
/ smtCycles
;
675 .name(name() + ".ipc_total")
676 .desc("IPC: Total IPC of All Threads")
678 totalIpc
= totalCommittedInsts
/ numCycles
;
687 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
691 bool pipes_idle
= true;
693 //Tick each of the stages
694 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
695 pipelineStage
[stNum
]->tick();
697 pipes_idle
= pipes_idle
&& pipelineStage
[stNum
]->idle
;
700 checkForInterrupts();
707 // Now advance the time buffers one tick
708 timeBuffer
.advance();
709 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
710 stageQueue
[sqNum
]->advance();
712 activityRec
.advance();
714 // Any squashed events, or insts then remove them now
715 cleanUpRemovedEvents();
716 cleanUpRemovedInsts();
718 // Re-schedule CPU for this cycle
719 if (!tickEvent
.scheduled()) {
720 if (_status
== SwitchedOut
) {
722 lastRunningCycle
= curTick();
723 } else if (!activityRec
.active()) {
724 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
725 lastRunningCycle
= curTick();
728 //Tick next_tick = curTick() + cycles(1);
729 //tickEvent.schedule(next_tick);
730 schedule(&tickEvent
, nextCycle(curTick() + 1));
731 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n",
732 nextCycle(curTick() + 1));
737 updateThreadPriority();
744 if (!deferRegistration
) {
745 registerThreadContexts();
748 // Set inSyscall so that the CPU doesn't squash when initially
749 // setting up registers.
750 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
751 thread
[tid
]->inSyscall
= true;
754 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
755 ThreadContext
*src_tc
= threadContexts
[tid
];
756 TheISA::initCPU(src_tc
, src_tc
->contextId());
761 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
762 thread
[tid
]->inSyscall
= false;
764 // Call Initializiation Routine for Resource Pool
769 InOrderCPU::getPort(const std::string
&if_name
, int idx
)
771 return resPool
->getPort(if_name
, idx
);
776 InOrderCPU::hwrei(ThreadID tid
)
778 #if THE_ISA == ALPHA_ISA
779 // Need to clear the lock flag upon returning from an interrupt.
780 setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG
, false, tid
);
782 thread
[tid
]->kernelStats
->hwrei();
783 // FIXME: XXX check for interrupts? XXX
791 InOrderCPU::simPalCheck(int palFunc
, ThreadID tid
)
793 #if THE_ISA == ALPHA_ISA
794 if (this->thread
[tid
]->kernelStats
)
795 this->thread
[tid
]->kernelStats
->callpal(palFunc
,
796 this->threadContexts
[tid
]);
801 if (--System::numSystemsRunning
== 0)
802 exitSimLoop("all cpus halted");
807 if (this->system
->breakpoint())
816 InOrderCPU::checkForInterrupts()
818 for (int i
= 0; i
< threadContexts
.size(); i
++) {
819 ThreadContext
*tc
= threadContexts
[i
];
821 if (interrupts
->checkInterrupts(tc
)) {
822 Fault interrupt
= interrupts
->getInterrupt(tc
);
824 if (interrupt
!= NoFault
) {
825 DPRINTF(Interrupt
, "Processing Intterupt for [tid:%i].\n",
828 ThreadID tid
= tc
->threadId();
829 interrupts
->updateIntrInfo(tc
);
831 // Squash from Last Stage in Pipeline
832 unsigned last_stage
= NumStages
- 1;
833 dummyTrapInst
[tid
]->squashingStage
= last_stage
;
834 pipelineStage
[last_stage
]->setupSquash(dummyTrapInst
[tid
],
837 // By default, setupSquash will always squash from stage + 1
838 pipelineStage
[BackEndStartStage
- 1]->setupSquash(dummyTrapInst
[tid
],
841 // Schedule Squash Through-out Resource Pool
842 resPool
->scheduleEvent(
843 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
,
844 dummyTrapInst
[tid
], 0);
846 // Finally, Setup Trap to happen at end of cycle
847 trapContext(interrupt
, tid
, dummyTrapInst
[tid
]);
854 InOrderCPU::getInterrupts()
856 // Check if there are any outstanding interrupts
857 return interrupts
->getInterrupt(threadContexts
[0]);
862 InOrderCPU::processInterrupts(Fault interrupt
)
864 // Check for interrupts here. For now can copy the code that
865 // exists within isa_fullsys_traits.hh. Also assume that thread 0
866 // is the one that handles the interrupts.
867 // @todo: Possibly consolidate the interrupt checking code.
868 // @todo: Allow other threads to handle interrupts.
870 assert(interrupt
!= NoFault
);
871 interrupts
->updateIntrInfo(threadContexts
[0]);
873 DPRINTF(InOrderCPU
, "Interrupt %s being handled\n", interrupt
->name());
875 // Note: Context ID ok here? Impl. of FS mode needs to revisit this
876 trap(interrupt
, threadContexts
[0]->contextId(), dummyBufferInst
);
881 InOrderCPU::updateMemPorts()
883 // Update all ThreadContext's memory ports (Functional/Virtual
885 ThreadID size
= thread
.size();
886 for (ThreadID i
= 0; i
< size
; ++i
)
887 thread
[i
]->connectMemPorts(thread
[i
]->getTC());
892 InOrderCPU::trapContext(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
894 scheduleCpuEvent(Trap
, fault
, tid
, inst
, delay
);
898 InOrderCPU::trap(Fault fault
, ThreadID tid
, DynInstPtr inst
)
900 fault
->invoke(tcBase(tid
), inst
->staticInst
);
901 removePipelineStalls(tid
);
905 InOrderCPU::squashFromMemStall(DynInstPtr inst
, ThreadID tid
, int delay
)
907 scheduleCpuEvent(SquashFromMemStall
, NoFault
, tid
, inst
, delay
);
912 InOrderCPU::squashDueToMemStall(int stage_num
, InstSeqNum seq_num
,
915 DPRINTF(InOrderCPU
, "Squashing Pipeline Stages Due to Memory Stall...\n");
917 // Squash all instructions in each stage including
918 // instruction that caused the squash (seq_num - 1)
919 // NOTE: The stage bandwidth needs to be cleared so thats why
920 // the stalling instruction is squashed as well. The stalled
921 // instruction is previously placed in another intermediate buffer
922 // while it's stall is being handled.
923 InstSeqNum squash_seq_num
= seq_num
- 1;
925 for (int stNum
=stage_num
; stNum
>= 0 ; stNum
--) {
926 pipelineStage
[stNum
]->squashDueToMemStall(squash_seq_num
, tid
);
931 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
932 ThreadID tid
, DynInstPtr inst
,
933 unsigned delay
, CPUEventPri event_pri
)
935 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, inst
,
938 Tick sked_tick
= nextCycle(curTick() + ticks(delay
));
940 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
941 eventNames
[c_event
], curTick() + delay
, tid
);
942 schedule(cpu_event
, sked_tick
);
944 cpu_event
->process();
945 cpuEventRemoveList
.push(cpu_event
);
948 // Broadcast event to the Resource Pool
949 // Need to reset tid just in case this is a dummy instruction
951 resPool
->scheduleEvent(c_event
, inst
, 0, 0, tid
);
955 InOrderCPU::isThreadActive(ThreadID tid
)
957 list
<ThreadID
>::iterator isActive
=
958 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
960 return (isActive
!= activeThreads
.end());
964 InOrderCPU::isThreadReady(ThreadID tid
)
966 list
<ThreadID
>::iterator isReady
=
967 std::find(readyThreads
.begin(), readyThreads
.end(), tid
);
969 return (isReady
!= readyThreads
.end());
973 InOrderCPU::isThreadSuspended(ThreadID tid
)
975 list
<ThreadID
>::iterator isSuspended
=
976 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
978 return (isSuspended
!= suspendedThreads
.end());
982 InOrderCPU::activateNextReadyThread()
984 if (readyThreads
.size() >= 1) {
985 ThreadID ready_tid
= readyThreads
.front();
987 // Activate in Pipeline
988 activateThread(ready_tid
);
990 // Activate in Resource Pool
991 resPool
->activateThread(ready_tid
);
993 list
<ThreadID
>::iterator ready_it
=
994 std::find(readyThreads
.begin(), readyThreads
.end(), ready_tid
);
995 readyThreads
.erase(ready_it
);
998 "Attempting to activate new thread, but No Ready Threads to"
1001 "Unable to switch to next active thread.\n");
1006 InOrderCPU::activateThread(ThreadID tid
)
1008 if (isThreadSuspended(tid
)) {
1010 "Removing [tid:%i] from suspended threads list.\n", tid
);
1012 list
<ThreadID
>::iterator susp_it
=
1013 std::find(suspendedThreads
.begin(), suspendedThreads
.end(),
1015 suspendedThreads
.erase(susp_it
);
1018 if (threadModel
== SwitchOnCacheMiss
&&
1019 numActiveThreads() == 1) {
1021 "Ignoring activation of [tid:%i], since [tid:%i] is "
1022 "already running.\n", tid
, activeThreadId());
1024 DPRINTF(InOrderCPU
,"Placing [tid:%i] on ready threads list\n",
1027 readyThreads
.push_back(tid
);
1029 } else if (!isThreadActive(tid
)) {
1031 "Adding [tid:%i] to active threads list.\n", tid
);
1032 activeThreads
.push_back(tid
);
1034 activateThreadInPipeline(tid
);
1036 thread
[tid
]->lastActivate
= curTick();
1038 tcBase(tid
)->setStatus(ThreadContext::Active
);
1047 InOrderCPU::activateThreadInPipeline(ThreadID tid
)
1049 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
1050 pipelineStage
[stNum
]->activateThread(tid
);
1055 InOrderCPU::deactivateContext(ThreadID tid
, int delay
)
1057 DPRINTF(InOrderCPU
,"[tid:%i]: Deactivating ...\n", tid
);
1059 scheduleCpuEvent(DeactivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1061 // Be sure to signal that there's some activity so the CPU doesn't
1062 // deschedule itself.
1063 activityRec
.activity();
1069 InOrderCPU::deactivateThread(ThreadID tid
)
1071 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
1073 if (isThreadActive(tid
)) {
1074 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
1076 list
<ThreadID
>::iterator thread_it
=
1077 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
1079 removePipelineStalls(*thread_it
);
1081 activeThreads
.erase(thread_it
);
1083 // Ideally, this should be triggered from the
1084 // suspendContext/Thread functions
1085 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1088 assert(!isThreadActive(tid
));
1092 InOrderCPU::removePipelineStalls(ThreadID tid
)
1094 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
1097 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
1098 pipelineStage
[stNum
]->removeStalls(tid
);
1104 InOrderCPU::updateThreadPriority()
1106 if (activeThreads
.size() > 1)
1108 //DEFAULT TO ROUND ROBIN SCHEME
1109 //e.g. Move highest priority to end of thread list
1110 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
1111 list
<ThreadID
>::iterator list_end
= activeThreads
.end();
1113 unsigned high_thread
= *list_begin
;
1115 activeThreads
.erase(list_begin
);
1117 activeThreads
.push_back(high_thread
);
1122 InOrderCPU::tickThreadStats()
1124 /** Keep track of cycles that each thread is active */
1125 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
1126 while (thread_it
!= activeThreads
.end()) {
1127 threadCycles
[*thread_it
]++;
1131 // Keep track of cycles where SMT is active
1132 if (activeThreads
.size() > 1) {
1138 InOrderCPU::activateContext(ThreadID tid
, int delay
)
1140 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
1143 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1145 // Be sure to signal that there's some activity so the CPU doesn't
1146 // deschedule itself.
1147 activityRec
.activity();
1153 InOrderCPU::activateNextReadyContext(int delay
)
1155 DPRINTF(InOrderCPU
,"Activating next ready thread\n");
1157 scheduleCpuEvent(ActivateNextReadyThread
, NoFault
, 0/*tid*/, dummyInst
[0],
1158 delay
, ActivateNextReadyThread_Pri
);
1160 // Be sure to signal that there's some activity so the CPU doesn't
1161 // deschedule itself.
1162 activityRec
.activity();
1168 InOrderCPU::haltContext(ThreadID tid
, int delay
)
1170 DPRINTF(InOrderCPU
, "[tid:%i]: Calling Halt Context...\n", tid
);
1172 scheduleCpuEvent(HaltThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1174 activityRec
.activity();
1178 InOrderCPU::haltThread(ThreadID tid
)
1180 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Halted Threads List...\n", tid
);
1181 deactivateThread(tid
);
1182 squashThreadInPipeline(tid
);
1183 haltedThreads
.push_back(tid
);
1185 tcBase(tid
)->setStatus(ThreadContext::Halted
);
1187 if (threadModel
== SwitchOnCacheMiss
) {
1188 activateNextReadyContext();
1193 InOrderCPU::suspendContext(ThreadID tid
, int delay
)
1195 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1199 InOrderCPU::suspendThread(ThreadID tid
)
1201 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Suspended Threads List...\n",
1203 deactivateThread(tid
);
1204 suspendedThreads
.push_back(tid
);
1205 thread
[tid
]->lastSuspend
= curTick();
1207 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1211 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
1213 //Squash all instructions in each stage
1214 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
1215 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
1220 InOrderCPU::getPipeStage(int stage_num
)
1222 return pipelineStage
[stage_num
];
1227 InOrderCPU::flattenRegIdx(RegIndex reg_idx
, RegType
®_type
, ThreadID tid
)
1229 if (reg_idx
< FP_Base_DepTag
) {
1231 return isa
[tid
].flattenIntIndex(reg_idx
);
1232 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1233 reg_type
= FloatType
;
1234 reg_idx
-= FP_Base_DepTag
;
1235 return isa
[tid
].flattenFloatIndex(reg_idx
);
1237 reg_type
= MiscType
;
1238 return reg_idx
- TheISA::Ctrl_Base_DepTag
;
1243 InOrderCPU::readIntReg(RegIndex reg_idx
, ThreadID tid
)
1245 DPRINTF(IntRegs
, "[tid:%i]: Reading Int. Reg %i as %x\n",
1246 tid
, reg_idx
, intRegs
[tid
][reg_idx
]);
1248 return intRegs
[tid
][reg_idx
];
1252 InOrderCPU::readFloatReg(RegIndex reg_idx
, ThreadID tid
)
1254 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1255 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1257 return floatRegs
.f
[tid
][reg_idx
];
1261 InOrderCPU::readFloatRegBits(RegIndex reg_idx
, ThreadID tid
)
1263 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1264 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1266 return floatRegs
.i
[tid
][reg_idx
];
1270 InOrderCPU::setIntReg(RegIndex reg_idx
, uint64_t val
, ThreadID tid
)
1272 if (reg_idx
== TheISA::ZeroReg
) {
1273 DPRINTF(IntRegs
, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1274 "(Int. Reg %i) to %x\n", tid
, reg_idx
, val
);
1277 DPRINTF(IntRegs
, "[tid:%i]: Setting Int. Reg %i to %x\n",
1280 intRegs
[tid
][reg_idx
] = val
;
1286 InOrderCPU::setFloatReg(RegIndex reg_idx
, FloatReg val
, ThreadID tid
)
1288 floatRegs
.f
[tid
][reg_idx
] = val
;
1289 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1292 floatRegs
.i
[tid
][reg_idx
],
1293 floatRegs
.f
[tid
][reg_idx
]);
1298 InOrderCPU::setFloatRegBits(RegIndex reg_idx
, FloatRegBits val
, ThreadID tid
)
1300 floatRegs
.i
[tid
][reg_idx
] = val
;
1301 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1304 floatRegs
.i
[tid
][reg_idx
],
1305 floatRegs
.f
[tid
][reg_idx
]);
1309 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
1311 // If Default value is set, then retrieve target thread
1312 if (tid
== InvalidThreadID
) {
1313 tid
= TheISA::getTargetThread(tcBase(tid
));
1316 if (reg_idx
< FP_Base_DepTag
) {
1317 // Integer Register File
1318 return readIntReg(reg_idx
, tid
);
1319 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1320 // Float Register File
1321 reg_idx
-= FP_Base_DepTag
;
1322 return readFloatRegBits(reg_idx
, tid
);
1324 reg_idx
-= Ctrl_Base_DepTag
;
1325 return readMiscReg(reg_idx
, tid
); // Misc. Register File
1329 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
1332 // If Default value is set, then retrieve target thread
1333 if (tid
== InvalidThreadID
) {
1334 tid
= TheISA::getTargetThread(tcBase(tid
));
1337 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
1338 setIntReg(reg_idx
, val
, tid
);
1339 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
1340 reg_idx
-= FP_Base_DepTag
;
1341 setFloatRegBits(reg_idx
, val
, tid
);
1343 reg_idx
-= Ctrl_Base_DepTag
;
1344 setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
1349 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1351 return isa
[tid
].readMiscRegNoEffect(misc_reg
);
1355 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
1357 DPRINTF(InOrderCPU
, "MiscReg: %i\n", misc_reg
);
1358 DPRINTF(InOrderCPU
, "tid: %i\n", tid
);
1359 DPRINTF(InOrderCPU
, "tcBase: %x\n", tcBase(tid
));
1360 DPRINTF(InOrderCPU
, "isa-tid: %x\n", &isa
[tid
]);
1362 return isa
[tid
].readMiscReg(misc_reg
, tcBase(tid
));
1366 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1368 isa
[tid
].setMiscRegNoEffect(misc_reg
, val
);
1372 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1374 isa
[tid
].setMiscReg(misc_reg
, val
, tcBase(tid
));
1379 InOrderCPU::addInst(DynInstPtr inst
)
1381 ThreadID tid
= inst
->readTid();
1383 instList
[tid
].push_back(inst
);
1385 return --(instList
[tid
].end());
1389 InOrderCPU::findInst(InstSeqNum seq_num
, ThreadID tid
)
1391 ListIt it
= instList
[tid
].begin();
1392 ListIt end
= instList
[tid
].end();
1395 if ((*it
)->seqNum
== seq_num
)
1397 else if ((*it
)->seqNum
> seq_num
)
1403 return instList
[tid
].end();
1407 InOrderCPU::updateContextSwitchStats()
1409 // Set Average Stat Here, then reset to 0
1410 instsPerCtxtSwitch
= instsPerSwitch
;
1416 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1418 // Set the nextPC to be fetched if this is the last instruction
1421 // This contributes to the precise state of the CPU
1422 // which can be used when restoring a thread to the CPU after after any
1423 // type of context switching activity (fork, exception, etc.)
1424 TheISA::PCState comm_pc
= inst
->pcState();
1425 lastCommittedPC
[tid
] = comm_pc
;
1426 TheISA::advancePC(comm_pc
, inst
->staticInst
);
1427 pcState(comm_pc
, tid
);
1429 //@todo: may be unnecessary with new-ISA-specific branch handling code
1430 if (inst
->isControl()) {
1431 thread
[tid
]->lastGradIsBranch
= true;
1432 thread
[tid
]->lastBranchPC
= inst
->pcState();
1433 TheISA::advancePC(thread
[tid
]->lastBranchPC
, inst
->staticInst
);
1435 thread
[tid
]->lastGradIsBranch
= false;
1439 // Finalize Trace Data For Instruction
1440 if (inst
->traceData
) {
1441 //inst->traceData->setCycle(curTick());
1442 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1443 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1444 inst
->traceData
->dump();
1445 delete inst
->traceData
;
1446 inst
->traceData
= NULL
;
1449 // Increment active thread's instruction count
1452 // Increment thread-state's instruction count
1453 thread
[tid
]->numInst
++;
1455 // Increment thread-state's instruction stats
1456 thread
[tid
]->numInsts
++;
1458 // Count committed insts per thread stats
1459 committedInsts
[tid
]++;
1461 // Count total insts committed stat
1462 totalCommittedInsts
++;
1464 // Count SMT-committed insts per thread stat
1465 if (numActiveThreads() > 1) {
1466 smtCommittedInsts
[tid
]++;
1469 // Instruction-Mix Stats
1470 if (inst
->isLoad()) {
1472 } else if (inst
->isStore()) {
1474 } else if (inst
->isControl()) {
1476 } else if (inst
->isNop()) {
1478 } else if (inst
->isNonSpeculative()) {
1480 } else if (inst
->isInteger()) {
1482 } else if (inst
->isFloating()) {
1486 // Check for instruction-count-based events.
1487 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numInst
);
1489 // Finally, remove instruction from CPU
1493 // currently unused function, but substitute repetitive code w/this function
1496 InOrderCPU::addToRemoveList(DynInstPtr inst
)
1498 removeInstsThisCycle
= true;
1499 if (!inst
->isRemoveList()) {
1500 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1501 "[sn:%lli] to remove list\n",
1502 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1503 inst
->setRemoveList();
1504 removeList
.push(inst
->getInstListIt());
1506 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1507 "[sn:%lli], already remove list\n",
1508 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1514 InOrderCPU::removeInst(DynInstPtr inst
)
1516 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %s "
1518 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1520 removeInstsThisCycle
= true;
1522 // Remove the instruction.
1523 if (!inst
->isRemoveList()) {
1524 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1525 "[sn:%lli] to remove list\n",
1526 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1527 inst
->setRemoveList();
1528 removeList
.push(inst
->getInstListIt());
1530 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1531 "[sn:%lli], already on remove list\n",
1532 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1538 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1540 //assert(!instList[tid].empty());
1542 removeInstsThisCycle
= true;
1544 ListIt inst_iter
= instList
[tid
].end();
1548 DPRINTF(InOrderCPU
, "Squashing instructions from CPU instruction "
1549 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1550 tid
, seq_num
, (*inst_iter
)->seqNum
);
1552 while ((*inst_iter
)->seqNum
> seq_num
) {
1554 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1556 squashInstIt(inst_iter
, tid
);
1567 InOrderCPU::squashInstIt(const ListIt inst_it
, ThreadID tid
)
1569 DynInstPtr inst
= (*inst_it
);
1570 if (inst
->threadNumber
== tid
) {
1571 DPRINTF(InOrderCPU
, "Squashing instruction, "
1572 "[tid:%i] [sn:%lli] PC %s\n",
1577 inst
->setSquashed();
1578 archRegDepMap
[tid
].remove(inst
);
1580 if (!inst
->isRemoveList()) {
1581 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1582 "[sn:%lli] to remove list\n",
1583 inst
->threadNumber
, inst
->pcState(),
1585 inst
->setRemoveList();
1586 removeList
.push(inst_it
);
1588 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i]"
1589 " PC %s [sn:%lli], already on remove list\n",
1590 inst
->threadNumber
, inst
->pcState(),
1600 InOrderCPU::cleanUpRemovedInsts()
1602 while (!removeList
.empty()) {
1603 DPRINTF(InOrderCPU
, "Removing instruction, "
1604 "[tid:%i] [sn:%lli] PC %s\n",
1605 (*removeList
.front())->threadNumber
,
1606 (*removeList
.front())->seqNum
,
1607 (*removeList
.front())->pcState());
1609 DynInstPtr inst
= *removeList
.front();
1610 ThreadID tid
= inst
->threadNumber
;
1612 // Remove From Register Dependency Map, If Necessary
1613 // archRegDepMap[tid].remove(inst);
1615 // Clear if Non-Speculative
1616 if (inst
->staticInst
&&
1617 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1618 nonSpecInstActive
[tid
] == true) {
1619 nonSpecInstActive
[tid
] = false;
1622 inst
->onInstList
= false;
1624 instList
[tid
].erase(removeList
.front());
1629 removeInstsThisCycle
= false;
1633 InOrderCPU::cleanUpRemovedEvents()
1635 while (!cpuEventRemoveList
.empty()) {
1636 Event
*cpu_event
= cpuEventRemoveList
.front();
1637 cpuEventRemoveList
.pop();
1644 InOrderCPU::dumpInsts()
1648 ListIt inst_list_it
= instList
[0].begin();
1650 cprintf("Dumping Instruction List\n");
1652 while (inst_list_it
!= instList
[0].end()) {
1653 cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1655 num
, (*inst_list_it
)->pcState(),
1656 (*inst_list_it
)->threadNumber
,
1657 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1658 (*inst_list_it
)->isSquashed());
1665 InOrderCPU::wakeCPU()
1667 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1668 DPRINTF(Activity
, "CPU already running.\n");
1672 DPRINTF(Activity
, "Waking up CPU\n");
1674 Tick extra_cycles
= tickToCycles((curTick() - 1) - lastRunningCycle
);
1676 idleCycles
+= extra_cycles
;
1677 for (int stage_num
= 0; stage_num
< NumStages
; stage_num
++) {
1678 pipelineStage
[stage_num
]->idleCycles
+= extra_cycles
;
1681 numCycles
+= extra_cycles
;
1683 schedule(&tickEvent
, nextCycle(curTick()));
1687 // Lots of copied full system code...place into BaseCPU class?
1689 InOrderCPU::wakeup()
1691 if (thread
[0]->status() != ThreadContext::Suspended
)
1696 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1697 threadContexts
[0]->activate();
1703 InOrderCPU::syscallContext(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
1705 //@todo: squash behind syscall
1706 scheduleCpuEvent(Syscall
, fault
, tid
, inst
, delay
, Syscall_Pri
);
1710 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1712 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1714 DPRINTF(Activity
,"Activity: syscall() called.\n");
1716 // Temporarily increase this by one to account for the syscall
1718 ++(this->thread
[tid
]->funcExeInst
);
1720 // Execute the actual syscall.
1721 this->thread
[tid
]->syscall(callnum
);
1723 // Decrease funcExeInst by one as the normal commit will handle
1725 --(this->thread
[tid
]->funcExeInst
);
1727 // Clear Non-Speculative Block Variable
1728 nonSpecInstActive
[tid
] = false;
1733 InOrderCPU::getITBPtr()
1735 CacheUnit
*itb_res
=
1736 dynamic_cast<CacheUnit
*>(resPool
->getResource(fetchPortIdx
));
1737 return itb_res
->tlb();
1742 InOrderCPU::getDTBPtr()
1744 CacheUnit
*dtb_res
=
1745 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1746 return dtb_res
->tlb();
1750 InOrderCPU::read(DynInstPtr inst
, Addr addr
,
1751 uint8_t *data
, unsigned size
, unsigned flags
)
1753 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1754 // you want to run w/out caches?
1755 CacheUnit
*cache_res
=
1756 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1758 return cache_res
->read(inst
, addr
, data
, size
, flags
);
1762 InOrderCPU::write(DynInstPtr inst
, uint8_t *data
, unsigned size
,
1763 Addr addr
, unsigned flags
, uint64_t *write_res
)
1765 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1766 // you want to run w/out caches?
1767 CacheUnit
*cache_res
=
1768 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1769 return cache_res
->write(inst
, data
, size
, addr
, flags
, write_res
);