src/cpu/inorder/cpu.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <algorithm>
  33
  34 #include "arch/utility.hh"
  35 #include "config/full_system.hh"
  36 #include "config/the_isa.hh"
  37 #include "cpu/activity.hh"
  38 #include "cpu/base.hh"
  39 #include "cpu/exetrace.hh"
  40 #include "cpu/inorder/cpu.hh"
  41 #include "cpu/inorder/first_stage.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource_pool.hh"
  45 #include "cpu/inorder/resources/resource_list.hh"
  46 #include "cpu/inorder/thread_context.hh"
  47 #include "cpu/inorder/thread_state.hh"
  48 #include "cpu/simple_thread.hh"
  49 #include "cpu/thread_context.hh"
  50 #include "mem/translating_port.hh"
  51 #include "params/InOrderCPU.hh"
  52 #include "sim/process.hh"
  53 #include "sim/stat_control.hh"
  54
  55 #if FULL_SYSTEM
  56 #include "cpu/quiesce_event.hh"
  57 #include "sim/system.hh"
  58 #endif
  59
  60 #if THE_ISA == ALPHA_ISA
  61 #include "arch/alpha/osfpal.hh"
  62 #endif
  63
  64 using namespace std;
  65 using namespace TheISA;
  66 using namespace ThePipeline;
  67
  68 InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
  69   : Event(CPU_Tick_Pri), cpu(c)
  70 { }
  71
  72
  73 void
  74 InOrderCPU::TickEvent::process()
  75 {
  76     cpu->tick();
  77 }
  78
  79
  80 const char *
  81 InOrderCPU::TickEvent::description()
  82 {
  83     return "InOrderCPU tick event";
  84 }
  85
  86 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
  87                                Fault fault, ThreadID _tid, DynInstPtr inst,
  88                                unsigned event_pri_offset)
  89     : Event(Event::Priority((unsigned int)CPU_Tick_Pri + event_pri_offset)),
  90       cpu(_cpu)
  91 {
  92     setEvent(e_type, fault, _tid, inst);
  93 }
  94
  95
  96 std::string InOrderCPU::eventNames[NumCPUEvents] =
  97 {
  98     "ActivateThread",
  99     "ActivateNextReadyThread",
 100     "DeactivateThread",
 101     "HaltThread",
 102     "SuspendThread",
 103     "Trap",
 104     "InstGraduated",
 105     "SquashFromMemStall",
 106     "UpdatePCs"
 107 };
 108
 109 void
 110 InOrderCPU::CPUEvent::process()
 111 {
 112     switch (cpuEventType)
 113     {
 114       case ActivateThread:
 115         cpu->activateThread(tid);
 116         break;
 117
 118       case ActivateNextReadyThread:
 119         cpu->activateNextReadyThread();
 120         break;
 121
 122       case DeactivateThread:
 123         cpu->deactivateThread(tid);
 124         break;
 125
 126       case HaltThread:
 127         cpu->haltThread(tid);
 128         break;
 129
 130       case SuspendThread:
 131         cpu->suspendThread(tid);
 132         break;
 133
 134       case SquashFromMemStall:
 135         cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
 136         break;
 137
 138       case Trap:
 139         cpu->trapCPU(fault, tid, inst);
 140         break;
 141
 142       default:
 143         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
 144     }
 145
 146     cpu->cpuEventRemoveList.push(this);
 147 }
 148
 149
 150
 151 const char *
 152 InOrderCPU::CPUEvent::description()
 153 {
 154     return "InOrderCPU event";
 155 }
 156
 157 void
 158 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 159 {
 160     assert(!scheduled() || squashed());
 161     cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
 162 }
 163
 164 void
 165 InOrderCPU::CPUEvent::unscheduleEvent()
 166 {
 167     if (scheduled())
 168         squash();
 169 }
 170
 171 InOrderCPU::InOrderCPU(Params *params)
 172     : BaseCPU(params),
 173       cpu_id(params->cpu_id),
 174       coreType("default"),
 175       _status(Idle),
 176       tickEvent(this),
 177       stageWidth(params->stageWidth),
 178       timeBuffer(2 , 2),
 179       removeInstsThisCycle(false),
 180       activityRec(params->name, NumStages, 10, params->activity),
 181 #if FULL_SYSTEM
 182       system(params->system),
 183       physmem(system->physmem),
 184 #endif // FULL_SYSTEM
 185 #ifdef DEBUG
 186       cpuEventNum(0),
 187       resReqCount(0),
 188 #endif // DEBUG
 189       switchCount(0),
 190       deferRegistration(false/*params->deferRegistration*/),
 191       stageTracing(params->stageTracing),
 192       instsPerSwitch(0)
 193 {
 194     ThreadID active_threads;
 195     cpu_params = params;
 196
 197     resPool = new ResourcePool(this, params);
 198
 199     // Resize for Multithreading CPUs
 200     thread.resize(numThreads);
 201
 202 #if FULL_SYSTEM
 203     active_threads = 1;
 204 #else
 205     active_threads = params->workload.size();
 206
 207     if (active_threads > MaxThreads) {
 208         panic("Workload Size too large. Increase the 'MaxThreads'"
 209               "in your InOrder implementation or "
 210               "edit your workload size.");
 211     }
 212
 213
 214     if (active_threads > 1) {
 215         threadModel = (InOrderCPU::ThreadModel) params->threadModel;
 216
 217         if (threadModel == SMT) {
 218             DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
 219         } else if (threadModel == SwitchOnCacheMiss) {
 220             DPRINTF(InOrderCPU, "Setting Thread Model to "
 221                     "Switch On Cache Miss\n");
 222         }
 223
 224     } else {
 225         threadModel = Single;
 226     }
 227
 228
 229
 230 #endif
 231
 232     // Bind the fetch & data ports from the resource pool.
 233     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
 234     if (fetchPortIdx == 0) {
 235         fatal("Unable to find port to fetch instructions from.\n");
 236     }
 237
 238     dataPortIdx = resPool->getPortIdx(params->dataMemPort);
 239     if (dataPortIdx == 0) {
 240         fatal("Unable to find port for data.\n");
 241     }
 242
 243     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 244 #if FULL_SYSTEM
 245         // SMT is not supported in FS mode yet.
 246         assert(numThreads == 1);
 247         thread[tid] = new Thread(this, 0);
 248 #else
 249         if (tid < (ThreadID)params->workload.size()) {
 250             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
 251                     tid, params->workload[tid]->prog_fname);
 252             thread[tid] =
 253                 new Thread(this, tid, params->workload[tid]);
 254         } else {
 255             //Allocate Empty thread so M5 can use later
 256             //when scheduling threads to CPU
 257             Process* dummy_proc = params->workload[0];
 258             thread[tid] = new Thread(this, tid, dummy_proc);
 259         }
 260
 261         // Eventually set this with parameters...
 262         asid[tid] = tid;
 263 #endif
 264
 265         // Setup the TC that will serve as the interface to the threads/CPU.
 266         InOrderThreadContext *tc = new InOrderThreadContext;
 267         tc->cpu = this;
 268         tc->thread = thread[tid];
 269
 270         // Give the thread the TC.
 271         thread[tid]->tc = tc;
 272         thread[tid]->setFuncExeInst(0);
 273         globalSeqNum[tid] = 1;
 274
 275         // Add the TC to the CPU's list of TC's.
 276         this->threadContexts.push_back(tc);
 277     }
 278
 279     // Initialize TimeBuffer Stage Queues
 280     for (int stNum=0; stNum < NumStages - 1; stNum++) {
 281         stageQueue[stNum] = new StageQueue(NumStages, NumStages);
 282         stageQueue[stNum]->id(stNum);
 283     }
 284
 285
 286     // Set Up Pipeline Stages
 287     for (int stNum=0; stNum < NumStages; stNum++) {
 288         if (stNum == 0)
 289             pipelineStage[stNum] = new FirstStage(params, stNum);
 290         else
 291             pipelineStage[stNum] = new PipelineStage(params, stNum);
 292
 293         pipelineStage[stNum]->setCPU(this);
 294         pipelineStage[stNum]->setActiveThreads(&activeThreads);
 295         pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
 296
 297         // Take Care of 1st/Nth stages
 298         if (stNum > 0)
 299             pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
 300         if (stNum < NumStages - 1)
 301             pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
 302     }
 303
 304     // Initialize thread specific variables
 305     for (ThreadID tid = 0; tid < numThreads; tid++) {
 306         archRegDepMap[tid].setCPU(this);
 307
 308         nonSpecInstActive[tid] = false;
 309         nonSpecSeqNum[tid] = 0;
 310
 311         squashSeqNum[tid] = MaxAddr;
 312         lastSquashCycle[tid] = 0;
 313
 314         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
 315         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
 316         isa[tid].clear();
 317
 318         isa[tid].expandForMultithreading(numThreads, 1/*numVirtProcs*/);
 319
 320         // Define dummy instructions and resource requests to be used.
 321         dummyInst[tid] = new InOrderDynInst(this,
 322                                             thread[tid],
 323                                             0,
 324                                             tid,
 325                                             asid[tid]);
 326
 327         dummyReq[tid] = new ResourceRequest(resPool->getResource(0),
 328                                             dummyInst[tid],
 329                                             0,
 330                                             0,
 331                                             0,
 332                                             0);
 333     }
 334
 335     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 336     dummyReqInst->setSquashed();
 337     dummyReqInst->resetInstCount();
 338
 339     dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
 340     dummyBufferInst->setSquashed();
 341     dummyBufferInst->resetInstCount();
 342
 343     endOfSkedIt = skedCache.end();
 344     frontEndSked = createFrontEndSked();
 345
 346     lastRunningCycle = curTick();
 347
 348     // Reset CPU to reset state.
 349 #if FULL_SYSTEM
 350     Fault resetFault = new ResetFault();
 351     resetFault->invoke(tcBase());
 352 #else
 353     reset();
 354 #endif
 355
 356
 357     // Schedule First Tick Event, CPU will reschedule itself from here on out.
 358     scheduleTickEvent(0);
 359 }
 360
 361 InOrderCPU::~InOrderCPU()
 362 {
 363     delete resPool;
 364 }
 365
 366 std::map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
 367
 368 RSkedPtr
 369 InOrderCPU::createFrontEndSked()
 370 {
 371     RSkedPtr res_sked = new ResourceSked();
 372     int stage_num = 0;
 373     StageScheduler F(res_sked, stage_num++);
 374     StageScheduler D(res_sked, stage_num++);
 375
 376     // FETCH
 377     F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
 378     F.needs(ICache, FetchUnit::InitiateFetch);
 379
 380     // DECODE
 381     D.needs(ICache, FetchUnit::CompleteFetch);
 382     D.needs(Decode, DecodeUnit::DecodeInst);
 383     D.needs(BPred, BranchPredictor::PredictBranch);
 384     D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
 385
 386
 387     DPRINTF(SkedCache, "Resource Sked created for instruction \"front_end\"\n");
 388
 389     return res_sked;
 390 }
 391
 392 RSkedPtr
 393 InOrderCPU::createBackEndSked(DynInstPtr inst)
 394 {
 395     RSkedPtr res_sked = lookupSked(inst);
 396     if (res_sked != NULL) {
 397         DPRINTF(SkedCache, "Found %s in sked cache.\n",
 398                 inst->instName());
 399         return res_sked;
 400     } else {
 401         res_sked = new ResourceSked();
 402     }
 403
 404     int stage_num = ThePipeline::BackEndStartStage;
 405     StageScheduler X(res_sked, stage_num++);
 406     StageScheduler M(res_sked, stage_num++);
 407     StageScheduler W(res_sked, stage_num++);
 408
 409     if (!inst->staticInst) {
 410         warn_once("Static Instruction Object Not Set. Can't Create"
 411                   " Back End Schedule");
 412         return NULL;
 413     }
 414
 415     // EXECUTE
 416     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 417         if (!idx || !inst->isStore()) {
 418             X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
 419         }
 420     }
 421
 422     if ( inst->isNonSpeculative() ) {
 423         // skip execution of non speculative insts until later
 424     } else if ( inst->isMemRef() ) {
 425         if ( inst->isLoad() ) {
 426             X.needs(AGEN, AGENUnit::GenerateAddr);
 427         }
 428     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 429         X.needs(MDU, MultDivUnit::StartMultDiv);
 430     } else {
 431         X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 432     }
 433
 434     if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 435         X.needs(MDU, MultDivUnit::EndMultDiv);
 436     }
 437
 438     // MEMORY
 439     if ( inst->isLoad() ) {
 440         M.needs(DCache, CacheUnit::InitiateReadData);
 441     } else if ( inst->isStore() ) {
 442         if ( inst->numSrcRegs() >= 2 ) {
 443             M.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 444         }
 445         M.needs(AGEN, AGENUnit::GenerateAddr);
 446         M.needs(DCache, CacheUnit::InitiateWriteData);
 447     }
 448
 449
 450     // WRITEBACK
 451     if ( inst->isLoad() ) {
 452         W.needs(DCache, CacheUnit::CompleteReadData);
 453     } else if ( inst->isStore() ) {
 454         W.needs(DCache, CacheUnit::CompleteWriteData);
 455     }
 456
 457     if ( inst->isNonSpeculative() ) {
 458         if ( inst->isMemRef() ) fatal("Non-Speculative Memory Instruction");
 459         W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
 460     }
 461
 462     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 463         W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
 464     }
 465
 466     W.needs(Grad, GraduationUnit::GraduateInst);
 467
 468     // Insert Front Schedule into our cache of
 469     // resource schedules
 470     addToSkedCache(inst, res_sked);
 471
 472     DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
 473             inst->instName(), inst->getMachInst());
 474     res_sked->print();
 475
 476     return res_sked;
 477 }
 478
 479 void
 480 InOrderCPU::regStats()
 481 {
 482     /* Register the Resource Pool's stats here.*/
 483     resPool->regStats();
 484
 485     /* Register for each Pipeline Stage */
 486     for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
 487         pipelineStage[stage_num]->regStats();
 488     }
 489
 490     /* Register any of the InOrderCPU's stats here.*/
 491     instsPerCtxtSwitch
 492         .name(name() + ".instsPerContextSwitch")
 493         .desc("Instructions Committed Per Context Switch")
 494         .prereq(instsPerCtxtSwitch);
 495
 496     numCtxtSwitches
 497         .name(name() + ".contextSwitches")
 498         .desc("Number of context switches");
 499
 500     comLoads
 501         .name(name() + ".comLoads")
 502         .desc("Number of Load instructions committed");
 503
 504     comStores
 505         .name(name() + ".comStores")
 506         .desc("Number of Store instructions committed");
 507
 508     comBranches
 509         .name(name() + ".comBranches")
 510         .desc("Number of Branches instructions committed");
 511
 512     comNops
 513         .name(name() + ".comNops")
 514         .desc("Number of Nop instructions committed");
 515
 516     comNonSpec
 517         .name(name() + ".comNonSpec")
 518         .desc("Number of Non-Speculative instructions committed");
 519
 520     comInts
 521         .name(name() + ".comInts")
 522         .desc("Number of Integer instructions committed");
 523
 524     comFloats
 525         .name(name() + ".comFloats")
 526         .desc("Number of Floating Point instructions committed");
 527
 528     timesIdled
 529         .name(name() + ".timesIdled")
 530         .desc("Number of times that the entire CPU went into an idle state and"
 531               " unscheduled itself")
 532         .prereq(timesIdled);
 533
 534     idleCycles
 535         .name(name() + ".idleCycles")
 536         .desc("Number of cycles cpu's stages were not processed");
 537
 538     runCycles
 539         .name(name() + ".runCycles")
 540         .desc("Number of cycles cpu stages are processed.");
 541
 542     activity
 543         .name(name() + ".activity")
 544         .desc("Percentage of cycles cpu is active")
 545         .precision(6);
 546     activity = (runCycles / numCycles) * 100;
 547
 548     threadCycles
 549         .init(numThreads)
 550         .name(name() + ".threadCycles")
 551         .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
 552
 553     smtCycles
 554         .name(name() + ".smtCycles")
 555         .desc("Total number of cycles that the CPU was in SMT-mode");
 556
 557     committedInsts
 558         .init(numThreads)
 559         .name(name() + ".committedInsts")
 560         .desc("Number of Instructions Simulated (Per-Thread)");
 561
 562     smtCommittedInsts
 563         .init(numThreads)
 564         .name(name() + ".smtCommittedInsts")
 565         .desc("Number of SMT Instructions Simulated (Per-Thread)");
 566
 567     totalCommittedInsts
 568         .name(name() + ".committedInsts_total")
 569         .desc("Number of Instructions Simulated (Total)");
 570
 571     cpi
 572         .name(name() + ".cpi")
 573         .desc("CPI: Cycles Per Instruction (Per-Thread)")
 574         .precision(6);
 575     cpi = numCycles / committedInsts;
 576
 577     smtCpi
 578         .name(name() + ".smt_cpi")
 579         .desc("CPI: Total SMT-CPI")
 580         .precision(6);
 581     smtCpi = smtCycles / smtCommittedInsts;
 582
 583     totalCpi
 584         .name(name() + ".cpi_total")
 585         .desc("CPI: Total CPI of All Threads")
 586         .precision(6);
 587     totalCpi = numCycles / totalCommittedInsts;
 588
 589     ipc
 590         .name(name() + ".ipc")
 591         .desc("IPC: Instructions Per Cycle (Per-Thread)")
 592         .precision(6);
 593     ipc =  committedInsts / numCycles;
 594
 595     smtIpc
 596         .name(name() + ".smt_ipc")
 597         .desc("IPC: Total SMT-IPC")
 598         .precision(6);
 599     smtIpc = smtCommittedInsts / smtCycles;
 600
 601     totalIpc
 602         .name(name() + ".ipc_total")
 603         .desc("IPC: Total IPC of All Threads")
 604         .precision(6);
 605         totalIpc =  totalCommittedInsts / numCycles;
 606
 607     BaseCPU::regStats();
 608 }
 609
 610
 611 void
 612 InOrderCPU::tick()
 613 {
 614     DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
 615
 616     ++numCycles;
 617
 618     bool pipes_idle = true;
 619
 620     //Tick each of the stages
 621     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
 622         pipelineStage[stNum]->tick();
 623
 624         pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
 625     }
 626
 627     if (pipes_idle)
 628         idleCycles++;
 629     else
 630         runCycles++;
 631
 632     // Now advance the time buffers one tick
 633     timeBuffer.advance();
 634     for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
 635         stageQueue[sqNum]->advance();
 636     }
 637     activityRec.advance();
 638
 639     // Any squashed events, or insts then remove them now
 640     cleanUpRemovedEvents();
 641     cleanUpRemovedInsts();
 642
 643     // Re-schedule CPU for this cycle
 644     if (!tickEvent.scheduled()) {
 645         if (_status == SwitchedOut) {
 646             // increment stat
 647             lastRunningCycle = curTick();
 648         } else if (!activityRec.active()) {
 649             DPRINTF(InOrderCPU, "sleeping CPU.\n");
 650             lastRunningCycle = curTick();
 651             timesIdled++;
 652         } else {
 653             //Tick next_tick = curTick() + cycles(1);
 654             //tickEvent.schedule(next_tick);
 655             schedule(&tickEvent, nextCycle(curTick() + 1));
 656             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
 657                     nextCycle(curTick() + 1));
 658         }
 659     }
 660
 661     tickThreadStats();
 662     updateThreadPriority();
 663 }
 664
 665
 666 void
 667 InOrderCPU::init()
 668 {
 669     if (!deferRegistration) {
 670         registerThreadContexts();
 671     }
 672
 673     // Set inSyscall so that the CPU doesn't squash when initially
 674     // setting up registers.
 675     for (ThreadID tid = 0; tid < numThreads; ++tid)
 676         thread[tid]->inSyscall = true;
 677
 678 #if FULL_SYSTEM
 679     for (ThreadID tid = 0; tid < numThreads; tid++) {
 680         ThreadContext *src_tc = threadContexts[tid];
 681         TheISA::initCPU(src_tc, src_tc->contextId());
 682     }
 683 #endif
 684
 685     // Clear inSyscall.
 686     for (ThreadID tid = 0; tid < numThreads; ++tid)
 687         thread[tid]->inSyscall = false;
 688
 689     // Call Initializiation Routine for Resource Pool
 690     resPool->init();
 691 }
 692
 693 void
 694 InOrderCPU::reset()
 695 {
 696     for (int i = 0; i < numThreads; i++) {
 697         isa[i].reset(coreType, numThreads,
 698                      1/*numVirtProcs*/, dynamic_cast<BaseCPU*>(this));
 699     }
 700 }
 701
 702 Port*
 703 InOrderCPU::getPort(const std::string &if_name, int idx)
 704 {
 705     return resPool->getPort(if_name, idx);
 706 }
 707
 708 #if FULL_SYSTEM
 709 Fault
 710 InOrderCPU::hwrei(ThreadID tid)
 711 {
 712     panic("hwrei: Unimplemented");
 713
 714     return NoFault;
 715 }
 716
 717
 718 bool
 719 InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
 720 {
 721     panic("simPalCheck: Unimplemented");
 722
 723     return true;
 724 }
 725
 726
 727 Fault
 728 InOrderCPU::getInterrupts()
 729 {
 730     // Check if there are any outstanding interrupts
 731     return interrupts->getInterrupt(threadContexts[0]);
 732 }
 733
 734
 735 void
 736 InOrderCPU::processInterrupts(Fault interrupt)
 737 {
 738     // Check for interrupts here.  For now can copy the code that
 739     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 740     // is the one that handles the interrupts.
 741     // @todo: Possibly consolidate the interrupt checking code.
 742     // @todo: Allow other threads to handle interrupts.
 743
 744     assert(interrupt != NoFault);
 745     interrupts->updateIntrInfo(threadContexts[0]);
 746
 747     DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
 748
 749     // Note: Context ID ok here? Impl. of FS mode needs to revisit this
 750     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 751 }
 752
 753
 754 void
 755 InOrderCPU::updateMemPorts()
 756 {
 757     // Update all ThreadContext's memory ports (Functional/Virtual
 758     // Ports)
 759     ThreadID size = thread.size();
 760     for (ThreadID i = 0; i < size; ++i)
 761         thread[i]->connectMemPorts(thread[i]->getTC());
 762 }
 763 #endif
 764
 765 void
 766 InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 767 {
 768     //@ Squash Pipeline during TRAP
 769     scheduleCpuEvent(Trap, fault, tid, inst, delay);
 770 }
 771
 772 void
 773 InOrderCPU::trapCPU(Fault fault, ThreadID tid, DynInstPtr inst)
 774 {
 775     fault->invoke(tcBase(tid), inst->staticInst);
 776 }
 777
 778 void
 779 InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
 780 {
 781     scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
 782 }
 783
 784
 785 void
 786 InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 787                                 ThreadID tid)
 788 {
 789     DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
 790
 791     // Squash all instructions in each stage including
 792     // instruction that caused the squash (seq_num - 1)
 793     // NOTE: The stage bandwidth needs to be cleared so thats why
 794     //       the stalling instruction is squashed as well. The stalled
 795     //       instruction is previously placed in another intermediate buffer
 796     //       while it's stall is being handled.
 797     InstSeqNum squash_seq_num = seq_num - 1;
 798
 799     for (int stNum=stage_num; stNum >= 0 ; stNum--) {
 800         pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
 801     }
 802 }
 803
 804 void
 805 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
 806                              ThreadID tid, DynInstPtr inst,
 807                              unsigned delay, unsigned event_pri_offset)
 808 {
 809     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
 810                                        event_pri_offset);
 811
 812     Tick sked_tick = nextCycle(curTick() + ticks(delay));
 813     if (delay >= 0) {
 814         DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
 815                 eventNames[c_event], curTick() + delay, tid);
 816         schedule(cpu_event, sked_tick);
 817     } else {
 818         cpu_event->process();
 819         cpuEventRemoveList.push(cpu_event);
 820     }
 821
 822     // Broadcast event to the Resource Pool
 823     // Need to reset tid just in case this is a dummy instruction
 824     inst->setTid(tid);
 825     resPool->scheduleEvent(c_event, inst, 0, 0, tid);
 826 }
 827
 828 bool
 829 InOrderCPU::isThreadActive(ThreadID tid)
 830 {
 831   list<ThreadID>::iterator isActive =
 832       std::find(activeThreads.begin(), activeThreads.end(), tid);
 833
 834     return (isActive != activeThreads.end());
 835 }
 836
 837 bool
 838 InOrderCPU::isThreadReady(ThreadID tid)
 839 {
 840   list<ThreadID>::iterator isReady =
 841       std::find(readyThreads.begin(), readyThreads.end(), tid);
 842
 843     return (isReady != readyThreads.end());
 844 }
 845
 846 bool
 847 InOrderCPU::isThreadSuspended(ThreadID tid)
 848 {
 849   list<ThreadID>::iterator isSuspended =
 850       std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
 851
 852     return (isSuspended != suspendedThreads.end());
 853 }
 854
 855 void
 856 InOrderCPU::activateNextReadyThread()
 857 {
 858     if (readyThreads.size() >= 1) {
 859         ThreadID ready_tid = readyThreads.front();
 860
 861         // Activate in Pipeline
 862         activateThread(ready_tid);
 863
 864         // Activate in Resource Pool
 865         resPool->activateAll(ready_tid);
 866
 867         list<ThreadID>::iterator ready_it =
 868             std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
 869         readyThreads.erase(ready_it);
 870     } else {
 871         DPRINTF(InOrderCPU,
 872                 "Attempting to activate new thread, but No Ready Threads to"
 873                 "activate.\n");
 874         DPRINTF(InOrderCPU,
 875                 "Unable to switch to next active thread.\n");
 876     }
 877 }
 878
 879 void
 880 InOrderCPU::activateThread(ThreadID tid)
 881 {
 882     if (isThreadSuspended(tid)) {
 883         DPRINTF(InOrderCPU,
 884                 "Removing [tid:%i] from suspended threads list.\n", tid);
 885
 886         list<ThreadID>::iterator susp_it =
 887             std::find(suspendedThreads.begin(), suspendedThreads.end(),
 888                       tid);
 889         suspendedThreads.erase(susp_it);
 890     }
 891
 892     if (threadModel == SwitchOnCacheMiss &&
 893         numActiveThreads() == 1) {
 894         DPRINTF(InOrderCPU,
 895                 "Ignoring activation of [tid:%i], since [tid:%i] is "
 896                 "already running.\n", tid, activeThreadId());
 897
 898         DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
 899                 tid);
 900
 901         readyThreads.push_back(tid);
 902
 903     } else if (!isThreadActive(tid)) {
 904         DPRINTF(InOrderCPU,
 905                 "Adding [tid:%i] to active threads list.\n", tid);
 906         activeThreads.push_back(tid);
 907
 908         activateThreadInPipeline(tid);
 909
 910         thread[tid]->lastActivate = curTick();
 911
 912         tcBase(tid)->setStatus(ThreadContext::Active);
 913
 914         wakeCPU();
 915
 916         numCtxtSwitches++;
 917     }
 918 }
 919
 920 void
 921 InOrderCPU::activateThreadInPipeline(ThreadID tid)
 922 {
 923     for (int stNum=0; stNum < NumStages; stNum++) {
 924         pipelineStage[stNum]->activateThread(tid);
 925     }
 926 }
 927
 928 void
 929 InOrderCPU::deactivateContext(ThreadID tid, int delay)
 930 {
 931     DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
 932
 933     scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
 934
 935     // Be sure to signal that there's some activity so the CPU doesn't
 936     // deschedule itself.
 937     activityRec.activity();
 938
 939     _status = Running;
 940 }
 941
 942 void
 943 InOrderCPU::deactivateThread(ThreadID tid)
 944 {
 945     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
 946
 947     if (isThreadActive(tid)) {
 948         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
 949                 tid);
 950         list<ThreadID>::iterator thread_it =
 951             std::find(activeThreads.begin(), activeThreads.end(), tid);
 952
 953         removePipelineStalls(*thread_it);
 954
 955         activeThreads.erase(thread_it);
 956
 957         // Ideally, this should be triggered from the
 958         // suspendContext/Thread functions
 959         tcBase(tid)->setStatus(ThreadContext::Suspended);
 960     }
 961
 962     assert(!isThreadActive(tid));
 963 }
 964
 965 void
 966 InOrderCPU::removePipelineStalls(ThreadID tid)
 967 {
 968     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
 969             tid);
 970
 971     for (int stNum = 0; stNum < NumStages ; stNum++) {
 972         pipelineStage[stNum]->removeStalls(tid);
 973     }
 974
 975 }
 976
 977 void
 978 InOrderCPU::updateThreadPriority()
 979 {
 980     if (activeThreads.size() > 1)
 981     {
 982         //DEFAULT TO ROUND ROBIN SCHEME
 983         //e.g. Move highest priority to end of thread list
 984         list<ThreadID>::iterator list_begin = activeThreads.begin();
 985         list<ThreadID>::iterator list_end   = activeThreads.end();
 986
 987         unsigned high_thread = *list_begin;
 988
 989         activeThreads.erase(list_begin);
 990
 991         activeThreads.push_back(high_thread);
 992     }
 993 }
 994
 995 inline void
 996 InOrderCPU::tickThreadStats()
 997 {
 998     /** Keep track of cycles that each thread is active */
 999     list<ThreadID>::iterator thread_it = activeThreads.begin();
1000     while (thread_it != activeThreads.end()) {
1001         threadCycles[*thread_it]++;
1002         thread_it++;
1003     }
1004
1005     // Keep track of cycles where SMT is active
1006     if (activeThreads.size() > 1) {
1007         smtCycles++;
1008     }
1009 }
1010
1011 void
1012 InOrderCPU::activateContext(ThreadID tid, int delay)
1013 {
1014     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
1015
1016
1017     scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
1018
1019     // Be sure to signal that there's some activity so the CPU doesn't
1020     // deschedule itself.
1021     activityRec.activity();
1022
1023     _status = Running;
1024 }
1025
1026 void
1027 InOrderCPU::activateNextReadyContext(int delay)
1028 {
1029     DPRINTF(InOrderCPU,"Activating next ready thread\n");
1030
1031     // NOTE: Add 5 to the event priority so that we always activate
1032     // threads after we've finished deactivating, squashing,etc.
1033     // other threads
1034     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
1035                      delay, 5);
1036
1037     // Be sure to signal that there's some activity so the CPU doesn't
1038     // deschedule itself.
1039     activityRec.activity();
1040
1041     _status = Running;
1042 }
1043
1044 void
1045 InOrderCPU::haltContext(ThreadID tid, int delay)
1046 {
1047     DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
1048
1049     scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
1050
1051     activityRec.activity();
1052 }
1053
1054 void
1055 InOrderCPU::haltThread(ThreadID tid)
1056 {
1057     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
1058     deactivateThread(tid);
1059     squashThreadInPipeline(tid);
1060     haltedThreads.push_back(tid);
1061
1062     tcBase(tid)->setStatus(ThreadContext::Halted);
1063
1064     if (threadModel == SwitchOnCacheMiss) {
1065         activateNextReadyContext();
1066     }
1067 }
1068
1069 void
1070 InOrderCPU::suspendContext(ThreadID tid, int delay)
1071 {
1072     scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
1073 }
1074
1075 void
1076 InOrderCPU::suspendThread(ThreadID tid)
1077 {
1078     DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
1079             tid);
1080     deactivateThread(tid);
1081     suspendedThreads.push_back(tid);
1082     thread[tid]->lastSuspend = curTick();
1083
1084     tcBase(tid)->setStatus(ThreadContext::Suspended);
1085 }
1086
1087 void
1088 InOrderCPU::squashThreadInPipeline(ThreadID tid)
1089 {
1090     //Squash all instructions in each stage
1091     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
1092         pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
1093     }
1094 }
1095
1096 PipelineStage*
1097 InOrderCPU::getPipeStage(int stage_num)
1098 {
1099     return pipelineStage[stage_num];
1100 }
1101
1102 uint64_t
1103 InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
1104 {
1105     return intRegs[tid][reg_idx];
1106 }
1107
1108 FloatReg
1109 InOrderCPU::readFloatReg(int reg_idx, ThreadID tid)
1110 {
1111     return floatRegs.f[tid][reg_idx];
1112 }
1113
1114 FloatRegBits
1115 InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
1116 {;
1117     return floatRegs.i[tid][reg_idx];
1118 }
1119
1120 void
1121 InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
1122 {
1123     intRegs[tid][reg_idx] = val;
1124 }
1125
1126
1127 void
1128 InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid)
1129 {
1130     floatRegs.f[tid][reg_idx] = val;
1131 }
1132
1133
1134 void
1135 InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid)
1136 {
1137     floatRegs.i[tid][reg_idx] = val;
1138 }
1139
1140 uint64_t
1141 InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
1142 {
1143     // If Default value is set, then retrieve target thread
1144     if (tid == InvalidThreadID) {
1145         tid = TheISA::getTargetThread(tcBase(tid));
1146     }
1147
1148     if (reg_idx < FP_Base_DepTag) {
1149         // Integer Register File
1150         return readIntReg(reg_idx, tid);
1151     } else if (reg_idx < Ctrl_Base_DepTag) {
1152         // Float Register File
1153         reg_idx -= FP_Base_DepTag;
1154         return readFloatRegBits(reg_idx, tid);
1155     } else {
1156         reg_idx -= Ctrl_Base_DepTag;
1157         return readMiscReg(reg_idx, tid);  // Misc. Register File
1158     }
1159 }
1160 void
1161 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
1162                               ThreadID tid)
1163 {
1164     // If Default value is set, then retrieve target thread
1165     if (tid == InvalidThreadID) {
1166         tid = TheISA::getTargetThread(tcBase(tid));
1167     }
1168
1169     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
1170         setIntReg(reg_idx, val, tid);
1171     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
1172         reg_idx -= FP_Base_DepTag;
1173         setFloatRegBits(reg_idx, val, tid);
1174     } else {
1175         reg_idx -= Ctrl_Base_DepTag;
1176         setMiscReg(reg_idx, val, tid); // Misc. Register File
1177     }
1178 }
1179
1180 MiscReg
1181 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1182 {
1183     return isa[tid].readMiscRegNoEffect(misc_reg);
1184 }
1185
1186 MiscReg
1187 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
1188 {
1189     return isa[tid].readMiscReg(misc_reg, tcBase(tid));
1190 }
1191
1192 void
1193 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
1194 {
1195     isa[tid].setMiscRegNoEffect(misc_reg, val);
1196 }
1197
1198 void
1199 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
1200 {
1201     isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1202 }
1203
1204
1205 InOrderCPU::ListIt
1206 InOrderCPU::addInst(DynInstPtr &inst)
1207 {
1208     ThreadID tid = inst->readTid();
1209
1210     instList[tid].push_back(inst);
1211
1212     return --(instList[tid].end());
1213 }
1214
1215 void
1216 InOrderCPU::updateContextSwitchStats()
1217 {
1218     // Set Average Stat Here, then reset to 0
1219     instsPerCtxtSwitch = instsPerSwitch;
1220     instsPerSwitch = 0;
1221 }
1222
1223
1224 void
1225 InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
1226 {
1227     // Set the CPU's PCs - This contributes to the precise state of the CPU
1228     // which can be used when restoring a thread to the CPU after after any
1229     // type of context switching activity (fork, exception, etc.)
1230     pcState(inst->pcState(), tid);
1231
1232     if (inst->isControl()) {
1233         thread[tid]->lastGradIsBranch = true;
1234         thread[tid]->lastBranchPC = inst->pcState();
1235         TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
1236     } else {
1237         thread[tid]->lastGradIsBranch = false;
1238     }
1239
1240
1241     // Finalize Trace Data For Instruction
1242     if (inst->traceData) {
1243         //inst->traceData->setCycle(curTick());
1244         inst->traceData->setFetchSeq(inst->seqNum);
1245         //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1246         inst->traceData->dump();
1247         delete inst->traceData;
1248         inst->traceData = NULL;
1249     }
1250
1251     // Increment active thread's instruction count
1252     instsPerSwitch++;
1253
1254     // Increment thread-state's instruction count
1255     thread[tid]->numInst++;
1256
1257     // Increment thread-state's instruction stats
1258     thread[tid]->numInsts++;
1259
1260     // Count committed insts per thread stats
1261     committedInsts[tid]++;
1262
1263     // Count total insts committed stat
1264     totalCommittedInsts++;
1265
1266     // Count SMT-committed insts per thread stat
1267     if (numActiveThreads() > 1) {
1268         smtCommittedInsts[tid]++;
1269     }
1270
1271     // Instruction-Mix Stats
1272     if (inst->isLoad()) {
1273         comLoads++;
1274     } else if (inst->isStore()) {
1275         comStores++;
1276     } else if (inst->isControl()) {
1277         comBranches++;
1278     } else if (inst->isNop()) {
1279         comNops++;
1280     } else if (inst->isNonSpeculative()) {
1281         comNonSpec++;
1282     } else if (inst->isInteger()) {
1283         comInts++;
1284     } else if (inst->isFloating()) {
1285         comFloats++;
1286     }
1287
1288     // Check for instruction-count-based events.
1289     comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1290
1291     // Broadcast to other resources an instruction
1292     // has been completed
1293     resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
1294                            0, 0, tid);
1295
1296     // Finally, remove instruction from CPU
1297     removeInst(inst);
1298 }
1299
1300 // currently unused function, but substitute repetitive code w/this function
1301 // call
1302 void
1303 InOrderCPU::addToRemoveList(DynInstPtr &inst)
1304 {
1305     removeInstsThisCycle = true;
1306     if (!inst->isRemoveList()) {
1307         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1308                 "[sn:%lli] to remove list\n",
1309                 inst->threadNumber, inst->pcState(), inst->seqNum);
1310         inst->setRemoveList();
1311         removeList.push(inst->getInstListIt());
1312     }  else {
1313         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1314                 "[sn:%lli], already remove list\n",
1315                 inst->threadNumber, inst->pcState(), inst->seqNum);
1316     }
1317
1318 }
1319
1320 void
1321 InOrderCPU::removeInst(DynInstPtr &inst)
1322 {
1323     DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
1324             "[sn:%lli]\n",
1325             inst->threadNumber, inst->pcState(), inst->seqNum);
1326
1327     removeInstsThisCycle = true;
1328
1329     // Remove the instruction.
1330     if (!inst->isRemoveList()) {
1331         DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1332                 "[sn:%lli] to remove list\n",
1333                 inst->threadNumber, inst->pcState(), inst->seqNum);
1334         inst->setRemoveList();
1335         removeList.push(inst->getInstListIt());
1336     } else {
1337         DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
1338                 "[sn:%lli], already on remove list\n",
1339                 inst->threadNumber, inst->pcState(), inst->seqNum);
1340     }
1341
1342 }
1343
1344 void
1345 InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1346 {
1347     //assert(!instList[tid].empty());
1348
1349     removeInstsThisCycle = true;
1350
1351     ListIt inst_iter = instList[tid].end();
1352
1353     inst_iter--;
1354
1355     DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
1356             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1357             tid, seq_num, (*inst_iter)->seqNum);
1358
1359     while ((*inst_iter)->seqNum > seq_num) {
1360
1361         bool break_loop = (inst_iter == instList[tid].begin());
1362
1363         squashInstIt(inst_iter, tid);
1364
1365         inst_iter--;
1366
1367         if (break_loop)
1368             break;
1369     }
1370 }
1371
1372
1373 inline void
1374 InOrderCPU::squashInstIt(const ListIt &instIt, ThreadID tid)
1375 {
1376     if ((*instIt)->threadNumber == tid) {
1377         DPRINTF(InOrderCPU, "Squashing instruction, "
1378                 "[tid:%i] [sn:%lli] PC %s\n",
1379                 (*instIt)->threadNumber,
1380                 (*instIt)->seqNum,
1381                 (*instIt)->pcState());
1382
1383         (*instIt)->setSquashed();
1384
1385         if (!(*instIt)->isRemoveList()) {
1386             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
1387                     "[sn:%lli] to remove list\n",
1388                     (*instIt)->threadNumber, (*instIt)->pcState(),
1389                     (*instIt)->seqNum);
1390             (*instIt)->setRemoveList();
1391             removeList.push(instIt);
1392         } else {
1393             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
1394                     " PC %s [sn:%lli], already on remove list\n",
1395                     (*instIt)->threadNumber, (*instIt)->pcState(),
1396                     (*instIt)->seqNum);
1397         }
1398
1399     }
1400
1401 }
1402
1403
1404 void
1405 InOrderCPU::cleanUpRemovedInsts()
1406 {
1407     while (!removeList.empty()) {
1408         DPRINTF(InOrderCPU, "Removing instruction, "
1409                 "[tid:%i] [sn:%lli] PC %s\n",
1410                 (*removeList.front())->threadNumber,
1411                 (*removeList.front())->seqNum,
1412                (*removeList.front())->pcState());
1413
1414         DynInstPtr inst = *removeList.front();
1415         ThreadID tid = inst->threadNumber;
1416
1417         // Remove From Register Dependency Map, If Necessary
1418         archRegDepMap[(*removeList.front())->threadNumber].
1419             remove((*removeList.front()));
1420
1421
1422         // Clear if Non-Speculative
1423         if (inst->staticInst &&
1424             inst->seqNum == nonSpecSeqNum[tid] &&
1425             nonSpecInstActive[tid] == true) {
1426             nonSpecInstActive[tid] = false;
1427         }
1428
1429         instList[tid].erase(removeList.front());
1430
1431         removeList.pop();
1432     }
1433
1434     removeInstsThisCycle = false;
1435 }
1436
1437 void
1438 InOrderCPU::cleanUpRemovedEvents()
1439 {
1440     while (!cpuEventRemoveList.empty()) {
1441         Event *cpu_event = cpuEventRemoveList.front();
1442         cpuEventRemoveList.pop();
1443         delete cpu_event;
1444     }
1445 }
1446
1447
1448 void
1449 InOrderCPU::dumpInsts()
1450 {
1451     int num = 0;
1452
1453     ListIt inst_list_it = instList[0].begin();
1454
1455     cprintf("Dumping Instruction List\n");
1456
1457     while (inst_list_it != instList[0].end()) {
1458         cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1459                 "Squashed:%i\n\n",
1460                 num, (*inst_list_it)->pcState(),
1461                 (*inst_list_it)->threadNumber,
1462                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1463                 (*inst_list_it)->isSquashed());
1464         inst_list_it++;
1465         ++num;
1466     }
1467 }
1468
1469 void
1470 InOrderCPU::wakeCPU()
1471 {
1472     if (/*activityRec.active() || */tickEvent.scheduled()) {
1473         DPRINTF(Activity, "CPU already running.\n");
1474         return;
1475     }
1476
1477     DPRINTF(Activity, "Waking up CPU\n");
1478
1479     Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
1480
1481     idleCycles += extra_cycles;
1482     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
1483         pipelineStage[stage_num]->idleCycles += extra_cycles;
1484     }
1485
1486     numCycles += extra_cycles;
1487
1488     schedule(&tickEvent, nextCycle(curTick()));
1489 }
1490
1491 #if FULL_SYSTEM
1492
1493 void
1494 InOrderCPU::wakeup()
1495 {
1496     if (thread[0]->status() != ThreadContext::Suspended)
1497         return;
1498
1499     wakeCPU();
1500
1501     DPRINTF(Quiesce, "Suspended Processor woken\n");
1502     threadContexts[0]->activate();
1503 }
1504 #endif
1505
1506 #if !FULL_SYSTEM
1507 void
1508 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
1509 {
1510     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
1511
1512     DPRINTF(Activity,"Activity: syscall() called.\n");
1513
1514     // Temporarily increase this by one to account for the syscall
1515     // instruction.
1516     ++(this->thread[tid]->funcExeInst);
1517
1518     // Execute the actual syscall.
1519     this->thread[tid]->syscall(callnum);
1520
1521     // Decrease funcExeInst by one as the normal commit will handle
1522     // incrementing it.
1523     --(this->thread[tid]->funcExeInst);
1524
1525     // Clear Non-Speculative Block Variable
1526     nonSpecInstActive[tid] = false;
1527 }
1528 #endif
1529
1530 TheISA::TLB*
1531 InOrderCPU::getITBPtr()
1532 {
1533     CacheUnit *itb_res =
1534         dynamic_cast<CacheUnit*>(resPool->getResource(fetchPortIdx));
1535     return itb_res->tlb();
1536 }
1537
1538
1539 TheISA::TLB*
1540 InOrderCPU::getDTBPtr()
1541 {
1542     CacheUnit *dtb_res =
1543         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1544     return dtb_res->tlb();
1545 }
1546
1547 Fault
1548 InOrderCPU::read(DynInstPtr inst, Addr addr,
1549                  uint8_t *data, unsigned size, unsigned flags)
1550 {
1551     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1552     //       you want to run w/out caches?
1553     CacheUnit *cache_res =
1554         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1555
1556     return cache_res->read(inst, addr, data, size, flags);
1557 }
1558
1559 Fault
1560 InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
1561                   Addr addr, unsigned flags, uint64_t *write_res)
1562 {
1563     //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1564     //       you want to run w/out caches?
1565     CacheUnit *cache_res =
1566         dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
1567     return cache_res->write(inst, data, size, addr, flags, write_res);
1568 }