2 * Copyright (c) 2012-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
15 * Copyright (c) 2007 MIPS Technologies, Inc.
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Korey Sewell
45 #ifndef __CPU_INORDER_CPU_HH__
46 #define __CPU_INORDER_CPU_HH__
54 #include "arch/isa_traits.hh"
55 #include "arch/registers.hh"
56 #include "arch/types.hh"
57 #include "base/statistics.hh"
58 #include "base/types.hh"
59 #include "config/the_isa.hh"
60 #include "cpu/inorder/inorder_dyn_inst.hh"
61 #include "cpu/inorder/pipeline_stage.hh"
62 #include "cpu/inorder/pipeline_traits.hh"
63 #include "cpu/inorder/reg_dep_map.hh"
64 #include "cpu/inorder/thread_state.hh"
65 #include "cpu/o3/dep_graph.hh"
66 #include "cpu/o3/rename_map.hh"
67 #include "cpu/activity.hh"
68 #include "cpu/base.hh"
69 #include "cpu/reg_class.hh"
70 #include "cpu/simple_thread.hh"
71 #include "cpu/timebuf.hh"
72 #include "mem/packet.hh"
73 #include "mem/port.hh"
74 #include "mem/request.hh"
75 #include "sim/eventq.hh"
76 #include "sim/process.hh"
85 class InOrderCPU : public BaseCPU
89 typedef ThePipeline::Params Params;
90 typedef InOrderThreadState Thread;
93 typedef TheISA::IntReg IntReg;
94 typedef TheISA::FloatReg FloatReg;
95 typedef TheISA::FloatRegBits FloatRegBits;
96 typedef TheISA::CCReg CCReg;
97 typedef TheISA::MiscReg MiscReg;
98 typedef TheISA::RegIndex RegIndex;
100 //DynInstPtr TypeDefs
101 typedef ThePipeline::DynInstPtr DynInstPtr;
102 typedef std::list<DynInstPtr>::iterator ListIt;
104 //TimeBuffer TypeDefs
105 typedef TimeBuffer<InterStageStruct> StageQueue;
107 friend class Resource;
110 /** Constructs a CPU with the given parameters. */
111 InOrderCPU(Params *params);
115 void verifyMemoryMode() const;
117 /** Return a reference to the data port. */
118 virtual MasterPort &getDataPort() { return dataPort; }
120 /** Return a reference to the instruction port. */
121 virtual MasterPort &getInstPort() { return instPort; }
127 ThreadID asid[ThePipeline::MaxThreads];
129 /** Type of core that this is */
130 std::string coreType;
132 // Only need for SE MODE
139 ThreadModel threadModel;
141 int readCpuId() { return cpu_id; }
143 void setCpuId(int val) { cpu_id = val; }
156 /** Overall CPU status. */
161 * CachePort class for the in-order CPU, interacting with a
162 * specific CacheUnit in the pipeline.
164 class CachePort : public MasterPort
168 /** Pointer to cache unit */
169 CacheUnit *cacheUnit;
172 /** Default constructor. */
173 CachePort(CacheUnit *_cacheUnit, const std::string& name);
177 /** Timing version of receive */
178 bool recvTimingResp(PacketPtr pkt);
180 /** Handles doing a retry of a failed timing request. */
183 /** Ignoring snoops for now. */
184 void recvTimingSnoopReq(PacketPtr pkt) { }
187 /** Define TickEvent for the CPU */
188 class TickEvent : public Event
191 /** Pointer to the CPU. */
195 /** Constructs a tick event. */
196 TickEvent(InOrderCPU *c);
198 /** Processes a tick event, calling tick() on the CPU. */
201 /** Returns the description of the tick event. */
202 const char *description() const;
205 /** The tick event used for scheduling CPU ticks. */
208 /** Schedule tick event, regardless of its current state. */
209 void scheduleTickEvent(Cycles delay)
211 assert(!tickEvent.scheduled() || tickEvent.squashed());
212 reschedule(&tickEvent, clockEdge(delay), true);
215 /** Unschedule tick event, regardless of its current state. */
216 void unscheduleTickEvent()
218 if (tickEvent.scheduled())
223 // List of Events That can be scheduled from
225 // NOTE(1): The Resource Pool also uses this event list
226 // to schedule events broadcast to all resources interfaces
227 // NOTE(2): CPU Events usually need to schedule a corresponding resource
231 ActivateNextReadyThread,
242 static std::string eventNames[NumCPUEvents];
245 InOrderCPU_Pri = Event::CPU_Tick_Pri,
246 Syscall_Pri = Event::CPU_Tick_Pri + 9,
247 ActivateNextReadyThread_Pri = Event::CPU_Tick_Pri + 10
250 /** Define CPU Event */
251 class CPUEvent : public Event
257 CPUEventType cpuEventType;
265 /** Constructs a CPU event. */
266 CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
267 ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
269 /** Set Type of Event To Be Scheduled */
270 void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
274 cpuEventType = e_type;
280 /** Processes a CPU event. */
283 /** Returns the description of the CPU event. */
284 const char *description() const;
286 /** Schedule Event */
287 void scheduleEvent(Cycles delay);
289 /** Unschedule This Event */
290 void unscheduleEvent();
293 /** Schedule a CPU Event */
294 void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
295 DynInstPtr inst, Cycles delay = Cycles(0),
296 CPUEventPri event_pri = InOrderCPU_Pri);
300 /** Width (processing bandwidth) of each stage */
303 /** Interface between the CPU and CPU resources. */
304 ResourcePool *resPool;
306 /** Instruction used to signify that there is no *real* instruction in
308 DynInstPtr dummyInst[ThePipeline::MaxThreads];
309 DynInstPtr dummyBufferInst;
310 DynInstPtr dummyReqInst;
311 DynInstPtr dummyTrapInst[ThePipeline::MaxThreads];
313 /** Used by resources to signify a denied access to a resource. */
314 ResourceRequest *dummyReq[ThePipeline::MaxThreads];
316 /** The Pipeline Stages for the CPU */
317 PipelineStage *pipelineStage[ThePipeline::NumStages];
319 /** Program Counters */
320 TheISA::PCState pc[ThePipeline::MaxThreads];
322 /** Last Committed PC */
323 TheISA::PCState lastCommittedPC[ThePipeline::MaxThreads];
325 /** The Register File for the CPU */
327 FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
328 FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
330 TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
331 #ifdef ISA_HAS_CC_REGS
332 TheISA::CCReg ccRegs[ThePipeline::MaxThreads][TheISA::NumCCRegs];
336 std::vector<TheISA::ISA *> isa;
338 /** Dependency Tracker for Integer & Floating Point Regs */
339 RegDepMap archRegDepMap[ThePipeline::MaxThreads];
341 /** Global communication structure */
342 TimeBuffer<TimeStruct> timeBuffer;
344 /** Communication structure that sits in between pipeline stages */
345 StageQueue *stageQueue[ThePipeline::NumStages-1];
347 TheISA::TLB *getITBPtr();
348 TheISA::TLB *getDTBPtr();
350 TheISA::Decoder *getDecoderPtr(unsigned tid);
352 /** Accessor Type for the SkedCache */
353 typedef uint32_t SkedID;
355 /** Cache of Instruction Schedule using the instruction's name as a key */
356 static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
358 typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
360 /** Initialized to last iterator in map, signifying a invalid entry
363 SkedCacheIt endOfSkedIt;
365 ThePipeline::RSkedPtr frontEndSked;
366 ThePipeline::RSkedPtr faultSked;
368 /** Add a new instruction schedule to the schedule cache */
369 void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
371 SkedID sked_id = genSkedID(inst);
372 assert(skedCache.find(sked_id) == skedCache.end());
373 skedCache[sked_id] = inst_sked;
377 /** Find a instruction schedule */
378 ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
380 SkedID sked_id = genSkedID(inst);
381 SkedCacheIt lookup_it = skedCache.find(sked_id);
383 if (lookup_it != endOfSkedIt) {
384 return (*lookup_it).second;
390 static const uint8_t INST_OPCLASS = 26;
391 static const uint8_t INST_LOAD = 25;
392 static const uint8_t INST_STORE = 24;
393 static const uint8_t INST_CONTROL = 23;
394 static const uint8_t INST_NONSPEC = 22;
395 static const uint8_t INST_DEST_REGS = 18;
396 static const uint8_t INST_SRC_REGS = 14;
397 static const uint8_t INST_SPLIT_DATA = 13;
399 inline SkedID genSkedID(DynInstPtr inst)
402 id = (inst->opClass() << INST_OPCLASS) |
403 (inst->isLoad() << INST_LOAD) |
404 (inst->isStore() << INST_STORE) |
405 (inst->isControl() << INST_CONTROL) |
406 (inst->isNonSpeculative() << INST_NONSPEC) |
407 (inst->numDestRegs() << INST_DEST_REGS) |
408 (inst->numSrcRegs() << INST_SRC_REGS) |
409 (inst->splitInst << INST_SPLIT_DATA);
413 ThePipeline::RSkedPtr createFrontEndSked();
414 ThePipeline::RSkedPtr createFaultSked();
415 ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
417 class StageScheduler {
419 ThePipeline::RSkedPtr rsked;
421 int nextTaskPriority;
424 StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
425 : rsked(_rsked), stageNum(stage_num),
429 void needs(int unit, int request) {
430 rsked->push(new ScheduleEntry(
431 stageNum, nextTaskPriority++, unit, request
435 void needs(int unit, int request, int param) {
436 rsked->push(new ScheduleEntry(
437 stageNum, nextTaskPriority++, unit, request, param
444 /** Data port. Note that it has to appear after the resPool. */
447 /** Instruction port. Note that it has to appear after the resPool. */
452 /** Registers statistics. */
455 /** Ticks CPU, calling tick() on each stage, and checking the overall
456 * activity to see if the CPU should deschedule itself.
460 /** Initialize the CPU */
463 /** HW return from error interrupt. */
464 Fault hwrei(ThreadID tid);
466 bool simPalCheck(int palFunc, ThreadID tid);
468 void checkForInterrupts();
470 /** Returns the Fault for any valid interrupt. */
471 Fault getInterrupts();
473 /** Processes any an interrupt fault. */
474 void processInterrupts(Fault interrupt);
476 /** Halts the CPU. */
477 void halt() { panic("Halt not implemented!\n"); }
479 /** Check if this address is a valid instruction address. */
480 bool validInstAddr(Addr addr) { return true; }
482 /** Check if this address is a valid data address. */
483 bool validDataAddr(Addr addr) { return true; }
485 /** Schedule a syscall on the CPU */
486 void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
487 Cycles delay = Cycles(0));
489 /** Executes a syscall.*/
490 void syscall(int64_t callnum, ThreadID tid);
492 /** Schedule a trap on the CPU */
493 void trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
494 Cycles delay = Cycles(0));
496 /** Perform trap to Handle Given Fault */
497 void trap(Fault fault, ThreadID tid, DynInstPtr inst);
499 /** Schedule thread activation on the CPU */
500 void activateContext(ThreadID tid, Cycles delay = Cycles(0));
502 /** Add Thread to Active Threads List. */
503 void activateThread(ThreadID tid);
505 /** Activate Thread In Each Pipeline Stage */
506 void activateThreadInPipeline(ThreadID tid);
508 /** Schedule Thread Activation from Ready List */
509 void activateNextReadyContext(Cycles delay = Cycles(0));
511 /** Add Thread From Ready List to Active Threads List. */
512 void activateNextReadyThread();
514 /** Schedule a thread deactivation on the CPU */
515 void deactivateContext(ThreadID tid, Cycles delay = Cycles(0));
517 /** Remove from Active Thread List */
518 void deactivateThread(ThreadID tid);
520 /** Schedule a thread suspension on the CPU */
521 void suspendContext(ThreadID tid);
523 /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
524 void suspendThread(ThreadID tid);
526 /** Schedule a thread halt on the CPU */
527 void haltContext(ThreadID tid);
529 /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
532 void haltThread(ThreadID tid);
534 /** squashFromMemStall() - sets up a squash event
535 * squashDueToMemStall() - squashes pipeline
536 * @note: maybe squashContext/squashThread would be better?
538 void squashFromMemStall(DynInstPtr inst, ThreadID tid,
539 Cycles delay = Cycles(0));
540 void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
542 void removePipelineStalls(ThreadID tid);
543 void squashThreadInPipeline(ThreadID tid);
544 void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
546 PipelineStage* getPipeStage(int stage_num);
551 hack_once("return a bogus context id");
555 /** Update The Order In Which We Process Threads. */
556 void updateThreadPriority();
558 /** Switches a Pipeline Stage to Active. (Unused currently) */
559 void switchToActive(int stage_idx)
560 { /*pipelineStage[stage_idx]->switchToActive();*/ }
562 /** Get the current instruction sequence number, and increment it. */
563 InstSeqNum getAndIncrementInstSeq(ThreadID tid)
564 { return globalSeqNum[tid]++; }
566 /** Get the current instruction sequence number, and increment it. */
567 InstSeqNum nextInstSeqNum(ThreadID tid)
568 { return globalSeqNum[tid]; }
570 /** Increment Instruction Sequence Number */
571 void incrInstSeqNum(ThreadID tid)
572 { globalSeqNum[tid]++; }
574 /** Set Instruction Sequence Number */
575 void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
577 globalSeqNum[tid] = seq_num;
580 /** Get & Update Next Event Number */
581 InstSeqNum getNextEventNum()
584 return cpuEventNum++;
590 /** Register file accessors */
591 uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
593 FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
595 FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
597 CCReg readCCReg(RegIndex reg_idx, ThreadID tid);
599 void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
601 void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
603 void setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid);
605 void setCCReg(RegIndex reg_idx, CCReg val, ThreadID tid);
607 RegIndex flattenRegIdx(RegIndex reg_idx, RegClass ®_type, ThreadID tid);
609 /** Reads a miscellaneous register. */
610 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
612 /** Reads a misc. register, including any side effects the read
613 * might have as defined by the architecture.
615 MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
617 /** Sets a miscellaneous register. */
618 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
621 /** Sets a misc. register, including any side effects the write
622 * might have as defined by the architecture.
624 void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
626 /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
629 uint64_t readRegOtherThread(unsigned misc_reg,
630 ThreadID tid = InvalidThreadID);
632 /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
635 void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
638 /** Reads the commit PC of a specific thread. */
640 pcState(ThreadID tid)
645 /** Sets the commit PC of a specific thread. */
647 pcState(const TheISA::PCState &newPC, ThreadID tid)
652 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
653 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
654 MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
656 /** Function to add instruction onto the head of the list of the
657 * instructions. Used when new instructions are fetched.
659 ListIt addInst(DynInstPtr inst);
661 /** Find instruction on instruction list */
662 ListIt findInst(InstSeqNum seq_num, ThreadID tid);
664 /** Function to tell the CPU that an instruction has completed. */
665 void instDone(DynInstPtr inst, ThreadID tid);
667 /** Add Instructions to the CPU Remove List*/
668 void addToRemoveList(DynInstPtr inst);
670 /** Remove an instruction from CPU */
671 void removeInst(DynInstPtr inst);
673 /** Remove all instructions younger than the given sequence number. */
674 void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
676 /** Removes the instruction pointed to by the iterator. */
677 inline void squashInstIt(const ListIt inst_it, ThreadID tid);
679 /** Cleans up all instructions on the instruction remove list. */
680 void cleanUpRemovedInsts();
682 /** Cleans up all events on the CPU event remove list. */
683 void cleanUpRemovedEvents();
685 /** Debug function to print all instructions on the list. */
688 /** Forwards an instruction read to the appropriate data
689 * resource (indexes into Resource Pool thru "dataPortIdx")
691 Fault read(DynInstPtr inst, Addr addr,
692 uint8_t *data, unsigned size, unsigned flags);
694 /** Forwards an instruction write. to the appropriate data
695 * resource (indexes into Resource Pool thru "dataPortIdx")
697 Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
698 Addr addr, unsigned flags, uint64_t *write_res = NULL);
701 /** Per-Thread List of all the instructions in flight. */
702 std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
704 /** List of all the instructions that will be removed at the end of this
707 std::queue<ListIt> removeList;
709 bool trapPending[ThePipeline::MaxThreads];
711 /** List of all the cpu event requests that will be removed at the end of
714 std::queue<Event*> cpuEventRemoveList;
716 /** Records if instructions need to be removed this cycle due to
717 * being retired or squashed.
719 bool removeInstsThisCycle;
721 /** True if there is non-speculative Inst Active In Pipeline. Lets any
722 * execution unit know, NOT to execute while the instruction is active.
724 bool nonSpecInstActive[ThePipeline::MaxThreads];
726 /** Instruction Seq. Num of current non-speculative instruction. */
727 InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
729 /** Instruction Seq. Num of last instruction squashed in pipeline */
730 InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
732 /** Last Cycle that the CPU squashed instruction end. */
733 Tick lastSquashCycle[ThePipeline::MaxThreads];
735 std::list<ThreadID> fetchPriorityList;
738 /** Active Threads List */
739 std::list<ThreadID> activeThreads;
741 /** Ready Threads List */
742 std::list<ThreadID> readyThreads;
744 /** Suspended Threads List */
745 std::list<ThreadID> suspendedThreads;
747 /** Halted Threads List */
748 std::list<ThreadID> haltedThreads;
750 /** Thread Status Functions */
751 bool isThreadActive(ThreadID tid);
752 bool isThreadReady(ThreadID tid);
753 bool isThreadSuspended(ThreadID tid);
756 /** The activity recorder; used to tell if the CPU has any
757 * activity remaining or if it can go to idle and deschedule
760 ActivityRecorder activityRec;
763 /** Number of Active Threads in the CPU */
764 ThreadID numActiveThreads() { return activeThreads.size(); }
766 /** Thread id of active thread
767 * Only used for SwitchOnCacheMiss model.
768 * Assumes only 1 thread active
770 ThreadID activeThreadId()
772 if (numActiveThreads() > 0)
773 return activeThreads.front();
775 return InvalidThreadID;
779 /** Records that there was time buffer activity this cycle. */
780 void activityThisCycle() { activityRec.activity(); }
782 /** Changes a stage's status to active within the activity recorder. */
783 void activateStage(const int idx)
784 { activityRec.activateStage(idx); }
786 /** Changes a stage's status to inactive within the activity recorder. */
787 void deactivateStage(const int idx)
788 { activityRec.deactivateStage(idx); }
790 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
793 virtual void wakeup();
795 /* LL/SC debug functionality
796 unsigned stCondFails;
798 unsigned readStCondFailures()
799 { return stCondFails; }
801 unsigned setStCondFailures(unsigned st_fails)
802 { return stCondFails = st_fails; }
805 /** Returns a pointer to a thread context. */
806 ThreadContext *tcBase(ThreadID tid = 0)
808 return thread[tid]->getTC();
811 /** Count the Total Instructions Committed in the CPU. */
812 virtual Counter totalInsts() const
816 for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
817 total += thread[tid]->numInst;
822 /** Count the Total Ops Committed in the CPU. */
823 virtual Counter totalOps() const
827 for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
828 total += thread[tid]->numOp;
833 /** Pointer to the system. */
836 /** The global sequence number counter. */
837 InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
840 /** The global event number counter. */
841 InstSeqNum cpuEventNum;
843 /** Number of resource requests active in CPU **/
844 unsigned resReqCount;
849 /** Temporary fix for the lock flag, works in the UP case. */
852 /** Counter of how many stages have completed draining */
855 /** Pointers to all of the threads in the CPU. */
856 std::vector<Thread *> thread;
858 /** Per-Stage Instruction Tracing */
861 /** The cycle that the CPU was last running, used for statistics. */
862 Tick lastRunningCycle;
864 void updateContextSwitchStats();
865 unsigned instsPerSwitch;
866 Stats::Average instsPerCtxtSwitch;
867 Stats::Scalar numCtxtSwitches;
869 /** Update Thread , used for statistic purposes*/
870 inline void tickThreadStats();
872 /** Per-Thread Tick */
873 Stats::Vector threadCycles;
876 Stats::Scalar smtCycles;
878 /** Stat for total number of times the CPU is descheduled. */
879 Stats::Scalar timesIdled;
881 /** Stat for total number of cycles the CPU spends descheduled or no
884 Stats::Scalar idleCycles;
886 /** Stat for total number of cycles the CPU is active. */
887 Stats::Scalar runCycles;
889 /** Percentage of cycles a stage was active */
890 Stats::Formula activity;
892 /** Instruction Mix Stats */
893 Stats::Scalar comLoads;
894 Stats::Scalar comStores;
895 Stats::Scalar comBranches;
896 Stats::Scalar comNops;
897 Stats::Scalar comNonSpec;
898 Stats::Scalar comInts;
899 Stats::Scalar comFloats;
901 /** Stat for the number of committed instructions per thread. */
902 Stats::Vector committedInsts;
904 /** Stat for the number of committed ops per thread. */
905 Stats::Vector committedOps;
907 /** Stat for the number of committed instructions per thread. */
908 Stats::Vector smtCommittedInsts;
910 /** Stat for the total number of committed instructions. */
911 Stats::Scalar totalCommittedInsts;
913 /** Stat for the CPI per thread. */
916 /** Stat for the SMT-CPI per thread. */
917 Stats::Formula smtCpi;
919 /** Stat for the total CPI. */
920 Stats::Formula totalCpi;
922 /** Stat for the IPC per thread. */
925 /** Stat for the total IPC. */
926 Stats::Formula smtIpc;
928 /** Stat for the total IPC. */
929 Stats::Formula totalIpc;
932 #endif // __CPU_O3_CPU_HH__