src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/types.hh"
  43 #include "arch/registers.hh"
  44 #include "base/statistics.hh"
  45 #include "cpu/timebuf.hh"
  46 #include "base/types.hh"
  47 #include "config/full_system.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/activity.hh"
  50 #include "cpu/base.hh"
  51 #include "cpu/simple_thread.hh"
  52 #include "cpu/inorder/inorder_dyn_inst.hh"
  53 #include "cpu/inorder/pipeline_traits.hh"
  54 #include "cpu/inorder/pipeline_stage.hh"
  55 #include "cpu/inorder/thread_state.hh"
  56 #include "cpu/inorder/reg_dep_map.hh"
  57 #include "cpu/o3/dep_graph.hh"
  58 #include "cpu/o3/rename_map.hh"
  59 #include "mem/packet.hh"
  60 #include "mem/port.hh"
  61 #include "mem/request.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/process.hh"
  64
  65 class ThreadContext;
  66 class MemInterface;
  67 class MemObject;
  68 class Process;
  69 class ResourcePool;
  70
  71 class InOrderCPU : public BaseCPU
  72 {
  73
  74   protected:
  75     typedef ThePipeline::Params Params;
  76     typedef InOrderThreadState Thread;
  77
  78    //ISA TypeDefs
  79     typedef TheISA::IntReg IntReg;
  80     typedef TheISA::FloatReg FloatReg;
  81     typedef TheISA::FloatRegBits FloatRegBits;
  82     typedef TheISA::MiscReg MiscReg;
  83
  84     //DynInstPtr TypeDefs
  85     typedef ThePipeline::DynInstPtr DynInstPtr;
  86     typedef std::list<DynInstPtr>::iterator ListIt;
  87
  88     //TimeBuffer TypeDefs
  89     typedef TimeBuffer<InterStageStruct> StageQueue;
  90
  91     friend class Resource;
  92
  93   public:
  94     /** Constructs a CPU with the given parameters. */
  95     InOrderCPU(Params *params);
  96     /* Destructor */
  97     ~InOrderCPU();
  98
  99     /** CPU ID */
 100     int cpu_id;
 101
 102     // SE Mode ASIDs
 103     ThreadID asid[ThePipeline::MaxThreads];
 104
 105     /** Type of core that this is */
 106     std::string coreType;
 107
 108     // Only need for SE MODE
 109     enum ThreadModel {
 110         Single,
 111         SMT,
 112         SwitchOnCacheMiss
 113     };
 114
 115     ThreadModel threadModel;
 116
 117     int readCpuId() { return cpu_id; }
 118
 119     void setCpuId(int val) { cpu_id = val; }
 120
 121     Params *cpu_params;
 122
 123   public:
 124     enum Status {
 125         Running,
 126         Idle,
 127         Halted,
 128         Blocked,
 129         SwitchedOut
 130     };
 131
 132     /** Overall CPU status. */
 133     Status _status;
 134   private:
 135     /** Define TickEvent for the CPU */
 136     class TickEvent : public Event
 137     {
 138       private:
 139         /** Pointer to the CPU. */
 140         InOrderCPU *cpu;
 141
 142       public:
 143         /** Constructs a tick event. */
 144         TickEvent(InOrderCPU *c);
 145
 146         /** Processes a tick event, calling tick() on the CPU. */
 147         void process();
 148
 149         /** Returns the description of the tick event. */
 150         const char *description();
 151     };
 152
 153     /** The tick event used for scheduling CPU ticks. */
 154     TickEvent tickEvent;
 155
 156     /** Schedule tick event, regardless of its current state. */
 157     void scheduleTickEvent(int delay)
 158     {
 159         assert(!tickEvent.scheduled() || tickEvent.squashed());
 160         reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
 161     }
 162
 163     /** Unschedule tick event, regardless of its current state. */
 164     void unscheduleTickEvent()
 165     {
 166         if (tickEvent.scheduled())
 167             tickEvent.squash();
 168     }
 169
 170   public:
 171     // List of Events That can be scheduled from
 172     // within the CPU.
 173     // NOTE(1): The Resource Pool also uses this event list
 174     // to schedule events broadcast to all resources interfaces
 175     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 176     // pool event.
 177     enum CPUEventType {
 178         ActivateThread,
 179         ActivateNextReadyThread,
 180         DeactivateThread,
 181         HaltThread,
 182         SuspendThread,
 183         Trap,
 184         InstGraduated,
 185         SquashFromMemStall,
 186         UpdatePCs,
 187         NumCPUEvents
 188     };
 189
 190     static std::string eventNames[NumCPUEvents];
 191
 192     /** Define CPU Event */
 193     class CPUEvent : public Event
 194     {
 195       protected:
 196         InOrderCPU *cpu;
 197
 198       public:
 199         CPUEventType cpuEventType;
 200         ThreadID tid;
 201         DynInstPtr inst;
 202         Fault fault;
 203         unsigned vpe;
 204
 205       public:
 206         /** Constructs a CPU event. */
 207         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 208                  ThreadID _tid, DynInstPtr inst, unsigned event_pri_offset);
 209
 210         /** Set Type of Event To Be Scheduled */
 211         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 212                       DynInstPtr _inst)
 213         {
 214             fault = _fault;
 215             cpuEventType = e_type;
 216             tid = _tid;
 217             inst = _inst;
 218             vpe = 0;
 219         }
 220
 221         /** Processes a CPU event. */
 222         void process();
 223
 224         /** Returns the description of the CPU event. */
 225         const char *description();
 226
 227         /** Schedule Event */
 228         void scheduleEvent(int delay);
 229
 230         /** Unschedule This Event */
 231         void unscheduleEvent();
 232     };
 233
 234     /** Schedule a CPU Event */
 235     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 236                           DynInstPtr inst, unsigned delay = 0,
 237                           unsigned event_pri_offset = 0);
 238
 239   public:
 240     /** Interface between the CPU and CPU resources. */
 241     ResourcePool *resPool;
 242
 243     /** Instruction used to signify that there is no *real* instruction in
 244         buffer slot */
 245     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 246     DynInstPtr dummyBufferInst;
 247     DynInstPtr dummyReqInst;
 248
 249     /** Used by resources to signify a denied access to a resource. */
 250     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 251
 252     /** Identifies the resource id that identifies a fetch
 253      * access unit.
 254      */
 255     unsigned fetchPortIdx;
 256
 257     /** Identifies the resource id that identifies a ITB       */
 258     unsigned itbIdx;
 259
 260     /** Identifies the resource id that identifies a data
 261      * access unit.
 262      */
 263     unsigned dataPortIdx;
 264
 265     /** Identifies the resource id that identifies a DTB       */
 266     unsigned dtbIdx;
 267
 268     /** The Pipeline Stages for the CPU */
 269     PipelineStage *pipelineStage[ThePipeline::NumStages];
 270
 271     /** Width (processing bandwidth) of each stage */
 272     int stageWidth;
 273
 274     /** Program Counters */
 275     TheISA::PCState pc[ThePipeline::MaxThreads];
 276
 277     /** The Register File for the CPU */
 278     union {
 279         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 280         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 281     } floatRegs;
 282     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 283
 284     /** ISA state */
 285     TheISA::ISA isa[ThePipeline::MaxThreads];
 286
 287     /** Dependency Tracker for Integer & Floating Point Regs */
 288     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 289
 290     /** Global communication structure */
 291     TimeBuffer<TimeStruct> timeBuffer;
 292
 293     /** Communication structure that sits in between pipeline stages */
 294     StageQueue *stageQueue[ThePipeline::NumStages-1];
 295
 296     TheISA::TLB *getITBPtr();
 297     TheISA::TLB *getDTBPtr();
 298
 299     /** Accessor Type for the SkedCache */
 300     typedef uint32_t SkedID;
 301
 302     /** Cache of Instruction Schedule using the instruction's name as a key */
 303     static std::map<SkedID, ThePipeline::RSkedPtr> skedCache;
 304
 305     typedef std::map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 306
 307     /** Initialized to last iterator in map, signifying a invalid entry
 308         on map searches
 309     */
 310     SkedCacheIt endOfSkedIt;
 311
 312     /** Add a new instruction schedule to the schedule cache */
 313     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 314     {
 315         SkedID sked_id = genSkedID(inst);
 316         skedCache[sked_id] = inst_sked;
 317     }
 318
 319
 320     /** Find a instruction schedule */
 321     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 322     {
 323         SkedID sked_id = genSkedID(inst);
 324         SkedCacheIt lookup_it = skedCache.find(sked_id);
 325
 326         if (lookup_it != endOfSkedIt) {
 327             return (*lookup_it).second;
 328         } else {
 329             return NULL;
 330         }
 331     }
 332
 333     static const uint8_t INST_OPCLASS                       = 26;
 334     static const uint8_t INST_LOAD                          = 25;
 335     static const uint8_t INST_STORE                         = 24;
 336     static const uint8_t INST_CONTROL                       = 23;
 337     static const uint8_t INST_NONSPEC                       = 22;
 338     static const uint8_t INST_DEST_REGS                     = 18;
 339     static const uint8_t INST_SRC_REGS                      = 14;
 340
 341     inline SkedID genSkedID(DynInstPtr inst)
 342     {
 343         SkedID id = 0;
 344         id = (inst->opClass() << INST_OPCLASS) |
 345             (inst->isLoad() << INST_LOAD) |
 346             (inst->isStore() << INST_STORE) |
 347             (inst->isControl() << INST_CONTROL) |
 348             (inst->isNonSpeculative() << INST_NONSPEC) |
 349             (inst->numDestRegs() << INST_DEST_REGS) |
 350             (inst->numSrcRegs() << INST_SRC_REGS);
 351         return id;
 352     }
 353
 354
 355   public:
 356
 357     /** Registers statistics. */
 358     void regStats();
 359
 360     /** Ticks CPU, calling tick() on each stage, and checking the overall
 361      *  activity to see if the CPU should deschedule itself.
 362      */
 363     void tick();
 364
 365     /** Initialize the CPU */
 366     void init();
 367
 368     /** Reset State in the CPU */
 369     void reset();
 370
 371     /** Get a Memory Port */
 372     Port* getPort(const std::string &if_name, int idx = 0);
 373
 374 #if FULL_SYSTEM
 375     /** HW return from error interrupt. */
 376     Fault hwrei(ThreadID tid);
 377
 378     bool simPalCheck(int palFunc, ThreadID tid);
 379
 380     /** Returns the Fault for any valid interrupt. */
 381     Fault getInterrupts();
 382
 383     /** Processes any an interrupt fault. */
 384     void processInterrupts(Fault interrupt);
 385
 386     /** Halts the CPU. */
 387     void halt() { panic("Halt not implemented!\n"); }
 388
 389     /** Update the Virt and Phys ports of all ThreadContexts to
 390      * reflect change in memory connections. */
 391     void updateMemPorts();
 392
 393     /** Check if this address is a valid instruction address. */
 394     bool validInstAddr(Addr addr) { return true; }
 395
 396     /** Check if this address is a valid data address. */
 397     bool validDataAddr(Addr addr) { return true; }
 398 #endif
 399
 400     /** trap() - sets up a trap event on the cpuTraps to handle given fault.
 401      *  trapCPU() - Traps to handle given fault
 402      */
 403     void trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
 404     void trapCPU(Fault fault, ThreadID tid, DynInstPtr inst);
 405
 406     /** Add Thread to Active Threads List. */
 407     void activateContext(ThreadID tid, int delay = 0);
 408     void activateThread(ThreadID tid);
 409     void activateThreadInPipeline(ThreadID tid);
 410
 411     /** Add Thread to Active Threads List. */
 412     void activateNextReadyContext(int delay = 0);
 413     void activateNextReadyThread();
 414
 415     /** Remove from Active Thread List */
 416     void deactivateContext(ThreadID tid, int delay = 0);
 417     void deactivateThread(ThreadID tid);
 418
 419     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 420     void suspendContext(ThreadID tid, int delay = 0);
 421     void suspendThread(ThreadID tid);
 422
 423     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 424      *  Threads List
 425      */
 426     void haltContext(ThreadID tid, int delay = 0);
 427     void haltThread(ThreadID tid);
 428
 429     /** squashFromMemStall() - sets up a squash event
 430      *  squashDueToMemStall() - squashes pipeline
 431      *  @note: maybe squashContext/squashThread would be better?
 432      */
 433     void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
 434     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 435
 436     void removePipelineStalls(ThreadID tid);
 437     void squashThreadInPipeline(ThreadID tid);
 438     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 439
 440     PipelineStage* getPipeStage(int stage_num);
 441
 442     int
 443     contextId()
 444     {
 445         hack_once("return a bogus context id");
 446         return 0;
 447     }
 448
 449     /** Update The Order In Which We Process Threads. */
 450     void updateThreadPriority();
 451
 452     /** Switches a Pipeline Stage to Active. (Unused currently) */
 453     void switchToActive(int stage_idx)
 454     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 455
 456     /** Get the current instruction sequence number, and increment it. */
 457     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 458     { return globalSeqNum[tid]++; }
 459
 460     /** Get the current instruction sequence number, and increment it. */
 461     InstSeqNum nextInstSeqNum(ThreadID tid)
 462     { return globalSeqNum[tid]; }
 463
 464     /** Increment Instruction Sequence Number */
 465     void incrInstSeqNum(ThreadID tid)
 466     { globalSeqNum[tid]++; }
 467
 468     /** Set Instruction Sequence Number */
 469     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 470     {
 471         globalSeqNum[tid] = seq_num;
 472     }
 473
 474     /** Get & Update Next Event Number */
 475     InstSeqNum getNextEventNum()
 476     {
 477 #ifdef DEBUG
 478         return cpuEventNum++;
 479 #else
 480         return 0;
 481 #endif
 482     }
 483
 484     /** Register file accessors  */
 485     uint64_t readIntReg(int reg_idx, ThreadID tid);
 486
 487     FloatReg readFloatReg(int reg_idx, ThreadID tid);
 488
 489     FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
 490
 491     void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
 492
 493     void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
 494
 495     void setFloatRegBits(int reg_idx, FloatRegBits val,  ThreadID tid);
 496
 497     /** Reads a miscellaneous register. */
 498     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 499
 500     /** Reads a misc. register, including any side effects the read
 501      * might have as defined by the architecture.
 502      */
 503     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 504
 505     /** Sets a miscellaneous register. */
 506     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 507                             ThreadID tid = 0);
 508
 509     /** Sets a misc. register, including any side effects the write
 510      * might have as defined by the architecture.
 511      */
 512     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 513
 514     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 515      *  target thread
 516      */
 517     uint64_t readRegOtherThread(unsigned misc_reg,
 518                                 ThreadID tid = InvalidThreadID);
 519
 520     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 521      * target thread
 522      */
 523     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 524                            ThreadID tid);
 525
 526     /** Reads the commit PC of a specific thread. */
 527     TheISA::PCState
 528     pcState(ThreadID tid)
 529     {
 530         return pc[tid];
 531     }
 532
 533     /** Sets the commit PC of a specific thread. */
 534     void
 535     pcState(const TheISA::PCState &newPC, ThreadID tid)
 536     {
 537         pc[tid] = newPC;
 538     }
 539
 540     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 541     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 542     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 543
 544     /** Function to add instruction onto the head of the list of the
 545      *  instructions.  Used when new instructions are fetched.
 546      */
 547     ListIt addInst(DynInstPtr &inst);
 548
 549     /** Function to tell the CPU that an instruction has completed. */
 550     void instDone(DynInstPtr inst, ThreadID tid);
 551
 552     /** Add Instructions to the CPU Remove List*/
 553     void addToRemoveList(DynInstPtr &inst);
 554
 555     /** Remove an instruction from CPU */
 556     void removeInst(DynInstPtr &inst);
 557
 558     /** Remove all instructions younger than the given sequence number. */
 559     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 560
 561     /** Removes the instruction pointed to by the iterator. */
 562     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 563
 564     /** Cleans up all instructions on the instruction remove list. */
 565     void cleanUpRemovedInsts();
 566
 567     /** Cleans up all instructions on the request remove list. */
 568     void cleanUpRemovedReqs();
 569
 570     /** Cleans up all instructions on the CPU event remove list. */
 571     void cleanUpRemovedEvents();
 572
 573     /** Debug function to print all instructions on the list. */
 574     void dumpInsts();
 575
 576     /** Forwards an instruction read to the appropriate data
 577      *  resource (indexes into Resource Pool thru "dataPortIdx")
 578      */
 579     Fault read(DynInstPtr inst, Addr addr,
 580                uint8_t *data, unsigned size, unsigned flags);
 581
 582     /** Forwards an instruction write. to the appropriate data
 583      *  resource (indexes into Resource Pool thru "dataPortIdx")
 584      */
 585     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 586                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 587
 588     /** Executes a syscall.*/
 589     void syscall(int64_t callnum, ThreadID tid);
 590
 591   public:
 592     /** Per-Thread List of all the instructions in flight. */
 593     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 594
 595     /** List of all the instructions that will be removed at the end of this
 596      *  cycle.
 597      */
 598     std::queue<ListIt> removeList;
 599
 600     /** List of all the resource requests that will be removed at the end
 601      *  of this cycle.
 602      */
 603     std::queue<ResourceRequest*> reqRemoveList;
 604
 605     /** List of all the cpu event requests that will be removed at the end of
 606      *  the current cycle.
 607      */
 608     std::queue<Event*> cpuEventRemoveList;
 609
 610     /** Records if instructions need to be removed this cycle due to
 611      *  being retired or squashed.
 612      */
 613     bool removeInstsThisCycle;
 614
 615     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 616      * execution unit know, NOT to execute while the instruction is active.
 617      */
 618     bool nonSpecInstActive[ThePipeline::MaxThreads];
 619
 620     /** Instruction Seq. Num of current non-speculative instruction. */
 621     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 622
 623     /** Instruction Seq. Num of last instruction squashed in pipeline */
 624     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 625
 626     /** Last Cycle that the CPU squashed instruction end. */
 627     Tick lastSquashCycle[ThePipeline::MaxThreads];
 628
 629     std::list<ThreadID> fetchPriorityList;
 630
 631   protected:
 632     /** Active Threads List */
 633     std::list<ThreadID> activeThreads;
 634
 635     /** Ready Threads List */
 636     std::list<ThreadID> readyThreads;
 637
 638     /** Suspended Threads List */
 639     std::list<ThreadID> suspendedThreads;
 640
 641     /** Halted Threads List */
 642     std::list<ThreadID> haltedThreads;
 643
 644     /** Thread Status Functions */
 645     bool isThreadActive(ThreadID tid);
 646     bool isThreadReady(ThreadID tid);
 647     bool isThreadSuspended(ThreadID tid);
 648
 649   private:
 650     /** The activity recorder; used to tell if the CPU has any
 651      * activity remaining or if it can go to idle and deschedule
 652      * itself.
 653      */
 654     ActivityRecorder activityRec;
 655
 656   public:
 657     /** Number of Active Threads in the CPU */
 658     ThreadID numActiveThreads() { return activeThreads.size(); }
 659
 660     /** Thread id of active thread
 661      *  Only used for SwitchOnCacheMiss model.
 662      *  Assumes only 1 thread active
 663      */
 664     ThreadID activeThreadId()
 665     {
 666         if (numActiveThreads() > 0)
 667             return activeThreads.front();
 668         else
 669             return InvalidThreadID;
 670     }
 671
 672
 673     /** Records that there was time buffer activity this cycle. */
 674     void activityThisCycle() { activityRec.activity(); }
 675
 676     /** Changes a stage's status to active within the activity recorder. */
 677     void activateStage(const int idx)
 678     { activityRec.activateStage(idx); }
 679
 680     /** Changes a stage's status to inactive within the activity recorder. */
 681     void deactivateStage(const int idx)
 682     { activityRec.deactivateStage(idx); }
 683
 684     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 685     void wakeCPU();
 686
 687 #if FULL_SYSTEM
 688     virtual void wakeup();
 689 #endif
 690
 691     // LL/SC debug functionality
 692     unsigned stCondFails;
 693
 694     unsigned readStCondFailures()
 695     { return stCondFails; }
 696
 697     unsigned setStCondFailures(unsigned st_fails)
 698     { return stCondFails = st_fails; }
 699
 700     /** Returns a pointer to a thread context. */
 701     ThreadContext *tcBase(ThreadID tid = 0)
 702     {
 703         return thread[tid]->getTC();
 704     }
 705
 706     /** Count the Total Instructions Committed in the CPU. */
 707     virtual Counter totalInstructions() const
 708     {
 709         Counter total(0);
 710
 711         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 712             total += thread[tid]->numInst;
 713
 714         return total;
 715     }
 716
 717 #if FULL_SYSTEM
 718     /** Pointer to the system. */
 719     System *system;
 720
 721     /** Pointer to physical memory. */
 722     PhysicalMemory *physmem;
 723 #endif
 724
 725     /** The global sequence number counter. */
 726     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 727
 728 #ifdef DEBUG
 729     /** The global event number counter. */
 730     InstSeqNum cpuEventNum;
 731
 732     /** Number of resource requests active in CPU **/
 733     unsigned resReqCount;
 734 #endif
 735
 736     /** Counter of how many stages have completed switching out. */
 737     int switchCount;
 738
 739     /** Pointers to all of the threads in the CPU. */
 740     std::vector<Thread *> thread;
 741
 742     /** Pointer to the icache interface. */
 743     MemInterface *icacheInterface;
 744
 745     /** Pointer to the dcache interface. */
 746     MemInterface *dcacheInterface;
 747
 748     /** Whether or not the CPU should defer its registration. */
 749     bool deferRegistration;
 750
 751     /** Per-Stage Instruction Tracing */
 752     bool stageTracing;
 753
 754     /** The cycle that the CPU was last running, used for statistics. */
 755     Tick lastRunningCycle;
 756
 757     void updateContextSwitchStats();
 758     unsigned instsPerSwitch;
 759     Stats::Average instsPerCtxtSwitch;
 760     Stats::Scalar numCtxtSwitches;
 761
 762     /** Update Thread , used for statistic purposes*/
 763     inline void tickThreadStats();
 764
 765     /** Per-Thread Tick */
 766     Stats::Vector threadCycles;
 767
 768     /** Tick for SMT */
 769     Stats::Scalar smtCycles;
 770
 771     /** Stat for total number of times the CPU is descheduled. */
 772     Stats::Scalar timesIdled;
 773
 774     /** Stat for total number of cycles the CPU spends descheduled or no
 775      *  stages active.
 776      */
 777     Stats::Scalar idleCycles;
 778
 779     /** Stat for total number of cycles the CPU is active. */
 780     Stats::Scalar runCycles;
 781
 782     /** Percentage of cycles a stage was active */
 783     Stats::Formula activity;
 784
 785     /** Instruction Mix Stats */
 786     Stats::Scalar comLoads;
 787     Stats::Scalar comStores;
 788     Stats::Scalar comBranches;
 789     Stats::Scalar comNops;
 790     Stats::Scalar comNonSpec;
 791     Stats::Scalar comInts;
 792     Stats::Scalar comFloats;
 793
 794     /** Stat for the number of committed instructions per thread. */
 795     Stats::Vector committedInsts;
 796
 797     /** Stat for the number of committed instructions per thread. */
 798     Stats::Vector smtCommittedInsts;
 799
 800     /** Stat for the total number of committed instructions. */
 801     Stats::Scalar totalCommittedInsts;
 802
 803     /** Stat for the CPI per thread. */
 804     Stats::Formula cpi;
 805
 806     /** Stat for the SMT-CPI per thread. */
 807     Stats::Formula smtCpi;
 808
 809     /** Stat for the total CPI. */
 810     Stats::Formula totalCpi;
 811
 812     /** Stat for the IPC per thread. */
 813     Stats::Formula ipc;
 814
 815     /** Stat for the total IPC. */
 816     Stats::Formula smtIpc;
 817
 818     /** Stat for the total IPC. */
 819     Stats::Formula totalIpc;
 820 };
 821
 822 #endif // __CPU_O3_CPU_HH__