2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_CPU_HH__
33 #define __CPU_INORDER_CPU_HH__
41 #include "arch/isa_traits.hh"
42 #include "arch/types.hh"
43 #include "arch/registers.hh"
44 #include "base/statistics.hh"
45 #include "cpu/timebuf.hh"
46 #include "base/types.hh"
47 #include "config/full_system.hh"
48 #include "config/the_isa.hh"
49 #include "cpu/activity.hh"
50 #include "cpu/base.hh"
51 #include "cpu/simple_thread.hh"
52 #include "cpu/inorder/inorder_dyn_inst.hh"
53 #include "cpu/inorder/pipeline_traits.hh"
54 #include "cpu/inorder/pipeline_stage.hh"
55 #include "cpu/inorder/thread_state.hh"
56 #include "cpu/inorder/reg_dep_map.hh"
57 #include "cpu/o3/dep_graph.hh"
58 #include "cpu/o3/rename_map.hh"
59 #include "mem/packet.hh"
60 #include "mem/port.hh"
61 #include "mem/request.hh"
62 #include "sim/eventq.hh"
63 #include "sim/process.hh"
71 class InOrderCPU : public BaseCPU
75 typedef ThePipeline::Params Params;
76 typedef InOrderThreadState Thread;
79 typedef TheISA::IntReg IntReg;
80 typedef TheISA::FloatReg FloatReg;
81 typedef TheISA::FloatRegBits FloatRegBits;
82 typedef TheISA::MiscReg MiscReg;
85 typedef ThePipeline::DynInstPtr DynInstPtr;
86 typedef std::list<DynInstPtr>::iterator ListIt;
89 typedef TimeBuffer<InterStageStruct> StageQueue;
91 friend class Resource;
94 /** Constructs a CPU with the given parameters. */
95 InOrderCPU(Params *params);
103 ThreadID asid[ThePipeline::MaxThreads];
105 /** Type of core that this is */
106 std::string coreType;
108 // Only need for SE MODE
115 ThreadModel threadModel;
117 int readCpuId() { return cpu_id; }
119 void setCpuId(int val) { cpu_id = val; }
132 /** Overall CPU status. */
135 /** Define TickEvent for the CPU */
136 class TickEvent : public Event
139 /** Pointer to the CPU. */
143 /** Constructs a tick event. */
144 TickEvent(InOrderCPU *c);
146 /** Processes a tick event, calling tick() on the CPU. */
149 /** Returns the description of the tick event. */
150 const char *description();
153 /** The tick event used for scheduling CPU ticks. */
156 /** Schedule tick event, regardless of its current state. */
157 void scheduleTickEvent(int delay)
159 assert(!tickEvent.scheduled() || tickEvent.squashed());
160 reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
163 /** Unschedule tick event, regardless of its current state. */
164 void unscheduleTickEvent()
166 if (tickEvent.scheduled())
171 // List of Events That can be scheduled from
173 // NOTE(1): The Resource Pool also uses this event list
174 // to schedule events broadcast to all resources interfaces
175 // NOTE(2): CPU Events usually need to schedule a corresponding resource
179 ActivateNextReadyThread,
190 static std::string eventNames[NumCPUEvents];
192 /** Define CPU Event */
193 class CPUEvent : public Event
199 CPUEventType cpuEventType;
206 /** Constructs a CPU event. */
207 CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
208 ThreadID _tid, DynInstPtr inst, unsigned event_pri_offset);
210 /** Set Type of Event To Be Scheduled */
211 void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
215 cpuEventType = e_type;
221 /** Processes a CPU event. */
224 /** Returns the description of the CPU event. */
225 const char *description();
227 /** Schedule Event */
228 void scheduleEvent(int delay);
230 /** Unschedule This Event */
231 void unscheduleEvent();
234 /** Schedule a CPU Event */
235 void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
236 DynInstPtr inst, unsigned delay = 0,
237 unsigned event_pri_offset = 0);
240 /** Interface between the CPU and CPU resources. */
241 ResourcePool *resPool;
243 /** Instruction used to signify that there is no *real* instruction in
245 DynInstPtr dummyInst[ThePipeline::MaxThreads];
246 DynInstPtr dummyBufferInst;
247 DynInstPtr dummyReqInst;
249 /** Used by resources to signify a denied access to a resource. */
250 ResourceRequest *dummyReq[ThePipeline::MaxThreads];
252 /** Identifies the resource id that identifies a fetch
255 unsigned fetchPortIdx;
257 /** Identifies the resource id that identifies a ITB */
260 /** Identifies the resource id that identifies a data
263 unsigned dataPortIdx;
265 /** Identifies the resource id that identifies a DTB */
268 /** The Pipeline Stages for the CPU */
269 PipelineStage *pipelineStage[ThePipeline::NumStages];
271 /** Width (processing bandwidth) of each stage */
274 /** Program Counters */
275 TheISA::PCState pc[ThePipeline::MaxThreads];
277 /** The Register File for the CPU */
279 FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
280 FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
282 TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
285 TheISA::ISA isa[ThePipeline::MaxThreads];
287 /** Dependency Tracker for Integer & Floating Point Regs */
288 RegDepMap archRegDepMap[ThePipeline::MaxThreads];
290 /** Global communication structure */
291 TimeBuffer<TimeStruct> timeBuffer;
293 /** Communication structure that sits in between pipeline stages */
294 StageQueue *stageQueue[ThePipeline::NumStages-1];
296 TheISA::TLB *getITBPtr();
297 TheISA::TLB *getDTBPtr();
299 /** Accessor Type for the SkedCache */
300 typedef uint32_t SkedID;
302 /** Cache of Instruction Schedule using the instruction's name as a key */
303 static std::map<SkedID, ThePipeline::RSkedPtr> skedCache;
305 typedef std::map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
307 /** Initialized to last iterator in map, signifying a invalid entry
310 SkedCacheIt endOfSkedIt;
312 ThePipeline::RSkedPtr frontEndSked;
314 /** Add a new instruction schedule to the schedule cache */
315 void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
317 SkedID sked_id = genSkedID(inst);
318 skedCache[sked_id] = inst_sked;
322 /** Find a instruction schedule */
323 ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
325 SkedID sked_id = genSkedID(inst);
326 SkedCacheIt lookup_it = skedCache.find(sked_id);
328 if (lookup_it != endOfSkedIt) {
329 return (*lookup_it).second;
335 static const uint8_t INST_OPCLASS = 26;
336 static const uint8_t INST_LOAD = 25;
337 static const uint8_t INST_STORE = 24;
338 static const uint8_t INST_CONTROL = 23;
339 static const uint8_t INST_NONSPEC = 22;
340 static const uint8_t INST_DEST_REGS = 18;
341 static const uint8_t INST_SRC_REGS = 14;
343 inline SkedID genSkedID(DynInstPtr inst)
346 id = (inst->opClass() << INST_OPCLASS) |
347 (inst->isLoad() << INST_LOAD) |
348 (inst->isStore() << INST_STORE) |
349 (inst->isControl() << INST_CONTROL) |
350 (inst->isNonSpeculative() << INST_NONSPEC) |
351 (inst->numDestRegs() << INST_DEST_REGS) |
352 (inst->numSrcRegs() << INST_SRC_REGS);
356 ThePipeline::RSkedPtr createFrontEndSked();
357 ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
359 class StageScheduler {
361 ThePipeline::RSkedPtr rsked;
363 int nextTaskPriority;
366 StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
367 : rsked(_rsked), stageNum(stage_num),
371 void needs(int unit, int request) {
372 rsked->push(new ScheduleEntry(
373 stageNum, nextTaskPriority++, unit, request
377 void needs(int unit, int request, int param) {
378 rsked->push(new ScheduleEntry(
379 stageNum, nextTaskPriority++, unit, request, param
386 /** Registers statistics. */
389 /** Ticks CPU, calling tick() on each stage, and checking the overall
390 * activity to see if the CPU should deschedule itself.
394 /** Initialize the CPU */
397 /** Reset State in the CPU */
400 /** Get a Memory Port */
401 Port* getPort(const std::string &if_name, int idx = 0);
404 /** HW return from error interrupt. */
405 Fault hwrei(ThreadID tid);
407 bool simPalCheck(int palFunc, ThreadID tid);
409 /** Returns the Fault for any valid interrupt. */
410 Fault getInterrupts();
412 /** Processes any an interrupt fault. */
413 void processInterrupts(Fault interrupt);
415 /** Halts the CPU. */
416 void halt() { panic("Halt not implemented!\n"); }
418 /** Update the Virt and Phys ports of all ThreadContexts to
419 * reflect change in memory connections. */
420 void updateMemPorts();
422 /** Check if this address is a valid instruction address. */
423 bool validInstAddr(Addr addr) { return true; }
425 /** Check if this address is a valid data address. */
426 bool validDataAddr(Addr addr) { return true; }
429 /** trap() - sets up a trap event on the cpuTraps to handle given fault.
430 * trapCPU() - Traps to handle given fault
432 void trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
433 void trapCPU(Fault fault, ThreadID tid, DynInstPtr inst);
435 /** Add Thread to Active Threads List. */
436 void activateContext(ThreadID tid, int delay = 0);
437 void activateThread(ThreadID tid);
438 void activateThreadInPipeline(ThreadID tid);
440 /** Add Thread to Active Threads List. */
441 void activateNextReadyContext(int delay = 0);
442 void activateNextReadyThread();
444 /** Remove from Active Thread List */
445 void deactivateContext(ThreadID tid, int delay = 0);
446 void deactivateThread(ThreadID tid);
448 /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
449 void suspendContext(ThreadID tid, int delay = 0);
450 void suspendThread(ThreadID tid);
452 /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
455 void haltContext(ThreadID tid, int delay = 0);
456 void haltThread(ThreadID tid);
458 /** squashFromMemStall() - sets up a squash event
459 * squashDueToMemStall() - squashes pipeline
460 * @note: maybe squashContext/squashThread would be better?
462 void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
463 void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
465 void removePipelineStalls(ThreadID tid);
466 void squashThreadInPipeline(ThreadID tid);
467 void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
469 PipelineStage* getPipeStage(int stage_num);
474 hack_once("return a bogus context id");
478 /** Update The Order In Which We Process Threads. */
479 void updateThreadPriority();
481 /** Switches a Pipeline Stage to Active. (Unused currently) */
482 void switchToActive(int stage_idx)
483 { /*pipelineStage[stage_idx]->switchToActive();*/ }
485 /** Get the current instruction sequence number, and increment it. */
486 InstSeqNum getAndIncrementInstSeq(ThreadID tid)
487 { return globalSeqNum[tid]++; }
489 /** Get the current instruction sequence number, and increment it. */
490 InstSeqNum nextInstSeqNum(ThreadID tid)
491 { return globalSeqNum[tid]; }
493 /** Increment Instruction Sequence Number */
494 void incrInstSeqNum(ThreadID tid)
495 { globalSeqNum[tid]++; }
497 /** Set Instruction Sequence Number */
498 void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
500 globalSeqNum[tid] = seq_num;
503 /** Get & Update Next Event Number */
504 InstSeqNum getNextEventNum()
507 return cpuEventNum++;
513 /** Register file accessors */
514 uint64_t readIntReg(int reg_idx, ThreadID tid);
516 FloatReg readFloatReg(int reg_idx, ThreadID tid);
518 FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
520 void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
522 void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
524 void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid);
526 /** Reads a miscellaneous register. */
527 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
529 /** Reads a misc. register, including any side effects the read
530 * might have as defined by the architecture.
532 MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
534 /** Sets a miscellaneous register. */
535 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
538 /** Sets a misc. register, including any side effects the write
539 * might have as defined by the architecture.
541 void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
543 /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
546 uint64_t readRegOtherThread(unsigned misc_reg,
547 ThreadID tid = InvalidThreadID);
549 /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
552 void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
555 /** Reads the commit PC of a specific thread. */
557 pcState(ThreadID tid)
562 /** Sets the commit PC of a specific thread. */
564 pcState(const TheISA::PCState &newPC, ThreadID tid)
569 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
570 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
571 MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
573 /** Function to add instruction onto the head of the list of the
574 * instructions. Used when new instructions are fetched.
576 ListIt addInst(DynInstPtr &inst);
578 /** Function to tell the CPU that an instruction has completed. */
579 void instDone(DynInstPtr inst, ThreadID tid);
581 /** Add Instructions to the CPU Remove List*/
582 void addToRemoveList(DynInstPtr &inst);
584 /** Remove an instruction from CPU */
585 void removeInst(DynInstPtr &inst);
587 /** Remove all instructions younger than the given sequence number. */
588 void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
590 /** Removes the instruction pointed to by the iterator. */
591 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
593 /** Cleans up all instructions on the instruction remove list. */
594 void cleanUpRemovedInsts();
596 /** Cleans up all instructions on the request remove list. */
597 void cleanUpRemovedReqs();
599 /** Cleans up all instructions on the CPU event remove list. */
600 void cleanUpRemovedEvents();
602 /** Debug function to print all instructions on the list. */
605 /** Forwards an instruction read to the appropriate data
606 * resource (indexes into Resource Pool thru "dataPortIdx")
608 Fault read(DynInstPtr inst, Addr addr,
609 uint8_t *data, unsigned size, unsigned flags);
611 /** Forwards an instruction write. to the appropriate data
612 * resource (indexes into Resource Pool thru "dataPortIdx")
614 Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
615 Addr addr, unsigned flags, uint64_t *write_res = NULL);
617 /** Executes a syscall.*/
618 void syscall(int64_t callnum, ThreadID tid);
621 /** Per-Thread List of all the instructions in flight. */
622 std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
624 /** List of all the instructions that will be removed at the end of this
627 std::queue<ListIt> removeList;
629 /** List of all the resource requests that will be removed at the end
632 std::queue<ResourceRequest*> reqRemoveList;
634 /** List of all the cpu event requests that will be removed at the end of
637 std::queue<Event*> cpuEventRemoveList;
639 /** Records if instructions need to be removed this cycle due to
640 * being retired or squashed.
642 bool removeInstsThisCycle;
644 /** True if there is non-speculative Inst Active In Pipeline. Lets any
645 * execution unit know, NOT to execute while the instruction is active.
647 bool nonSpecInstActive[ThePipeline::MaxThreads];
649 /** Instruction Seq. Num of current non-speculative instruction. */
650 InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
652 /** Instruction Seq. Num of last instruction squashed in pipeline */
653 InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
655 /** Last Cycle that the CPU squashed instruction end. */
656 Tick lastSquashCycle[ThePipeline::MaxThreads];
658 std::list<ThreadID> fetchPriorityList;
661 /** Active Threads List */
662 std::list<ThreadID> activeThreads;
664 /** Ready Threads List */
665 std::list<ThreadID> readyThreads;
667 /** Suspended Threads List */
668 std::list<ThreadID> suspendedThreads;
670 /** Halted Threads List */
671 std::list<ThreadID> haltedThreads;
673 /** Thread Status Functions */
674 bool isThreadActive(ThreadID tid);
675 bool isThreadReady(ThreadID tid);
676 bool isThreadSuspended(ThreadID tid);
679 /** The activity recorder; used to tell if the CPU has any
680 * activity remaining or if it can go to idle and deschedule
683 ActivityRecorder activityRec;
686 /** Number of Active Threads in the CPU */
687 ThreadID numActiveThreads() { return activeThreads.size(); }
689 /** Thread id of active thread
690 * Only used for SwitchOnCacheMiss model.
691 * Assumes only 1 thread active
693 ThreadID activeThreadId()
695 if (numActiveThreads() > 0)
696 return activeThreads.front();
698 return InvalidThreadID;
702 /** Records that there was time buffer activity this cycle. */
703 void activityThisCycle() { activityRec.activity(); }
705 /** Changes a stage's status to active within the activity recorder. */
706 void activateStage(const int idx)
707 { activityRec.activateStage(idx); }
709 /** Changes a stage's status to inactive within the activity recorder. */
710 void deactivateStage(const int idx)
711 { activityRec.deactivateStage(idx); }
713 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
717 virtual void wakeup();
720 // LL/SC debug functionality
721 unsigned stCondFails;
723 unsigned readStCondFailures()
724 { return stCondFails; }
726 unsigned setStCondFailures(unsigned st_fails)
727 { return stCondFails = st_fails; }
729 /** Returns a pointer to a thread context. */
730 ThreadContext *tcBase(ThreadID tid = 0)
732 return thread[tid]->getTC();
735 /** Count the Total Instructions Committed in the CPU. */
736 virtual Counter totalInstructions() const
740 for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
741 total += thread[tid]->numInst;
747 /** Pointer to the system. */
750 /** Pointer to physical memory. */
751 PhysicalMemory *physmem;
754 /** The global sequence number counter. */
755 InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
758 /** The global event number counter. */
759 InstSeqNum cpuEventNum;
761 /** Number of resource requests active in CPU **/
762 unsigned resReqCount;
765 /** Counter of how many stages have completed switching out. */
768 /** Pointers to all of the threads in the CPU. */
769 std::vector<Thread *> thread;
771 /** Pointer to the icache interface. */
772 MemInterface *icacheInterface;
774 /** Pointer to the dcache interface. */
775 MemInterface *dcacheInterface;
777 /** Whether or not the CPU should defer its registration. */
778 bool deferRegistration;
780 /** Per-Stage Instruction Tracing */
783 /** The cycle that the CPU was last running, used for statistics. */
784 Tick lastRunningCycle;
786 void updateContextSwitchStats();
787 unsigned instsPerSwitch;
788 Stats::Average instsPerCtxtSwitch;
789 Stats::Scalar numCtxtSwitches;
791 /** Update Thread , used for statistic purposes*/
792 inline void tickThreadStats();
794 /** Per-Thread Tick */
795 Stats::Vector threadCycles;
798 Stats::Scalar smtCycles;
800 /** Stat for total number of times the CPU is descheduled. */
801 Stats::Scalar timesIdled;
803 /** Stat for total number of cycles the CPU spends descheduled or no
806 Stats::Scalar idleCycles;
808 /** Stat for total number of cycles the CPU is active. */
809 Stats::Scalar runCycles;
811 /** Percentage of cycles a stage was active */
812 Stats::Formula activity;
814 /** Instruction Mix Stats */
815 Stats::Scalar comLoads;
816 Stats::Scalar comStores;
817 Stats::Scalar comBranches;
818 Stats::Scalar comNops;
819 Stats::Scalar comNonSpec;
820 Stats::Scalar comInts;
821 Stats::Scalar comFloats;
823 /** Stat for the number of committed instructions per thread. */
824 Stats::Vector committedInsts;
826 /** Stat for the number of committed instructions per thread. */
827 Stats::Vector smtCommittedInsts;
829 /** Stat for the total number of committed instructions. */
830 Stats::Scalar totalCommittedInsts;
832 /** Stat for the CPI per thread. */
835 /** Stat for the SMT-CPI per thread. */
836 Stats::Formula smtCpi;
838 /** Stat for the total CPI. */
839 Stats::Formula totalCpi;
841 /** Stat for the IPC per thread. */
844 /** Stat for the total IPC. */
845 Stats::Formula smtIpc;
847 /** Stat for the total IPC. */
848 Stats::Formula totalIpc;
851 #endif // __CPU_O3_CPU_HH__