2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007 MIPS Technologies, Inc.
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Korey Sewell
44 #ifndef __CPU_INORDER_CPU_HH__
45 #define __CPU_INORDER_CPU_HH__
53 #include "arch/isa_traits.hh"
54 #include "arch/registers.hh"
55 #include "arch/types.hh"
56 #include "base/statistics.hh"
57 #include "base/types.hh"
58 #include "config/the_isa.hh"
59 #include "cpu/inorder/inorder_dyn_inst.hh"
60 #include "cpu/inorder/pipeline_stage.hh"
61 #include "cpu/inorder/pipeline_traits.hh"
62 #include "cpu/inorder/reg_dep_map.hh"
63 #include "cpu/inorder/thread_state.hh"
64 #include "cpu/o3/dep_graph.hh"
65 #include "cpu/o3/rename_map.hh"
66 #include "cpu/activity.hh"
67 #include "cpu/base.hh"
68 #include "cpu/simple_thread.hh"
69 #include "cpu/timebuf.hh"
70 #include "mem/packet.hh"
71 #include "mem/port.hh"
72 #include "mem/request.hh"
73 #include "sim/eventq.hh"
74 #include "sim/process.hh"
83 class InOrderCPU : public BaseCPU
87 typedef ThePipeline::Params Params;
88 typedef InOrderThreadState Thread;
91 typedef TheISA::IntReg IntReg;
92 typedef TheISA::FloatReg FloatReg;
93 typedef TheISA::FloatRegBits FloatRegBits;
94 typedef TheISA::MiscReg MiscReg;
95 typedef TheISA::RegIndex RegIndex;
98 typedef ThePipeline::DynInstPtr DynInstPtr;
99 typedef std::list<DynInstPtr>::iterator ListIt;
101 //TimeBuffer TypeDefs
102 typedef TimeBuffer<InterStageStruct> StageQueue;
104 friend class Resource;
107 /** Constructs a CPU with the given parameters. */
108 InOrderCPU(Params *params);
112 /** Return a reference to the data port. */
113 virtual CpuPort &getDataPort() { return dataPort; }
115 /** Return a reference to the instruction port. */
116 virtual CpuPort &getInstPort() { return instPort; }
122 ThreadID asid[ThePipeline::MaxThreads];
124 /** Type of core that this is */
125 std::string coreType;
127 // Only need for SE MODE
134 ThreadModel threadModel;
136 int readCpuId() { return cpu_id; }
138 void setCpuId(int val) { cpu_id = val; }
151 /** Overall CPU status. */
156 * CachePort class for the in-order CPU, interacting with a
157 * specific CacheUnit in the pipeline.
159 class CachePort : public CpuPort
163 /** Pointer to cache unit */
164 CacheUnit *cacheUnit;
167 /** Default constructor. */
168 CachePort(CacheUnit *_cacheUnit, const std::string& name);
172 /** Timing version of receive */
173 bool recvTimingResp(PacketPtr pkt);
175 /** Handles doing a retry of a failed timing request. */
178 /** Ignoring snoops for now. */
179 void recvTimingSnoopReq(PacketPtr pkt) { }
182 /** Define TickEvent for the CPU */
183 class TickEvent : public Event
186 /** Pointer to the CPU. */
190 /** Constructs a tick event. */
191 TickEvent(InOrderCPU *c);
193 /** Processes a tick event, calling tick() on the CPU. */
196 /** Returns the description of the tick event. */
197 const char *description() const;
200 /** The tick event used for scheduling CPU ticks. */
203 /** Schedule tick event, regardless of its current state. */
204 void scheduleTickEvent(int delay)
206 assert(!tickEvent.scheduled() || tickEvent.squashed());
207 reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
210 /** Unschedule tick event, regardless of its current state. */
211 void unscheduleTickEvent()
213 if (tickEvent.scheduled())
218 // List of Events That can be scheduled from
220 // NOTE(1): The Resource Pool also uses this event list
221 // to schedule events broadcast to all resources interfaces
222 // NOTE(2): CPU Events usually need to schedule a corresponding resource
226 ActivateNextReadyThread,
237 static std::string eventNames[NumCPUEvents];
240 InOrderCPU_Pri = Event::CPU_Tick_Pri,
241 Syscall_Pri = Event::CPU_Tick_Pri + 9,
242 ActivateNextReadyThread_Pri = Event::CPU_Tick_Pri + 10
245 /** Define CPU Event */
246 class CPUEvent : public Event
252 CPUEventType cpuEventType;
260 /** Constructs a CPU event. */
261 CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
262 ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
264 /** Set Type of Event To Be Scheduled */
265 void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
269 cpuEventType = e_type;
275 /** Processes a CPU event. */
278 /** Returns the description of the CPU event. */
279 const char *description() const;
281 /** Schedule Event */
282 void scheduleEvent(int delay);
284 /** Unschedule This Event */
285 void unscheduleEvent();
288 /** Schedule a CPU Event */
289 void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
290 DynInstPtr inst, unsigned delay = 0,
291 CPUEventPri event_pri = InOrderCPU_Pri);
295 /** Width (processing bandwidth) of each stage */
298 /** Interface between the CPU and CPU resources. */
299 ResourcePool *resPool;
301 /** Instruction used to signify that there is no *real* instruction in
303 DynInstPtr dummyInst[ThePipeline::MaxThreads];
304 DynInstPtr dummyBufferInst;
305 DynInstPtr dummyReqInst;
306 DynInstPtr dummyTrapInst[ThePipeline::MaxThreads];
308 /** Used by resources to signify a denied access to a resource. */
309 ResourceRequest *dummyReq[ThePipeline::MaxThreads];
311 /** The Pipeline Stages for the CPU */
312 PipelineStage *pipelineStage[ThePipeline::NumStages];
314 /** Program Counters */
315 TheISA::PCState pc[ThePipeline::MaxThreads];
317 /** Last Committed PC */
318 TheISA::PCState lastCommittedPC[ThePipeline::MaxThreads];
320 /** The Register File for the CPU */
322 FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
323 FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
325 TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
328 TheISA::ISA isa[ThePipeline::MaxThreads];
330 /** Dependency Tracker for Integer & Floating Point Regs */
331 RegDepMap archRegDepMap[ThePipeline::MaxThreads];
333 /** Register Types Used in Dependency Tracking */
334 enum RegType { IntType, FloatType, MiscType, NumRegTypes};
336 /** Global communication structure */
337 TimeBuffer<TimeStruct> timeBuffer;
339 /** Communication structure that sits in between pipeline stages */
340 StageQueue *stageQueue[ThePipeline::NumStages-1];
342 TheISA::TLB *getITBPtr();
343 TheISA::TLB *getDTBPtr();
345 TheISA::Decoder *getDecoderPtr(unsigned tid);
347 /** Accessor Type for the SkedCache */
348 typedef uint32_t SkedID;
350 /** Cache of Instruction Schedule using the instruction's name as a key */
351 static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
353 typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
355 /** Initialized to last iterator in map, signifying a invalid entry
358 SkedCacheIt endOfSkedIt;
360 ThePipeline::RSkedPtr frontEndSked;
361 ThePipeline::RSkedPtr faultSked;
363 /** Add a new instruction schedule to the schedule cache */
364 void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
366 SkedID sked_id = genSkedID(inst);
367 assert(skedCache.find(sked_id) == skedCache.end());
368 skedCache[sked_id] = inst_sked;
372 /** Find a instruction schedule */
373 ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
375 SkedID sked_id = genSkedID(inst);
376 SkedCacheIt lookup_it = skedCache.find(sked_id);
378 if (lookup_it != endOfSkedIt) {
379 return (*lookup_it).second;
385 static const uint8_t INST_OPCLASS = 26;
386 static const uint8_t INST_LOAD = 25;
387 static const uint8_t INST_STORE = 24;
388 static const uint8_t INST_CONTROL = 23;
389 static const uint8_t INST_NONSPEC = 22;
390 static const uint8_t INST_DEST_REGS = 18;
391 static const uint8_t INST_SRC_REGS = 14;
392 static const uint8_t INST_SPLIT_DATA = 13;
394 inline SkedID genSkedID(DynInstPtr inst)
397 id = (inst->opClass() << INST_OPCLASS) |
398 (inst->isLoad() << INST_LOAD) |
399 (inst->isStore() << INST_STORE) |
400 (inst->isControl() << INST_CONTROL) |
401 (inst->isNonSpeculative() << INST_NONSPEC) |
402 (inst->numDestRegs() << INST_DEST_REGS) |
403 (inst->numSrcRegs() << INST_SRC_REGS) |
404 (inst->splitInst << INST_SPLIT_DATA);
408 ThePipeline::RSkedPtr createFrontEndSked();
409 ThePipeline::RSkedPtr createFaultSked();
410 ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
412 class StageScheduler {
414 ThePipeline::RSkedPtr rsked;
416 int nextTaskPriority;
419 StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
420 : rsked(_rsked), stageNum(stage_num),
424 void needs(int unit, int request) {
425 rsked->push(new ScheduleEntry(
426 stageNum, nextTaskPriority++, unit, request
430 void needs(int unit, int request, int param) {
431 rsked->push(new ScheduleEntry(
432 stageNum, nextTaskPriority++, unit, request, param
439 /** Data port. Note that it has to appear after the resPool. */
442 /** Instruction port. Note that it has to appear after the resPool. */
447 /** Registers statistics. */
450 /** Ticks CPU, calling tick() on each stage, and checking the overall
451 * activity to see if the CPU should deschedule itself.
455 /** Initialize the CPU */
458 /** HW return from error interrupt. */
459 Fault hwrei(ThreadID tid);
461 bool simPalCheck(int palFunc, ThreadID tid);
463 void checkForInterrupts();
465 /** Returns the Fault for any valid interrupt. */
466 Fault getInterrupts();
468 /** Processes any an interrupt fault. */
469 void processInterrupts(Fault interrupt);
471 /** Halts the CPU. */
472 void halt() { panic("Halt not implemented!\n"); }
474 /** Check if this address is a valid instruction address. */
475 bool validInstAddr(Addr addr) { return true; }
477 /** Check if this address is a valid data address. */
478 bool validDataAddr(Addr addr) { return true; }
480 /** Schedule a syscall on the CPU */
481 void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
484 /** Executes a syscall.*/
485 void syscall(int64_t callnum, ThreadID tid);
487 /** Schedule a trap on the CPU */
488 void trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
490 /** Perform trap to Handle Given Fault */
491 void trap(Fault fault, ThreadID tid, DynInstPtr inst);
493 /** Schedule thread activation on the CPU */
494 void activateContext(ThreadID tid, int delay = 0);
496 /** Add Thread to Active Threads List. */
497 void activateThread(ThreadID tid);
499 /** Activate Thread In Each Pipeline Stage */
500 void activateThreadInPipeline(ThreadID tid);
502 /** Schedule Thread Activation from Ready List */
503 void activateNextReadyContext(int delay = 0);
505 /** Add Thread From Ready List to Active Threads List. */
506 void activateNextReadyThread();
508 /** Schedule a thread deactivation on the CPU */
509 void deactivateContext(ThreadID tid, int delay = 0);
511 /** Remove from Active Thread List */
512 void deactivateThread(ThreadID tid);
514 /** Schedule a thread suspension on the CPU */
515 void suspendContext(ThreadID tid);
517 /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
518 void suspendThread(ThreadID tid);
520 /** Schedule a thread halt on the CPU */
521 void haltContext(ThreadID tid);
523 /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
526 void haltThread(ThreadID tid);
528 /** squashFromMemStall() - sets up a squash event
529 * squashDueToMemStall() - squashes pipeline
530 * @note: maybe squashContext/squashThread would be better?
532 void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
533 void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
535 void removePipelineStalls(ThreadID tid);
536 void squashThreadInPipeline(ThreadID tid);
537 void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
539 PipelineStage* getPipeStage(int stage_num);
544 hack_once("return a bogus context id");
548 /** Update The Order In Which We Process Threads. */
549 void updateThreadPriority();
551 /** Switches a Pipeline Stage to Active. (Unused currently) */
552 void switchToActive(int stage_idx)
553 { /*pipelineStage[stage_idx]->switchToActive();*/ }
555 /** Get the current instruction sequence number, and increment it. */
556 InstSeqNum getAndIncrementInstSeq(ThreadID tid)
557 { return globalSeqNum[tid]++; }
559 /** Get the current instruction sequence number, and increment it. */
560 InstSeqNum nextInstSeqNum(ThreadID tid)
561 { return globalSeqNum[tid]; }
563 /** Increment Instruction Sequence Number */
564 void incrInstSeqNum(ThreadID tid)
565 { globalSeqNum[tid]++; }
567 /** Set Instruction Sequence Number */
568 void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
570 globalSeqNum[tid] = seq_num;
573 /** Get & Update Next Event Number */
574 InstSeqNum getNextEventNum()
577 return cpuEventNum++;
583 /** Register file accessors */
584 uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
586 FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
588 FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
590 void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
592 void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
594 void setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid);
596 RegType inline getRegType(RegIndex reg_idx)
598 if (reg_idx < TheISA::FP_Base_DepTag)
600 else if (reg_idx < TheISA::Ctrl_Base_DepTag)
606 RegIndex flattenRegIdx(RegIndex reg_idx, RegType ®_type, ThreadID tid);
608 /** Reads a miscellaneous register. */
609 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
611 /** Reads a misc. register, including any side effects the read
612 * might have as defined by the architecture.
614 MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
616 /** Sets a miscellaneous register. */
617 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
620 /** Sets a misc. register, including any side effects the write
621 * might have as defined by the architecture.
623 void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
625 /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
628 uint64_t readRegOtherThread(unsigned misc_reg,
629 ThreadID tid = InvalidThreadID);
631 /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
634 void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
637 /** Reads the commit PC of a specific thread. */
639 pcState(ThreadID tid)
644 /** Sets the commit PC of a specific thread. */
646 pcState(const TheISA::PCState &newPC, ThreadID tid)
651 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
652 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
653 MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
655 /** Function to add instruction onto the head of the list of the
656 * instructions. Used when new instructions are fetched.
658 ListIt addInst(DynInstPtr inst);
660 /** Find instruction on instruction list */
661 ListIt findInst(InstSeqNum seq_num, ThreadID tid);
663 /** Function to tell the CPU that an instruction has completed. */
664 void instDone(DynInstPtr inst, ThreadID tid);
666 /** Add Instructions to the CPU Remove List*/
667 void addToRemoveList(DynInstPtr inst);
669 /** Remove an instruction from CPU */
670 void removeInst(DynInstPtr inst);
672 /** Remove all instructions younger than the given sequence number. */
673 void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
675 /** Removes the instruction pointed to by the iterator. */
676 inline void squashInstIt(const ListIt inst_it, ThreadID tid);
678 /** Cleans up all instructions on the instruction remove list. */
679 void cleanUpRemovedInsts();
681 /** Cleans up all events on the CPU event remove list. */
682 void cleanUpRemovedEvents();
684 /** Debug function to print all instructions on the list. */
687 /** Forwards an instruction read to the appropriate data
688 * resource (indexes into Resource Pool thru "dataPortIdx")
690 Fault read(DynInstPtr inst, Addr addr,
691 uint8_t *data, unsigned size, unsigned flags);
693 /** Forwards an instruction write. to the appropriate data
694 * resource (indexes into Resource Pool thru "dataPortIdx")
696 Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
697 Addr addr, unsigned flags, uint64_t *write_res = NULL);
700 /** Per-Thread List of all the instructions in flight. */
701 std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
703 /** List of all the instructions that will be removed at the end of this
706 std::queue<ListIt> removeList;
708 bool trapPending[ThePipeline::MaxThreads];
710 /** List of all the cpu event requests that will be removed at the end of
713 std::queue<Event*> cpuEventRemoveList;
715 /** Records if instructions need to be removed this cycle due to
716 * being retired or squashed.
718 bool removeInstsThisCycle;
720 /** True if there is non-speculative Inst Active In Pipeline. Lets any
721 * execution unit know, NOT to execute while the instruction is active.
723 bool nonSpecInstActive[ThePipeline::MaxThreads];
725 /** Instruction Seq. Num of current non-speculative instruction. */
726 InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
728 /** Instruction Seq. Num of last instruction squashed in pipeline */
729 InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
731 /** Last Cycle that the CPU squashed instruction end. */
732 Tick lastSquashCycle[ThePipeline::MaxThreads];
734 std::list<ThreadID> fetchPriorityList;
737 /** Active Threads List */
738 std::list<ThreadID> activeThreads;
740 /** Ready Threads List */
741 std::list<ThreadID> readyThreads;
743 /** Suspended Threads List */
744 std::list<ThreadID> suspendedThreads;
746 /** Halted Threads List */
747 std::list<ThreadID> haltedThreads;
749 /** Thread Status Functions */
750 bool isThreadActive(ThreadID tid);
751 bool isThreadReady(ThreadID tid);
752 bool isThreadSuspended(ThreadID tid);
755 /** The activity recorder; used to tell if the CPU has any
756 * activity remaining or if it can go to idle and deschedule
759 ActivityRecorder activityRec;
762 /** Number of Active Threads in the CPU */
763 ThreadID numActiveThreads() { return activeThreads.size(); }
765 /** Thread id of active thread
766 * Only used for SwitchOnCacheMiss model.
767 * Assumes only 1 thread active
769 ThreadID activeThreadId()
771 if (numActiveThreads() > 0)
772 return activeThreads.front();
774 return InvalidThreadID;
778 /** Records that there was time buffer activity this cycle. */
779 void activityThisCycle() { activityRec.activity(); }
781 /** Changes a stage's status to active within the activity recorder. */
782 void activateStage(const int idx)
783 { activityRec.activateStage(idx); }
785 /** Changes a stage's status to inactive within the activity recorder. */
786 void deactivateStage(const int idx)
787 { activityRec.deactivateStage(idx); }
789 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
792 virtual void wakeup();
794 /* LL/SC debug functionality
795 unsigned stCondFails;
797 unsigned readStCondFailures()
798 { return stCondFails; }
800 unsigned setStCondFailures(unsigned st_fails)
801 { return stCondFails = st_fails; }
804 /** Returns a pointer to a thread context. */
805 ThreadContext *tcBase(ThreadID tid = 0)
807 return thread[tid]->getTC();
810 /** Count the Total Instructions Committed in the CPU. */
811 virtual Counter totalInsts() const
815 for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
816 total += thread[tid]->numInst;
821 /** Count the Total Ops Committed in the CPU. */
822 virtual Counter totalOps() const
826 for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
827 total += thread[tid]->numOp;
832 /** Pointer to the system. */
835 /** The global sequence number counter. */
836 InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
839 /** The global event number counter. */
840 InstSeqNum cpuEventNum;
842 /** Number of resource requests active in CPU **/
843 unsigned resReqCount;
848 /** Temporary fix for the lock flag, works in the UP case. */
851 /** Counter of how many stages have completed draining */
854 /** Pointers to all of the threads in the CPU. */
855 std::vector<Thread *> thread;
857 /** Whether or not the CPU should defer its registration. */
858 bool deferRegistration;
860 /** Per-Stage Instruction Tracing */
863 /** The cycle that the CPU was last running, used for statistics. */
864 Tick lastRunningCycle;
866 void updateContextSwitchStats();
867 unsigned instsPerSwitch;
868 Stats::Average instsPerCtxtSwitch;
869 Stats::Scalar numCtxtSwitches;
871 /** Update Thread , used for statistic purposes*/
872 inline void tickThreadStats();
874 /** Per-Thread Tick */
875 Stats::Vector threadCycles;
878 Stats::Scalar smtCycles;
880 /** Stat for total number of times the CPU is descheduled. */
881 Stats::Scalar timesIdled;
883 /** Stat for total number of cycles the CPU spends descheduled or no
886 Stats::Scalar idleCycles;
888 /** Stat for total number of cycles the CPU is active. */
889 Stats::Scalar runCycles;
891 /** Percentage of cycles a stage was active */
892 Stats::Formula activity;
894 /** Instruction Mix Stats */
895 Stats::Scalar comLoads;
896 Stats::Scalar comStores;
897 Stats::Scalar comBranches;
898 Stats::Scalar comNops;
899 Stats::Scalar comNonSpec;
900 Stats::Scalar comInts;
901 Stats::Scalar comFloats;
903 /** Stat for the number of committed instructions per thread. */
904 Stats::Vector committedInsts;
906 /** Stat for the number of committed ops per thread. */
907 Stats::Vector committedOps;
909 /** Stat for the number of committed instructions per thread. */
910 Stats::Vector smtCommittedInsts;
912 /** Stat for the total number of committed instructions. */
913 Stats::Scalar totalCommittedInsts;
915 /** Stat for the CPI per thread. */
918 /** Stat for the SMT-CPI per thread. */
919 Stats::Formula smtCpi;
921 /** Stat for the total CPI. */
922 Stats::Formula totalCpi;
924 /** Stat for the IPC per thread. */
927 /** Stat for the total IPC. */
928 Stats::Formula smtIpc;
930 /** Stat for the total IPC. */
931 Stats::Formula totalIpc;
934 #endif // __CPU_O3_CPU_HH__