2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_CPU_HH__
33 #define __CPU_INORDER_CPU_HH__
41 #include "arch/isa_traits.hh"
42 #include "arch/types.hh"
43 #include "base/statistics.hh"
44 #include "base/timebuf.hh"
45 #include "base/types.hh"
46 #include "config/full_system.hh"
47 #include "cpu/activity.hh"
48 #include "cpu/base.hh"
49 #include "cpu/simple_thread.hh"
50 #include "cpu/inorder/inorder_dyn_inst.hh"
51 #include "cpu/inorder/pipeline_traits.hh"
52 #include "cpu/inorder/pipeline_stage.hh"
53 #include "cpu/inorder/thread_state.hh"
54 #include "cpu/inorder/reg_dep_map.hh"
55 #include "cpu/o3/dep_graph.hh"
56 #include "cpu/o3/rename_map.hh"
57 #include "mem/packet.hh"
58 #include "mem/port.hh"
59 #include "mem/request.hh"
60 #include "sim/eventq.hh"
61 #include "sim/process.hh"
69 class InOrderCPU : public BaseCPU
73 typedef ThePipeline::Params Params;
74 typedef InOrderThreadState Thread;
77 typedef TheISA::IntReg IntReg;
78 typedef TheISA::FloatReg FloatReg;
79 typedef TheISA::FloatRegBits FloatRegBits;
80 typedef TheISA::MiscReg MiscReg;
83 typedef ThePipeline::DynInstPtr DynInstPtr;
84 typedef std::list<DynInstPtr>::iterator ListIt;
87 typedef TimeBuffer<InterStageStruct> StageQueue;
89 friend class Resource;
92 /** Constructs a CPU with the given parameters. */
93 InOrderCPU(Params *params);
98 /** Type of core that this is */
101 int readCpuId() { return cpu_id; }
103 void setCpuId(int val) { cpu_id = val; }
116 /** Overall CPU status. */
120 /** Define TickEvent for the CPU */
121 class TickEvent : public Event
124 /** Pointer to the CPU. */
128 /** Constructs a tick event. */
129 TickEvent(InOrderCPU *c);
131 /** Processes a tick event, calling tick() on the CPU. */
134 /** Returns the description of the tick event. */
135 const char *description();
138 /** The tick event used for scheduling CPU ticks. */
141 /** Schedule tick event, regardless of its current state. */
142 void scheduleTickEvent(int delay)
144 if (tickEvent.squashed())
145 mainEventQueue.reschedule(&tickEvent, nextCycle(curTick + ticks(delay)));
146 else if (!tickEvent.scheduled())
147 mainEventQueue.schedule(&tickEvent, nextCycle(curTick + ticks(delay)));
150 /** Unschedule tick event, regardless of its current state. */
151 void unscheduleTickEvent()
153 if (tickEvent.scheduled())
158 // List of Events That can be scheduled from
160 // NOTE(1): The Resource Pool also uses this event list
161 // to schedule events broadcast to all resources interfaces
162 // NOTE(2): CPU Events usually need to schedule a corresponding resource
179 static std::string eventNames[NumCPUEvents];
181 /** Define CPU Event */
182 class CPUEvent : public Event
188 CPUEventType cpuEventType;
194 /** Constructs a CPU event. */
195 CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
196 ThreadID _tid, unsigned _vpe);
198 /** Set Type of Event To Be Scheduled */
199 void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
203 cpuEventType = e_type;
208 /** Processes a resource event. */
209 virtual void process();
211 /** Returns the description of the resource event. */
212 const char *description();
214 /** Schedule Event */
215 void scheduleEvent(int delay);
217 /** Unschedule This Event */
218 void unscheduleEvent();
221 /** Schedule a CPU Event */
222 void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
223 unsigned vpe, unsigned delay = 0);
226 /** Interface between the CPU and CPU resources. */
227 ResourcePool *resPool;
229 /** Instruction used to signify that there is no *real* instruction in buffer slot */
230 DynInstPtr dummyBufferInst;
232 /** Used by resources to signify a denied access to a resource. */
233 ResourceRequest *dummyReq;
235 /** Identifies the resource id that identifies a fetch
238 unsigned fetchPortIdx;
240 /** Identifies the resource id that identifies a ITB */
243 /** Identifies the resource id that identifies a data
246 unsigned dataPortIdx;
248 /** Identifies the resource id that identifies a DTB */
251 /** The Pipeline Stages for the CPU */
252 PipelineStage *pipelineStage[ThePipeline::NumStages];
254 /** Program Counters */
255 TheISA::IntReg PC[ThePipeline::MaxThreads];
256 TheISA::IntReg nextPC[ThePipeline::MaxThreads];
257 TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
259 /** The Register File for the CPU */
261 FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
262 FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
264 TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
267 TheISA::ISA isa[ThePipeline::MaxThreads];
269 /** Dependency Tracker for Integer & Floating Point Regs */
270 RegDepMap archRegDepMap[ThePipeline::MaxThreads];
272 /** Global communication structure */
273 TimeBuffer<TimeStruct> timeBuffer;
275 /** Communication structure that sits in between pipeline stages */
276 StageQueue *stageQueue[ThePipeline::NumStages-1];
278 TheISA::TLB *getITBPtr();
279 TheISA::TLB *getDTBPtr();
283 /** Registers statistics. */
286 /** Ticks CPU, calling tick() on each stage, and checking the overall
287 * activity to see if the CPU should deschedule itself.
291 /** Initialize the CPU */
294 /** Reset State in the CPU */
297 /** Get a Memory Port */
298 Port* getPort(const std::string &if_name, int idx = 0);
300 /** trap() - sets up a trap event on the cpuTraps to handle given fault.
301 * trapCPU() - Traps to handle given fault
303 void trap(Fault fault, ThreadID tid, int delay = 0);
304 void trapCPU(Fault fault, ThreadID tid);
306 /** Setup CPU to insert a thread's context */
307 void insertThread(ThreadID tid);
309 /** Remove all of a thread's context from CPU */
310 void removeThread(ThreadID tid);
312 /** Add Thread to Active Threads List. */
313 void activateContext(ThreadID tid, int delay = 0);
314 void activateThread(ThreadID tid);
316 /** Remove Thread from Active Threads List */
317 void suspendContext(ThreadID tid, int delay = 0);
318 void suspendThread(ThreadID tid);
320 /** Remove Thread from Active Threads List &&
321 * Remove Thread Context from CPU.
323 void deallocateContext(ThreadID tid, int delay = 0);
324 void deallocateThread(ThreadID tid);
325 void deactivateThread(ThreadID tid);
327 PipelineStage* getPipeStage(int stage_num);
332 hack_once("return a bogus context id");
336 /** Remove Thread from Active Threads List &&
337 * Remove Thread Context from CPU.
339 void haltContext(ThreadID tid, int delay = 0);
341 void removePipelineStalls(ThreadID tid);
343 void squashThreadInPipeline(ThreadID tid);
345 /// Notify the CPU to enable a virtual processor element.
346 virtual void enableVirtProcElement(unsigned vpe);
347 void enableVPEs(unsigned vpe);
349 /// Notify the CPU to disable a virtual processor element.
350 virtual void disableVirtProcElement(ThreadID tid, unsigned vpe);
351 void disableVPEs(ThreadID tid, unsigned vpe);
353 /// Notify the CPU that multithreading is enabled.
354 virtual void enableMultiThreading(unsigned vpe);
355 void enableThreads(unsigned vpe);
357 /// Notify the CPU that multithreading is disabled.
358 virtual void disableMultiThreading(ThreadID tid, unsigned vpe);
359 void disableThreads(ThreadID tid, unsigned vpe);
361 /** Activate a Thread When CPU Resources are Available. */
362 void activateWhenReady(ThreadID tid);
364 /** Add or Remove a Thread Context in the CPU. */
365 void doContextSwitch();
367 /** Update The Order In Which We Process Threads. */
368 void updateThreadPriority();
370 /** Switches a Pipeline Stage to Active. (Unused currently) */
371 void switchToActive(int stage_idx)
372 { /*pipelineStage[stage_idx]->switchToActive();*/ }
374 /** Get the current instruction sequence number, and increment it. */
375 InstSeqNum getAndIncrementInstSeq(ThreadID tid)
376 { return globalSeqNum[tid]++; }
378 /** Get the current instruction sequence number, and increment it. */
379 InstSeqNum nextInstSeqNum(ThreadID tid)
380 { return globalSeqNum[tid]; }
382 /** Increment Instruction Sequence Number */
383 void incrInstSeqNum(ThreadID tid)
384 { globalSeqNum[tid]++; }
386 /** Set Instruction Sequence Number */
387 void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
389 globalSeqNum[tid] = seq_num;
392 /** Get & Update Next Event Number */
393 InstSeqNum getNextEventNum()
395 return cpuEventNum++;
398 /** Register file accessors */
399 uint64_t readIntReg(int reg_idx, ThreadID tid);
401 FloatReg readFloatReg(int reg_idx, ThreadID tid);
403 FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
405 void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
407 void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
409 void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid);
411 /** Reads a miscellaneous register. */
412 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
414 /** Reads a misc. register, including any side effects the read
415 * might have as defined by the architecture.
417 MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
419 /** Sets a miscellaneous register. */
420 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
423 /** Sets a misc. register, including any side effects the write
424 * might have as defined by the architecture.
426 void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
428 /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
431 uint64_t readRegOtherThread(unsigned misc_reg,
432 ThreadID tid = InvalidThreadID);
434 /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
437 void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
440 /** Reads the commit PC of a specific thread. */
441 uint64_t readPC(ThreadID tid);
443 /** Sets the commit PC of a specific thread. */
444 void setPC(Addr new_PC, ThreadID tid);
446 /** Reads the next PC of a specific thread. */
447 uint64_t readNextPC(ThreadID tid);
449 /** Sets the next PC of a specific thread. */
450 void setNextPC(uint64_t val, ThreadID tid);
452 /** Reads the next NPC of a specific thread. */
453 uint64_t readNextNPC(ThreadID tid);
455 /** Sets the next NPC of a specific thread. */
456 void setNextNPC(uint64_t val, ThreadID tid);
458 /** Function to add instruction onto the head of the list of the
459 * instructions. Used when new instructions are fetched.
461 ListIt addInst(DynInstPtr &inst);
463 /** Function to tell the CPU that an instruction has completed. */
464 void instDone(DynInstPtr inst, ThreadID tid);
466 /** Add Instructions to the CPU Remove List*/
467 void addToRemoveList(DynInstPtr &inst);
469 /** Remove an instruction from CPU */
470 void removeInst(DynInstPtr &inst);
472 /** Remove all instructions younger than the given sequence number. */
473 void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
475 /** Removes the instruction pointed to by the iterator. */
476 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
478 /** Cleans up all instructions on the instruction remove list. */
479 void cleanUpRemovedInsts();
481 /** Cleans up all instructions on the request remove list. */
482 void cleanUpRemovedReqs();
484 /** Cleans up all instructions on the CPU event remove list. */
485 void cleanUpRemovedEvents();
487 /** Debug function to print all instructions on the list. */
490 /** Forwards an instruction read to the appropriate data
491 * resource (indexes into Resource Pool thru "dataPortIdx")
494 Fault read(DynInstPtr inst, Addr addr, T &data, unsigned flags);
496 /** Forwards an instruction write. to the appropriate data
497 * resource (indexes into Resource Pool thru "dataPortIdx")
500 Fault write(DynInstPtr inst, T data, Addr addr, unsigned flags,
501 uint64_t *write_res = NULL);
503 /** Forwards an instruction prefetch to the appropriate data
504 * resource (indexes into Resource Pool thru "dataPortIdx")
506 void prefetch(DynInstPtr inst);
508 /** Forwards an instruction writeHint to the appropriate data
509 * resource (indexes into Resource Pool thru "dataPortIdx")
511 void writeHint(DynInstPtr inst);
513 /** Executes a syscall.*/
514 void syscall(int64_t callnum, ThreadID tid);
517 /** Per-Thread List of all the instructions in flight. */
518 std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
520 /** List of all the instructions that will be removed at the end of this
523 std::queue<ListIt> removeList;
525 /** List of all the resource requests that will be removed at the end of this
528 std::queue<ResourceRequest*> reqRemoveList;
530 /** List of all the cpu event requests that will be removed at the end of
533 std::queue<Event*> cpuEventRemoveList;
535 /** Records if instructions need to be removed this cycle due to
536 * being retired or squashed.
538 bool removeInstsThisCycle;
540 /** True if there is non-speculative Inst Active In Pipeline. Lets any
541 * execution unit know, NOT to execute while the instruction is active.
543 bool nonSpecInstActive[ThePipeline::MaxThreads];
545 /** Instruction Seq. Num of current non-speculative instruction. */
546 InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
548 /** Instruction Seq. Num of last instruction squashed in pipeline */
549 InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
551 /** Last Cycle that the CPU squashed instruction end. */
552 Tick lastSquashCycle[ThePipeline::MaxThreads];
554 std::list<ThreadID> fetchPriorityList;
557 /** Active Threads List */
558 std::list<ThreadID> activeThreads;
560 /** Current Threads List */
561 std::list<ThreadID> currentThreads;
563 /** Suspended Threads List */
564 std::list<ThreadID> suspendedThreads;
566 /** Thread Status Functions (Unused Currently) */
567 bool isThreadInCPU(ThreadID tid);
568 bool isThreadActive(ThreadID tid);
569 bool isThreadSuspended(ThreadID tid);
570 void addToCurrentThreads(ThreadID tid);
571 void removeFromCurrentThreads(ThreadID tid);
574 /** The activity recorder; used to tell if the CPU has any
575 * activity remaining or if it can go to idle and deschedule
578 ActivityRecorder activityRec;
581 void readFunctional(Addr addr, uint32_t &buffer);
583 /** Number of Active Threads in the CPU */
584 ThreadID numActiveThreads() { return activeThreads.size(); }
586 /** Records that there was time buffer activity this cycle. */
587 void activityThisCycle() { activityRec.activity(); }
589 /** Changes a stage's status to active within the activity recorder. */
590 void activateStage(const int idx)
591 { activityRec.activateStage(idx); }
593 /** Changes a stage's status to inactive within the activity recorder. */
594 void deactivateStage(const int idx)
595 { activityRec.deactivateStage(idx); }
597 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
600 /** Gets a free thread id. Use if thread ids change across system. */
601 ThreadID getFreeTid();
603 // LL/SC debug functionality
604 unsigned stCondFails;
605 unsigned readStCondFailures() { return stCondFails; }
606 unsigned setStCondFailures(unsigned st_fails) { return stCondFails = st_fails; }
608 /** Returns a pointer to a thread context. */
609 ThreadContext *tcBase(ThreadID tid = 0)
611 return thread[tid]->getTC();
614 /** Count the Total Instructions Committed in the CPU. */
615 virtual Counter totalInstructions() const
619 for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
620 total += thread[tid]->numInst;
625 /** The global sequence number counter. */
626 InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
628 /** The global event number counter. */
629 InstSeqNum cpuEventNum;
631 /** Counter of how many stages have completed switching out. */
634 /** Pointers to all of the threads in the CPU. */
635 std::vector<Thread *> thread;
637 /** Pointer to the icache interface. */
638 MemInterface *icacheInterface;
640 /** Pointer to the dcache interface. */
641 MemInterface *dcacheInterface;
643 /** Whether or not the CPU should defer its registration. */
644 bool deferRegistration;
646 /** Per-Stage Instruction Tracing */
649 /** Is there a context switch pending? */
652 /** Threads Scheduled to Enter CPU */
653 std::list<int> cpuWaitList;
655 /** The cycle that the CPU was last running, used for statistics. */
656 Tick lastRunningCycle;
658 /** Number of Virtual Processors the CPU can process */
659 unsigned numVirtProcs;
661 /** Update Thread , used for statistic purposes*/
662 inline void tickThreadStats();
664 /** Per-Thread Tick */
665 Stats::Vector threadCycles;
668 Stats::Scalar smtCycles;
670 /** Stat for total number of times the CPU is descheduled. */
671 Stats::Scalar timesIdled;
673 /** Stat for total number of cycles the CPU spends descheduled. */
674 Stats::Scalar idleCycles;
676 /** Stat for the number of committed instructions per thread. */
677 Stats::Vector committedInsts;
679 /** Stat for the number of committed instructions per thread. */
680 Stats::Vector smtCommittedInsts;
682 /** Stat for the total number of committed instructions. */
683 Stats::Scalar totalCommittedInsts;
685 /** Stat for the CPI per thread. */
688 /** Stat for the SMT-CPI per thread. */
689 Stats::Formula smtCpi;
691 /** Stat for the total CPI. */
692 Stats::Formula totalCpi;
694 /** Stat for the IPC per thread. */
697 /** Stat for the total IPC. */
698 Stats::Formula smtIpc;
700 /** Stat for the total IPC. */
701 Stats::Formula totalIpc;
704 #endif // __CPU_O3_CPU_HH__