src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/types.hh"
  43 #include "arch/registers.hh"
  44 #include "base/statistics.hh"
  45 #include "base/timebuf.hh"
  46 #include "base/types.hh"
  47 #include "config/full_system.hh"
  48 #include "cpu/activity.hh"
  49 #include "cpu/base.hh"
  50 #include "cpu/simple_thread.hh"
  51 #include "cpu/inorder/inorder_dyn_inst.hh"
  52 #include "cpu/inorder/pipeline_traits.hh"
  53 #include "cpu/inorder/pipeline_stage.hh"
  54 #include "cpu/inorder/thread_state.hh"
  55 #include "cpu/inorder/reg_dep_map.hh"
  56 #include "cpu/o3/dep_graph.hh"
  57 #include "cpu/o3/rename_map.hh"
  58 #include "mem/packet.hh"
  59 #include "mem/port.hh"
  60 #include "mem/request.hh"
  61 #include "sim/eventq.hh"
  62 #include "sim/process.hh"
  63
  64 class ThreadContext;
  65 class MemInterface;
  66 class MemObject;
  67 class Process;
  68 class ResourcePool;
  69
  70 class InOrderCPU : public BaseCPU
  71 {
  72
  73   protected:
  74     typedef ThePipeline::Params Params;
  75     typedef InOrderThreadState Thread;
  76
  77    //ISA TypeDefs
  78     typedef TheISA::IntReg IntReg;
  79     typedef TheISA::FloatReg FloatReg;
  80     typedef TheISA::FloatRegBits FloatRegBits;
  81     typedef TheISA::MiscReg MiscReg;
  82
  83     //DynInstPtr TypeDefs
  84     typedef ThePipeline::DynInstPtr DynInstPtr;
  85     typedef std::list<DynInstPtr>::iterator ListIt;
  86
  87     //TimeBuffer TypeDefs
  88     typedef TimeBuffer<InterStageStruct> StageQueue;
  89
  90     friend class Resource;
  91
  92   public:
  93     /** Constructs a CPU with the given parameters. */
  94     InOrderCPU(Params *params);
  95
  96     /** CPU ID */
  97     int cpu_id;
  98
  99     /** Type of core that this is */
 100     std::string coreType;
 101
 102     int readCpuId() { return cpu_id; }
 103
 104     void setCpuId(int val) { cpu_id = val; }
 105
 106     Params *cpu_params;
 107
 108   public:
 109     enum Status {
 110         Running,
 111         Idle,
 112         Halted,
 113         Blocked,
 114         SwitchedOut
 115     };
 116
 117     /** Overall CPU status. */
 118     Status _status;
 119
 120   private:
 121     /** Define TickEvent for the CPU */
 122     class TickEvent : public Event
 123     {
 124       private:
 125         /** Pointer to the CPU. */
 126         InOrderCPU *cpu;
 127
 128       public:
 129         /** Constructs a tick event. */
 130         TickEvent(InOrderCPU *c);
 131
 132         /** Processes a tick event, calling tick() on the CPU. */
 133         void process();
 134
 135         /** Returns the description of the tick event. */
 136         const char *description();
 137     };
 138
 139     /** The tick event used for scheduling CPU ticks. */
 140     TickEvent tickEvent;
 141
 142     /** Schedule tick event, regardless of its current state. */
 143     void scheduleTickEvent(int delay)
 144     {
 145         if (tickEvent.squashed())
 146           mainEventQueue.reschedule(&tickEvent, nextCycle(curTick + ticks(delay)));
 147         else if (!tickEvent.scheduled())
 148           mainEventQueue.schedule(&tickEvent, nextCycle(curTick + ticks(delay)));
 149     }
 150
 151     /** Unschedule tick event, regardless of its current state. */
 152     void unscheduleTickEvent()
 153     {
 154         if (tickEvent.scheduled())
 155             tickEvent.squash();
 156     }
 157
 158   public:
 159     // List of Events That can be scheduled from
 160     // within the CPU.
 161     // NOTE(1): The Resource Pool also uses this event list
 162     // to schedule events broadcast to all resources interfaces
 163     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 164     // pool event.
 165     enum CPUEventType {
 166         ActivateThread,
 167         DeallocateThread,
 168         SuspendThread,
 169         DisableThreads,
 170         EnableThreads,
 171         DisableVPEs,
 172         EnableVPEs,
 173         Trap,
 174         InstGraduated,
 175         SquashAll,
 176         UpdatePCs,
 177         NumCPUEvents
 178     };
 179
 180     static std::string eventNames[NumCPUEvents];
 181
 182     /** Define CPU Event */
 183     class CPUEvent : public Event
 184     {
 185       protected:
 186         InOrderCPU *cpu;
 187
 188       public:
 189         CPUEventType cpuEventType;
 190         ThreadID tid;
 191         unsigned vpe;
 192         Fault fault;
 193
 194       public:
 195         /** Constructs a CPU event. */
 196         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 197                  ThreadID _tid, unsigned _vpe);
 198
 199         /** Set Type of Event To Be Scheduled */
 200         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 201                       unsigned _vpe)
 202         {
 203             fault = _fault;
 204             cpuEventType = e_type;
 205             tid = _tid;
 206             vpe = _vpe;
 207         }
 208
 209         /** Processes a resource event. */
 210         virtual void process();
 211
 212         /** Returns the description of the resource event. */
 213         const char *description();
 214
 215         /** Schedule Event */
 216         void scheduleEvent(int delay);
 217
 218         /** Unschedule This Event */
 219         void unscheduleEvent();
 220     };
 221
 222     /** Schedule a CPU Event */
 223     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 224                           unsigned vpe, unsigned delay = 0);
 225
 226   public:
 227     /** Interface between the CPU and CPU resources. */
 228     ResourcePool *resPool;
 229
 230     /** Instruction used to signify that there is no *real* instruction in buffer slot */
 231     DynInstPtr dummyBufferInst;
 232
 233     /** Used by resources to signify a denied access to a resource. */
 234     ResourceRequest *dummyReq;
 235
 236     /** Identifies the resource id that identifies a fetch
 237      * access unit.
 238      */
 239     unsigned fetchPortIdx;
 240
 241     /** Identifies the resource id that identifies a ITB       */
 242     unsigned itbIdx;
 243
 244     /** Identifies the resource id that identifies a data
 245      * access unit.
 246      */
 247     unsigned dataPortIdx;
 248
 249     /** Identifies the resource id that identifies a DTB       */
 250     unsigned dtbIdx;
 251
 252     /** The Pipeline Stages for the CPU */
 253     PipelineStage *pipelineStage[ThePipeline::NumStages];
 254
 255     /** Program Counters */
 256     TheISA::IntReg PC[ThePipeline::MaxThreads];
 257     TheISA::IntReg nextPC[ThePipeline::MaxThreads];
 258     TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
 259
 260     /** The Register File for the CPU */
 261     union {
 262         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 263         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 264     } floatRegs;
 265     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 266
 267     /** ISA state */
 268     TheISA::ISA isa[ThePipeline::MaxThreads];
 269
 270     /** Dependency Tracker for Integer & Floating Point Regs */
 271     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 272
 273     /** Global communication structure */
 274     TimeBuffer<TimeStruct> timeBuffer;
 275
 276     /** Communication structure that sits in between pipeline stages */
 277     StageQueue *stageQueue[ThePipeline::NumStages-1];
 278
 279     TheISA::TLB *getITBPtr();
 280     TheISA::TLB *getDTBPtr();
 281
 282   public:
 283
 284     /** Registers statistics. */
 285     void regStats();
 286
 287     /** Ticks CPU, calling tick() on each stage, and checking the overall
 288      *  activity to see if the CPU should deschedule itself.
 289      */
 290     void tick();
 291
 292     /** Initialize the CPU */
 293     void init();
 294
 295     /** Reset State in the CPU */
 296     void reset();
 297
 298     /** Get a Memory Port */
 299     Port* getPort(const std::string &if_name, int idx = 0);
 300
 301 #if FULL_SYSTEM
 302     /** HW return from error interrupt. */
 303     Fault hwrei(ThreadID tid);
 304
 305     bool simPalCheck(int palFunc, ThreadID tid);
 306
 307     /** Returns the Fault for any valid interrupt. */
 308     Fault getInterrupts();
 309
 310     /** Processes any an interrupt fault. */
 311     void processInterrupts(Fault interrupt);
 312
 313     /** Halts the CPU. */
 314     void halt() { panic("Halt not implemented!\n"); }
 315
 316     /** Update the Virt and Phys ports of all ThreadContexts to
 317      * reflect change in memory connections. */
 318     void updateMemPorts();
 319
 320     /** Check if this address is a valid instruction address. */
 321     bool validInstAddr(Addr addr) { return true; }
 322
 323     /** Check if this address is a valid data address. */
 324     bool validDataAddr(Addr addr) { return true; }
 325 #endif
 326
 327     /** trap() - sets up a trap event on the cpuTraps to handle given fault.
 328      *  trapCPU() - Traps to handle given fault
 329      */
 330     void trap(Fault fault, ThreadID tid, int delay = 0);
 331     void trapCPU(Fault fault, ThreadID tid);
 332
 333     /** Setup CPU to insert a thread's context */
 334     void insertThread(ThreadID tid);
 335
 336     /** Remove all of a thread's context from CPU */
 337     void removeThread(ThreadID tid);
 338
 339     /** Add Thread to Active Threads List. */
 340     void activateContext(ThreadID tid, int delay = 0);
 341     void activateThread(ThreadID tid);
 342
 343     /** Remove Thread from Active Threads List */
 344     void suspendContext(ThreadID tid, int delay = 0);
 345     void suspendThread(ThreadID tid);
 346
 347     /** Remove Thread from Active Threads List &&
 348      *  Remove Thread Context from CPU.
 349      */
 350     void deallocateContext(ThreadID tid, int delay = 0);
 351     void deallocateThread(ThreadID tid);
 352     void deactivateThread(ThreadID tid);
 353
 354     PipelineStage* getPipeStage(int stage_num);
 355
 356     int
 357     contextId()
 358     {
 359         hack_once("return a bogus context id");
 360         return 0;
 361     }
 362
 363     /** Remove Thread from Active Threads List &&
 364      *  Remove Thread Context from CPU.
 365      */
 366     void haltContext(ThreadID tid, int delay = 0);
 367
 368     void removePipelineStalls(ThreadID tid);
 369
 370     void squashThreadInPipeline(ThreadID tid);
 371
 372     /// Notify the CPU to enable a virtual processor element.
 373     virtual void enableVirtProcElement(unsigned vpe);
 374     void enableVPEs(unsigned vpe);
 375
 376     /// Notify the CPU to disable a virtual processor element.
 377     virtual void disableVirtProcElement(ThreadID tid, unsigned vpe);
 378     void disableVPEs(ThreadID tid, unsigned vpe);
 379
 380     /// Notify the CPU that multithreading is enabled.
 381     virtual void enableMultiThreading(unsigned vpe);
 382     void enableThreads(unsigned vpe);
 383
 384     /// Notify the CPU that multithreading is disabled.
 385     virtual void disableMultiThreading(ThreadID tid, unsigned vpe);
 386     void disableThreads(ThreadID tid, unsigned vpe);
 387
 388     /** Activate a Thread When CPU Resources are Available. */
 389     void activateWhenReady(ThreadID tid);
 390
 391     /** Add or Remove a Thread Context in the CPU. */
 392     void doContextSwitch();
 393
 394     /** Update The Order In Which We Process Threads. */
 395     void updateThreadPriority();
 396
 397     /** Switches a Pipeline Stage to Active. (Unused currently) */
 398     void switchToActive(int stage_idx)
 399     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 400
 401     /** Get the current instruction sequence number, and increment it. */
 402     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 403     { return globalSeqNum[tid]++; }
 404
 405     /** Get the current instruction sequence number, and increment it. */
 406     InstSeqNum nextInstSeqNum(ThreadID tid)
 407     { return globalSeqNum[tid]; }
 408
 409     /** Increment Instruction Sequence Number */
 410     void incrInstSeqNum(ThreadID tid)
 411     { globalSeqNum[tid]++; }
 412
 413     /** Set Instruction Sequence Number */
 414     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 415     {
 416         globalSeqNum[tid] = seq_num;
 417     }
 418
 419     /** Get & Update Next Event Number */
 420     InstSeqNum getNextEventNum()
 421     {
 422         return cpuEventNum++;
 423     }
 424
 425     /** Register file accessors  */
 426     uint64_t readIntReg(int reg_idx, ThreadID tid);
 427
 428     FloatReg readFloatReg(int reg_idx, ThreadID tid);
 429
 430     FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
 431
 432     void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
 433
 434     void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
 435
 436     void setFloatRegBits(int reg_idx, FloatRegBits val,  ThreadID tid);
 437
 438     /** Reads a miscellaneous register. */
 439     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 440
 441     /** Reads a misc. register, including any side effects the read
 442      * might have as defined by the architecture.
 443      */
 444     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 445
 446     /** Sets a miscellaneous register. */
 447     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 448                             ThreadID tid = 0);
 449
 450     /** Sets a misc. register, including any side effects the write
 451      * might have as defined by the architecture.
 452      */
 453     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 454
 455     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 456      *  target thread
 457      */
 458     uint64_t readRegOtherThread(unsigned misc_reg,
 459                                 ThreadID tid = InvalidThreadID);
 460
 461     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 462      * target thread
 463      */
 464     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 465                            ThreadID tid);
 466
 467     /** Reads the commit PC of a specific thread. */
 468     uint64_t readPC(ThreadID tid);
 469
 470     /** Sets the commit PC of a specific thread. */
 471     void setPC(Addr new_PC, ThreadID tid);
 472
 473     /** Reads the next PC of a specific thread. */
 474     uint64_t readNextPC(ThreadID tid);
 475
 476     /** Sets the next PC of a specific thread. */
 477     void setNextPC(uint64_t val, ThreadID tid);
 478
 479     /** Reads the next NPC of a specific thread. */
 480     uint64_t readNextNPC(ThreadID tid);
 481
 482     /** Sets the next NPC of a specific thread. */
 483     void setNextNPC(uint64_t val, ThreadID tid);
 484
 485     /** Function to add instruction onto the head of the list of the
 486      *  instructions.  Used when new instructions are fetched.
 487      */
 488     ListIt addInst(DynInstPtr &inst);
 489
 490     /** Function to tell the CPU that an instruction has completed. */
 491     void instDone(DynInstPtr inst, ThreadID tid);
 492
 493     /** Add Instructions to the CPU Remove List*/
 494     void addToRemoveList(DynInstPtr &inst);
 495
 496     /** Remove an instruction from CPU */
 497     void removeInst(DynInstPtr &inst);
 498
 499     /** Remove all instructions younger than the given sequence number. */
 500     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 501
 502     /** Removes the instruction pointed to by the iterator. */
 503     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 504
 505     /** Cleans up all instructions on the instruction remove list. */
 506     void cleanUpRemovedInsts();
 507
 508     /** Cleans up all instructions on the request remove list. */
 509     void cleanUpRemovedReqs();
 510
 511     /** Cleans up all instructions on the CPU event remove list. */
 512     void cleanUpRemovedEvents();
 513
 514     /** Debug function to print all instructions on the list. */
 515     void dumpInsts();
 516
 517     /** Forwards an instruction read to the appropriate data
 518      *  resource (indexes into Resource Pool thru "dataPortIdx")
 519      */
 520     template <class T>
 521     Fault read(DynInstPtr inst, Addr addr, T &data, unsigned flags);
 522
 523     /** Forwards an instruction write. to the appropriate data
 524      *  resource (indexes into Resource Pool thru "dataPortIdx")
 525      */
 526     template <class T>
 527     Fault write(DynInstPtr inst, T data, Addr addr, unsigned flags,
 528                 uint64_t *write_res = NULL);
 529
 530     /** Forwards an instruction prefetch to the appropriate data
 531      *  resource (indexes into Resource Pool thru "dataPortIdx")
 532      */
 533     void prefetch(DynInstPtr inst);
 534
 535     /** Forwards an instruction writeHint to the appropriate data
 536      *  resource (indexes into Resource Pool thru "dataPortIdx")
 537      */
 538     void writeHint(DynInstPtr inst);
 539
 540     /** Executes a syscall.*/
 541     void syscall(int64_t callnum, ThreadID tid);
 542
 543   public:
 544     /** Per-Thread List of all the instructions in flight. */
 545     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 546
 547     /** List of all the instructions that will be removed at the end of this
 548      *  cycle.
 549      */
 550     std::queue<ListIt> removeList;
 551
 552     /** List of all the resource requests that will be removed at the end of this
 553      *  cycle.
 554      */
 555     std::queue<ResourceRequest*> reqRemoveList;
 556
 557     /** List of all the cpu event requests that will be removed at the end of
 558      *  the current cycle.
 559      */
 560     std::queue<Event*> cpuEventRemoveList;
 561
 562     /** Records if instructions need to be removed this cycle due to
 563      *  being retired or squashed.
 564      */
 565     bool removeInstsThisCycle;
 566
 567     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 568      * execution unit know, NOT to execute while the instruction is active.
 569      */
 570     bool nonSpecInstActive[ThePipeline::MaxThreads];
 571
 572     /** Instruction Seq. Num of current non-speculative instruction. */
 573     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 574
 575     /** Instruction Seq. Num of last instruction squashed in pipeline */
 576     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 577
 578     /** Last Cycle that the CPU squashed instruction end. */
 579     Tick lastSquashCycle[ThePipeline::MaxThreads];
 580
 581     std::list<ThreadID> fetchPriorityList;
 582
 583   protected:
 584     /** Active Threads List */
 585     std::list<ThreadID> activeThreads;
 586
 587     /** Current Threads List */
 588     std::list<ThreadID> currentThreads;
 589
 590     /** Suspended Threads List */
 591     std::list<ThreadID> suspendedThreads;
 592
 593     /** Thread Status Functions (Unused Currently) */
 594     bool isThreadInCPU(ThreadID tid);
 595     bool isThreadActive(ThreadID tid);
 596     bool isThreadSuspended(ThreadID tid);
 597     void addToCurrentThreads(ThreadID tid);
 598     void removeFromCurrentThreads(ThreadID tid);
 599
 600   private:
 601     /** The activity recorder; used to tell if the CPU has any
 602      * activity remaining or if it can go to idle and deschedule
 603      * itself.
 604      */
 605     ActivityRecorder activityRec;
 606
 607   public:
 608     /** Number of Active Threads in the CPU */
 609     ThreadID numActiveThreads() { return activeThreads.size(); }
 610
 611     /** Records that there was time buffer activity this cycle. */
 612     void activityThisCycle() { activityRec.activity(); }
 613
 614     /** Changes a stage's status to active within the activity recorder. */
 615     void activateStage(const int idx)
 616     { activityRec.activateStage(idx); }
 617
 618     /** Changes a stage's status to inactive within the activity recorder. */
 619     void deactivateStage(const int idx)
 620     { activityRec.deactivateStage(idx); }
 621
 622     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 623     void wakeCPU();
 624
 625 #if FULL_SYSTEM
 626     virtual void wakeup();
 627 #endif
 628
 629     /** Gets a free thread id. Use if thread ids change across system. */
 630     ThreadID getFreeTid();
 631
 632     // LL/SC debug functionality
 633     unsigned stCondFails;
 634     unsigned readStCondFailures() { return stCondFails; }
 635     unsigned setStCondFailures(unsigned st_fails) { return stCondFails = st_fails; }
 636
 637     /** Returns a pointer to a thread context. */
 638     ThreadContext *tcBase(ThreadID tid = 0)
 639     {
 640         return thread[tid]->getTC();
 641     }
 642
 643     /** Count the Total Instructions Committed in the CPU. */
 644     virtual Counter totalInstructions() const
 645     {
 646         Counter total(0);
 647
 648         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 649             total += thread[tid]->numInst;
 650
 651         return total;
 652     }
 653
 654 #if FULL_SYSTEM
 655     /** Pointer to the system. */
 656     System *system;
 657
 658     /** Pointer to physical memory. */
 659     PhysicalMemory *physmem;
 660 #endif
 661
 662     /** The global sequence number counter. */
 663     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 664
 665     /** The global event number counter. */
 666     InstSeqNum cpuEventNum;
 667
 668     /** Counter of how many stages have completed switching out. */
 669     int switchCount;
 670
 671     /** Pointers to all of the threads in the CPU. */
 672     std::vector<Thread *> thread;
 673
 674     /** Pointer to the icache interface. */
 675     MemInterface *icacheInterface;
 676
 677     /** Pointer to the dcache interface. */
 678     MemInterface *dcacheInterface;
 679
 680     /** Whether or not the CPU should defer its registration. */
 681     bool deferRegistration;
 682
 683     /** Per-Stage Instruction Tracing */
 684     bool stageTracing;
 685
 686     /** Is there a context switch pending? */
 687     bool contextSwitch;
 688
 689     /** Threads Scheduled to Enter CPU */
 690     std::list<int> cpuWaitList;
 691
 692     /** The cycle that the CPU was last running, used for statistics. */
 693     Tick lastRunningCycle;
 694
 695     /** Number of Virtual Processors the CPU can process */
 696     unsigned numVirtProcs;
 697
 698     /** Update Thread , used for statistic purposes*/
 699     inline void tickThreadStats();
 700
 701     /** Per-Thread Tick */
 702     Stats::Vector threadCycles;
 703
 704     /** Tick for SMT */
 705     Stats::Scalar smtCycles;
 706
 707     /** Stat for total number of times the CPU is descheduled. */
 708     Stats::Scalar timesIdled;
 709
 710     /** Stat for total number of cycles the CPU spends descheduled. */
 711     Stats::Scalar idleCycles;
 712
 713     /** Stat for the number of committed instructions per thread. */
 714     Stats::Vector committedInsts;
 715
 716     /** Stat for the number of committed instructions per thread. */
 717     Stats::Vector smtCommittedInsts;
 718
 719     /** Stat for the total number of committed instructions. */
 720     Stats::Scalar totalCommittedInsts;
 721
 722     /** Stat for the CPI per thread. */
 723     Stats::Formula cpi;
 724
 725     /** Stat for the SMT-CPI per thread. */
 726     Stats::Formula smtCpi;
 727
 728     /** Stat for the total CPI. */
 729     Stats::Formula totalCpi;
 730
 731     /** Stat for the IPC per thread. */
 732     Stats::Formula ipc;
 733
 734     /** Stat for the total IPC. */
 735     Stats::Formula smtIpc;
 736
 737     /** Stat for the total IPC. */
 738     Stats::Formula totalIpc;
 739 };
 740
 741 #endif // __CPU_O3_CPU_HH__