2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_CPU_HH__
33 #define __CPU_INORDER_CPU_HH__
41 #include "arch/isa_traits.hh"
42 #include "arch/registers.hh"
43 #include "arch/types.hh"
44 #include "base/statistics.hh"
45 #include "base/types.hh"
46 #include "config/full_system.hh"
47 #include "config/the_isa.hh"
48 #include "cpu/inorder/inorder_dyn_inst.hh"
49 #include "cpu/inorder/pipeline_stage.hh"
50 #include "cpu/inorder/pipeline_traits.hh"
51 #include "cpu/inorder/reg_dep_map.hh"
52 #include "cpu/inorder/thread_state.hh"
53 #include "cpu/o3/dep_graph.hh"
54 #include "cpu/o3/rename_map.hh"
55 #include "cpu/activity.hh"
56 #include "cpu/base.hh"
57 #include "cpu/simple_thread.hh"
58 #include "cpu/timebuf.hh"
59 #include "mem/packet.hh"
60 #include "mem/port.hh"
61 #include "mem/request.hh"
62 #include "sim/eventq.hh"
63 #include "sim/process.hh"
71 class InOrderCPU : public BaseCPU
75 typedef ThePipeline::Params Params;
76 typedef InOrderThreadState Thread;
79 typedef TheISA::IntReg IntReg;
80 typedef TheISA::FloatReg FloatReg;
81 typedef TheISA::FloatRegBits FloatRegBits;
82 typedef TheISA::MiscReg MiscReg;
83 typedef TheISA::RegIndex RegIndex;
86 typedef ThePipeline::DynInstPtr DynInstPtr;
87 typedef std::list<DynInstPtr>::iterator ListIt;
90 typedef TimeBuffer<InterStageStruct> StageQueue;
92 friend class Resource;
95 /** Constructs a CPU with the given parameters. */
96 InOrderCPU(Params *params);
104 ThreadID asid[ThePipeline::MaxThreads];
106 /** Type of core that this is */
107 std::string coreType;
109 // Only need for SE MODE
116 ThreadModel threadModel;
118 int readCpuId() { return cpu_id; }
120 void setCpuId(int val) { cpu_id = val; }
133 /** Overall CPU status. */
136 /** Define TickEvent for the CPU */
137 class TickEvent : public Event
140 /** Pointer to the CPU. */
144 /** Constructs a tick event. */
145 TickEvent(InOrderCPU *c);
147 /** Processes a tick event, calling tick() on the CPU. */
150 /** Returns the description of the tick event. */
151 const char *description();
154 /** The tick event used for scheduling CPU ticks. */
157 /** Schedule tick event, regardless of its current state. */
158 void scheduleTickEvent(int delay)
160 assert(!tickEvent.scheduled() || tickEvent.squashed());
161 reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
164 /** Unschedule tick event, regardless of its current state. */
165 void unscheduleTickEvent()
167 if (tickEvent.scheduled())
172 // List of Events That can be scheduled from
174 // NOTE(1): The Resource Pool also uses this event list
175 // to schedule events broadcast to all resources interfaces
176 // NOTE(2): CPU Events usually need to schedule a corresponding resource
180 ActivateNextReadyThread,
191 static std::string eventNames[NumCPUEvents];
193 /** Define CPU Event */
194 class CPUEvent : public Event
200 CPUEventType cpuEventType;
207 /** Constructs a CPU event. */
208 CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
209 ThreadID _tid, DynInstPtr inst, unsigned event_pri_offset);
211 /** Set Type of Event To Be Scheduled */
212 void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
216 cpuEventType = e_type;
222 /** Processes a CPU event. */
225 /** Returns the description of the CPU event. */
226 const char *description();
228 /** Schedule Event */
229 void scheduleEvent(int delay);
231 /** Unschedule This Event */
232 void unscheduleEvent();
235 /** Schedule a CPU Event */
236 void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
237 DynInstPtr inst, unsigned delay = 0,
238 unsigned event_pri_offset = 0);
241 /** Interface between the CPU and CPU resources. */
242 ResourcePool *resPool;
244 /** Instruction used to signify that there is no *real* instruction in
246 DynInstPtr dummyInst[ThePipeline::MaxThreads];
247 DynInstPtr dummyBufferInst;
248 DynInstPtr dummyReqInst;
250 /** Used by resources to signify a denied access to a resource. */
251 ResourceRequest *dummyReq[ThePipeline::MaxThreads];
253 /** Identifies the resource id that identifies a fetch
256 unsigned fetchPortIdx;
258 /** Identifies the resource id that identifies a ITB */
261 /** Identifies the resource id that identifies a data
264 unsigned dataPortIdx;
266 /** Identifies the resource id that identifies a DTB */
269 /** The Pipeline Stages for the CPU */
270 PipelineStage *pipelineStage[ThePipeline::NumStages];
272 /** Width (processing bandwidth) of each stage */
275 /** Program Counters */
276 TheISA::PCState pc[ThePipeline::MaxThreads];
278 /** The Register File for the CPU */
280 FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
281 FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
283 TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
286 TheISA::ISA isa[ThePipeline::MaxThreads];
288 /** Dependency Tracker for Integer & Floating Point Regs */
289 RegDepMap archRegDepMap[ThePipeline::MaxThreads];
291 /** Register Types Used in Dependency Tracking */
292 enum RegType { IntType, FloatType, MiscType, NumRegTypes};
294 /** Global communication structure */
295 TimeBuffer<TimeStruct> timeBuffer;
297 /** Communication structure that sits in between pipeline stages */
298 StageQueue *stageQueue[ThePipeline::NumStages-1];
300 TheISA::TLB *getITBPtr();
301 TheISA::TLB *getDTBPtr();
303 /** Accessor Type for the SkedCache */
304 typedef uint32_t SkedID;
306 /** Cache of Instruction Schedule using the instruction's name as a key */
307 static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
309 typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
311 /** Initialized to last iterator in map, signifying a invalid entry
314 SkedCacheIt endOfSkedIt;
316 ThePipeline::RSkedPtr frontEndSked;
318 /** Add a new instruction schedule to the schedule cache */
319 void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
321 SkedID sked_id = genSkedID(inst);
322 assert(skedCache.find(sked_id) == skedCache.end());
323 skedCache[sked_id] = inst_sked;
327 /** Find a instruction schedule */
328 ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
330 SkedID sked_id = genSkedID(inst);
331 SkedCacheIt lookup_it = skedCache.find(sked_id);
333 if (lookup_it != endOfSkedIt) {
334 return (*lookup_it).second;
340 static const uint8_t INST_OPCLASS = 26;
341 static const uint8_t INST_LOAD = 25;
342 static const uint8_t INST_STORE = 24;
343 static const uint8_t INST_CONTROL = 23;
344 static const uint8_t INST_NONSPEC = 22;
345 static const uint8_t INST_DEST_REGS = 18;
346 static const uint8_t INST_SRC_REGS = 14;
348 inline SkedID genSkedID(DynInstPtr inst)
351 id = (inst->opClass() << INST_OPCLASS) |
352 (inst->isLoad() << INST_LOAD) |
353 (inst->isStore() << INST_STORE) |
354 (inst->isControl() << INST_CONTROL) |
355 (inst->isNonSpeculative() << INST_NONSPEC) |
356 (inst->numDestRegs() << INST_DEST_REGS) |
357 (inst->numSrcRegs() << INST_SRC_REGS);
361 ThePipeline::RSkedPtr createFrontEndSked();
362 ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
364 class StageScheduler {
366 ThePipeline::RSkedPtr rsked;
368 int nextTaskPriority;
371 StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
372 : rsked(_rsked), stageNum(stage_num),
376 void needs(int unit, int request) {
377 rsked->push(new ScheduleEntry(
378 stageNum, nextTaskPriority++, unit, request
382 void needs(int unit, int request, int param) {
383 rsked->push(new ScheduleEntry(
384 stageNum, nextTaskPriority++, unit, request, param
391 /** Registers statistics. */
394 /** Ticks CPU, calling tick() on each stage, and checking the overall
395 * activity to see if the CPU should deschedule itself.
399 /** Initialize the CPU */
402 /** Get a Memory Port */
403 Port* getPort(const std::string &if_name, int idx = 0);
406 /** HW return from error interrupt. */
407 Fault hwrei(ThreadID tid);
409 bool simPalCheck(int palFunc, ThreadID tid);
411 /** Returns the Fault for any valid interrupt. */
412 Fault getInterrupts();
414 /** Processes any an interrupt fault. */
415 void processInterrupts(Fault interrupt);
417 /** Halts the CPU. */
418 void halt() { panic("Halt not implemented!\n"); }
420 /** Update the Virt and Phys ports of all ThreadContexts to
421 * reflect change in memory connections. */
422 void updateMemPorts();
424 /** Check if this address is a valid instruction address. */
425 bool validInstAddr(Addr addr) { return true; }
427 /** Check if this address is a valid data address. */
428 bool validDataAddr(Addr addr) { return true; }
431 /** trap() - sets up a trap event on the cpuTraps to handle given fault.
432 * trapCPU() - Traps to handle given fault
434 void trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
435 void trapCPU(Fault fault, ThreadID tid, DynInstPtr inst);
437 /** Add Thread to Active Threads List. */
438 void activateContext(ThreadID tid, int delay = 0);
439 void activateThread(ThreadID tid);
440 void activateThreadInPipeline(ThreadID tid);
442 /** Add Thread to Active Threads List. */
443 void activateNextReadyContext(int delay = 0);
444 void activateNextReadyThread();
446 /** Remove from Active Thread List */
447 void deactivateContext(ThreadID tid, int delay = 0);
448 void deactivateThread(ThreadID tid);
450 /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
451 void suspendContext(ThreadID tid, int delay = 0);
452 void suspendThread(ThreadID tid);
454 /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
457 void haltContext(ThreadID tid, int delay = 0);
458 void haltThread(ThreadID tid);
460 /** squashFromMemStall() - sets up a squash event
461 * squashDueToMemStall() - squashes pipeline
462 * @note: maybe squashContext/squashThread would be better?
464 void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
465 void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
467 void removePipelineStalls(ThreadID tid);
468 void squashThreadInPipeline(ThreadID tid);
469 void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
471 PipelineStage* getPipeStage(int stage_num);
476 hack_once("return a bogus context id");
480 /** Update The Order In Which We Process Threads. */
481 void updateThreadPriority();
483 /** Switches a Pipeline Stage to Active. (Unused currently) */
484 void switchToActive(int stage_idx)
485 { /*pipelineStage[stage_idx]->switchToActive();*/ }
487 /** Get the current instruction sequence number, and increment it. */
488 InstSeqNum getAndIncrementInstSeq(ThreadID tid)
489 { return globalSeqNum[tid]++; }
491 /** Get the current instruction sequence number, and increment it. */
492 InstSeqNum nextInstSeqNum(ThreadID tid)
493 { return globalSeqNum[tid]; }
495 /** Increment Instruction Sequence Number */
496 void incrInstSeqNum(ThreadID tid)
497 { globalSeqNum[tid]++; }
499 /** Set Instruction Sequence Number */
500 void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
502 globalSeqNum[tid] = seq_num;
505 /** Get & Update Next Event Number */
506 InstSeqNum getNextEventNum()
509 return cpuEventNum++;
515 /** Register file accessors */
516 uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
518 FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
520 FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
522 void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
524 void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
526 void setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid);
528 RegIndex flattenRegIdx(RegIndex reg_idx, RegType ®_type, ThreadID tid);
530 /** Reads a miscellaneous register. */
531 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
533 /** Reads a misc. register, including any side effects the read
534 * might have as defined by the architecture.
536 MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
538 /** Sets a miscellaneous register. */
539 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
542 /** Sets a misc. register, including any side effects the write
543 * might have as defined by the architecture.
545 void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
547 /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
550 uint64_t readRegOtherThread(unsigned misc_reg,
551 ThreadID tid = InvalidThreadID);
553 /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
556 void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
559 /** Reads the commit PC of a specific thread. */
561 pcState(ThreadID tid)
566 /** Sets the commit PC of a specific thread. */
568 pcState(const TheISA::PCState &newPC, ThreadID tid)
573 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
574 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
575 MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
577 /** Function to add instruction onto the head of the list of the
578 * instructions. Used when new instructions are fetched.
580 ListIt addInst(DynInstPtr inst);
582 /** Function to tell the CPU that an instruction has completed. */
583 void instDone(DynInstPtr inst, ThreadID tid);
585 /** Add Instructions to the CPU Remove List*/
586 void addToRemoveList(DynInstPtr inst);
588 /** Remove an instruction from CPU */
589 void removeInst(DynInstPtr inst);
591 /** Remove all instructions younger than the given sequence number. */
592 void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
594 /** Removes the instruction pointed to by the iterator. */
595 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
597 /** Cleans up all instructions on the instruction remove list. */
598 void cleanUpRemovedInsts();
600 /** Cleans up all events on the CPU event remove list. */
601 void cleanUpRemovedEvents();
603 /** Debug function to print all instructions on the list. */
606 /** Forwards an instruction read to the appropriate data
607 * resource (indexes into Resource Pool thru "dataPortIdx")
609 Fault read(DynInstPtr inst, Addr addr,
610 uint8_t *data, unsigned size, unsigned flags);
612 /** Forwards an instruction write. to the appropriate data
613 * resource (indexes into Resource Pool thru "dataPortIdx")
615 Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
616 Addr addr, unsigned flags, uint64_t *write_res = NULL);
618 /** Executes a syscall.*/
619 void syscall(int64_t callnum, ThreadID tid);
622 /** Per-Thread List of all the instructions in flight. */
623 std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
625 /** List of all the instructions that will be removed at the end of this
628 std::queue<ListIt> removeList;
630 /** List of all the cpu event requests that will be removed at the end of
633 std::queue<Event*> cpuEventRemoveList;
635 /** Records if instructions need to be removed this cycle due to
636 * being retired or squashed.
638 bool removeInstsThisCycle;
640 /** True if there is non-speculative Inst Active In Pipeline. Lets any
641 * execution unit know, NOT to execute while the instruction is active.
643 bool nonSpecInstActive[ThePipeline::MaxThreads];
645 /** Instruction Seq. Num of current non-speculative instruction. */
646 InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
648 /** Instruction Seq. Num of last instruction squashed in pipeline */
649 InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
651 /** Last Cycle that the CPU squashed instruction end. */
652 Tick lastSquashCycle[ThePipeline::MaxThreads];
654 std::list<ThreadID> fetchPriorityList;
657 /** Active Threads List */
658 std::list<ThreadID> activeThreads;
660 /** Ready Threads List */
661 std::list<ThreadID> readyThreads;
663 /** Suspended Threads List */
664 std::list<ThreadID> suspendedThreads;
666 /** Halted Threads List */
667 std::list<ThreadID> haltedThreads;
669 /** Thread Status Functions */
670 bool isThreadActive(ThreadID tid);
671 bool isThreadReady(ThreadID tid);
672 bool isThreadSuspended(ThreadID tid);
675 /** The activity recorder; used to tell if the CPU has any
676 * activity remaining or if it can go to idle and deschedule
679 ActivityRecorder activityRec;
682 /** Number of Active Threads in the CPU */
683 ThreadID numActiveThreads() { return activeThreads.size(); }
685 /** Thread id of active thread
686 * Only used for SwitchOnCacheMiss model.
687 * Assumes only 1 thread active
689 ThreadID activeThreadId()
691 if (numActiveThreads() > 0)
692 return activeThreads.front();
694 return InvalidThreadID;
698 /** Records that there was time buffer activity this cycle. */
699 void activityThisCycle() { activityRec.activity(); }
701 /** Changes a stage's status to active within the activity recorder. */
702 void activateStage(const int idx)
703 { activityRec.activateStage(idx); }
705 /** Changes a stage's status to inactive within the activity recorder. */
706 void deactivateStage(const int idx)
707 { activityRec.deactivateStage(idx); }
709 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
713 virtual void wakeup();
716 // LL/SC debug functionality
717 unsigned stCondFails;
719 unsigned readStCondFailures()
720 { return stCondFails; }
722 unsigned setStCondFailures(unsigned st_fails)
723 { return stCondFails = st_fails; }
725 /** Returns a pointer to a thread context. */
726 ThreadContext *tcBase(ThreadID tid = 0)
728 return thread[tid]->getTC();
731 /** Count the Total Instructions Committed in the CPU. */
732 virtual Counter totalInstructions() const
736 for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
737 total += thread[tid]->numInst;
743 /** Pointer to the system. */
746 /** Pointer to physical memory. */
747 PhysicalMemory *physmem;
750 /** The global sequence number counter. */
751 InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
754 /** The global event number counter. */
755 InstSeqNum cpuEventNum;
757 /** Number of resource requests active in CPU **/
758 unsigned resReqCount;
761 /** Counter of how many stages have completed switching out. */
764 /** Pointers to all of the threads in the CPU. */
765 std::vector<Thread *> thread;
767 /** Pointer to the icache interface. */
768 MemInterface *icacheInterface;
770 /** Pointer to the dcache interface. */
771 MemInterface *dcacheInterface;
773 /** Whether or not the CPU should defer its registration. */
774 bool deferRegistration;
776 /** Per-Stage Instruction Tracing */
779 /** The cycle that the CPU was last running, used for statistics. */
780 Tick lastRunningCycle;
782 void updateContextSwitchStats();
783 unsigned instsPerSwitch;
784 Stats::Average instsPerCtxtSwitch;
785 Stats::Scalar numCtxtSwitches;
787 /** Update Thread , used for statistic purposes*/
788 inline void tickThreadStats();
790 /** Per-Thread Tick */
791 Stats::Vector threadCycles;
794 Stats::Scalar smtCycles;
796 /** Stat for total number of times the CPU is descheduled. */
797 Stats::Scalar timesIdled;
799 /** Stat for total number of cycles the CPU spends descheduled or no
802 Stats::Scalar idleCycles;
804 /** Stat for total number of cycles the CPU is active. */
805 Stats::Scalar runCycles;
807 /** Percentage of cycles a stage was active */
808 Stats::Formula activity;
810 /** Instruction Mix Stats */
811 Stats::Scalar comLoads;
812 Stats::Scalar comStores;
813 Stats::Scalar comBranches;
814 Stats::Scalar comNops;
815 Stats::Scalar comNonSpec;
816 Stats::Scalar comInts;
817 Stats::Scalar comFloats;
819 /** Stat for the number of committed instructions per thread. */
820 Stats::Vector committedInsts;
822 /** Stat for the number of committed instructions per thread. */
823 Stats::Vector smtCommittedInsts;
825 /** Stat for the total number of committed instructions. */
826 Stats::Scalar totalCommittedInsts;
828 /** Stat for the CPI per thread. */
831 /** Stat for the SMT-CPI per thread. */
832 Stats::Formula smtCpi;
834 /** Stat for the total CPI. */
835 Stats::Formula totalCpi;
837 /** Stat for the IPC per thread. */
840 /** Stat for the total IPC. */
841 Stats::Formula smtIpc;
843 /** Stat for the total IPC. */
844 Stats::Formula totalIpc;
847 #endif // __CPU_O3_CPU_HH__