2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_CPU_HH__
33 #define __CPU_INORDER_CPU_HH__
41 #include "arch/isa_traits.hh"
42 #include "arch/types.hh"
43 #include "arch/registers.hh"
44 #include "base/statistics.hh"
45 #include "cpu/timebuf.hh"
46 #include "base/types.hh"
47 #include "config/full_system.hh"
48 #include "config/the_isa.hh"
49 #include "cpu/activity.hh"
50 #include "cpu/base.hh"
51 #include "cpu/simple_thread.hh"
52 #include "cpu/inorder/inorder_dyn_inst.hh"
53 #include "cpu/inorder/pipeline_traits.hh"
54 #include "cpu/inorder/pipeline_stage.hh"
55 #include "cpu/inorder/thread_state.hh"
56 #include "cpu/inorder/reg_dep_map.hh"
57 #include "cpu/o3/dep_graph.hh"
58 #include "cpu/o3/rename_map.hh"
59 #include "mem/packet.hh"
60 #include "mem/port.hh"
61 #include "mem/request.hh"
62 #include "sim/eventq.hh"
63 #include "sim/process.hh"
71 class InOrderCPU : public BaseCPU
75 typedef ThePipeline::Params Params;
76 typedef InOrderThreadState Thread;
79 typedef TheISA::IntReg IntReg;
80 typedef TheISA::FloatReg FloatReg;
81 typedef TheISA::FloatRegBits FloatRegBits;
82 typedef TheISA::MiscReg MiscReg;
85 typedef ThePipeline::DynInstPtr DynInstPtr;
86 typedef std::list<DynInstPtr>::iterator ListIt;
89 typedef TimeBuffer<InterStageStruct> StageQueue;
91 friend class Resource;
94 /** Constructs a CPU with the given parameters. */
95 InOrderCPU(Params *params);
103 ThreadID asid[ThePipeline::MaxThreads];
105 /** Type of core that this is */
106 std::string coreType;
108 // Only need for SE MODE
115 ThreadModel threadModel;
117 int readCpuId() { return cpu_id; }
119 void setCpuId(int val) { cpu_id = val; }
132 /** Overall CPU status. */
135 /** Define TickEvent for the CPU */
136 class TickEvent : public Event
139 /** Pointer to the CPU. */
143 /** Constructs a tick event. */
144 TickEvent(InOrderCPU *c);
146 /** Processes a tick event, calling tick() on the CPU. */
149 /** Returns the description of the tick event. */
150 const char *description();
153 /** The tick event used for scheduling CPU ticks. */
156 /** Schedule tick event, regardless of its current state. */
157 void scheduleTickEvent(int delay)
159 assert(!tickEvent.scheduled() || tickEvent.squashed());
160 reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
163 /** Unschedule tick event, regardless of its current state. */
164 void unscheduleTickEvent()
166 if (tickEvent.scheduled())
171 // List of Events That can be scheduled from
173 // NOTE(1): The Resource Pool also uses this event list
174 // to schedule events broadcast to all resources interfaces
175 // NOTE(2): CPU Events usually need to schedule a corresponding resource
179 ActivateNextReadyThread,
190 static std::string eventNames[NumCPUEvents];
192 /** Define CPU Event */
193 class CPUEvent : public Event
199 CPUEventType cpuEventType;
206 /** Constructs a CPU event. */
207 CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
208 ThreadID _tid, DynInstPtr inst, unsigned event_pri_offset);
210 /** Set Type of Event To Be Scheduled */
211 void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
215 cpuEventType = e_type;
221 /** Processes a CPU event. */
224 /** Returns the description of the CPU event. */
225 const char *description();
227 /** Schedule Event */
228 void scheduleEvent(int delay);
230 /** Unschedule This Event */
231 void unscheduleEvent();
234 /** Schedule a CPU Event */
235 void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
236 DynInstPtr inst, unsigned delay = 0,
237 unsigned event_pri_offset = 0);
240 /** Interface between the CPU and CPU resources. */
241 ResourcePool *resPool;
243 /** Instruction used to signify that there is no *real* instruction in
245 DynInstPtr dummyInst[ThePipeline::MaxThreads];
246 DynInstPtr dummyBufferInst;
247 DynInstPtr dummyReqInst;
249 /** Used by resources to signify a denied access to a resource. */
250 ResourceRequest *dummyReq[ThePipeline::MaxThreads];
252 /** Identifies the resource id that identifies a fetch
255 unsigned fetchPortIdx;
257 /** Identifies the resource id that identifies a ITB */
260 /** Identifies the resource id that identifies a data
263 unsigned dataPortIdx;
265 /** Identifies the resource id that identifies a DTB */
268 /** The Pipeline Stages for the CPU */
269 PipelineStage *pipelineStage[ThePipeline::NumStages];
271 /** Program Counters */
272 TheISA::PCState pc[ThePipeline::MaxThreads];
274 /** The Register File for the CPU */
276 FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
277 FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
279 TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
282 TheISA::ISA isa[ThePipeline::MaxThreads];
284 /** Dependency Tracker for Integer & Floating Point Regs */
285 RegDepMap archRegDepMap[ThePipeline::MaxThreads];
287 /** Global communication structure */
288 TimeBuffer<TimeStruct> timeBuffer;
290 /** Communication structure that sits in between pipeline stages */
291 StageQueue *stageQueue[ThePipeline::NumStages-1];
293 TheISA::TLB *getITBPtr();
294 TheISA::TLB *getDTBPtr();
298 /** Registers statistics. */
301 /** Ticks CPU, calling tick() on each stage, and checking the overall
302 * activity to see if the CPU should deschedule itself.
306 /** Initialize the CPU */
309 /** Reset State in the CPU */
312 /** Get a Memory Port */
313 Port* getPort(const std::string &if_name, int idx = 0);
316 /** HW return from error interrupt. */
317 Fault hwrei(ThreadID tid);
319 bool simPalCheck(int palFunc, ThreadID tid);
321 /** Returns the Fault for any valid interrupt. */
322 Fault getInterrupts();
324 /** Processes any an interrupt fault. */
325 void processInterrupts(Fault interrupt);
327 /** Halts the CPU. */
328 void halt() { panic("Halt not implemented!\n"); }
330 /** Update the Virt and Phys ports of all ThreadContexts to
331 * reflect change in memory connections. */
332 void updateMemPorts();
334 /** Check if this address is a valid instruction address. */
335 bool validInstAddr(Addr addr) { return true; }
337 /** Check if this address is a valid data address. */
338 bool validDataAddr(Addr addr) { return true; }
341 /** trap() - sets up a trap event on the cpuTraps to handle given fault.
342 * trapCPU() - Traps to handle given fault
344 void trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
345 void trapCPU(Fault fault, ThreadID tid, DynInstPtr inst);
347 /** Add Thread to Active Threads List. */
348 void activateContext(ThreadID tid, int delay = 0);
349 void activateThread(ThreadID tid);
350 void activateThreadInPipeline(ThreadID tid);
352 /** Add Thread to Active Threads List. */
353 void activateNextReadyContext(int delay = 0);
354 void activateNextReadyThread();
356 /** Remove from Active Thread List */
357 void deactivateContext(ThreadID tid, int delay = 0);
358 void deactivateThread(ThreadID tid);
360 /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
361 void suspendContext(ThreadID tid, int delay = 0);
362 void suspendThread(ThreadID tid);
364 /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
367 void haltContext(ThreadID tid, int delay = 0);
368 void haltThread(ThreadID tid);
370 /** squashFromMemStall() - sets up a squash event
371 * squashDueToMemStall() - squashes pipeline
372 * @note: maybe squashContext/squashThread would be better?
374 void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
375 void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
377 void removePipelineStalls(ThreadID tid);
378 void squashThreadInPipeline(ThreadID tid);
379 void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
381 PipelineStage* getPipeStage(int stage_num);
386 hack_once("return a bogus context id");
390 /** Update The Order In Which We Process Threads. */
391 void updateThreadPriority();
393 /** Switches a Pipeline Stage to Active. (Unused currently) */
394 void switchToActive(int stage_idx)
395 { /*pipelineStage[stage_idx]->switchToActive();*/ }
397 /** Get the current instruction sequence number, and increment it. */
398 InstSeqNum getAndIncrementInstSeq(ThreadID tid)
399 { return globalSeqNum[tid]++; }
401 /** Get the current instruction sequence number, and increment it. */
402 InstSeqNum nextInstSeqNum(ThreadID tid)
403 { return globalSeqNum[tid]; }
405 /** Increment Instruction Sequence Number */
406 void incrInstSeqNum(ThreadID tid)
407 { globalSeqNum[tid]++; }
409 /** Set Instruction Sequence Number */
410 void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
412 globalSeqNum[tid] = seq_num;
415 /** Get & Update Next Event Number */
416 InstSeqNum getNextEventNum()
419 return cpuEventNum++;
425 /** Register file accessors */
426 uint64_t readIntReg(int reg_idx, ThreadID tid);
428 FloatReg readFloatReg(int reg_idx, ThreadID tid);
430 FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
432 void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
434 void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
436 void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid);
438 /** Reads a miscellaneous register. */
439 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
441 /** Reads a misc. register, including any side effects the read
442 * might have as defined by the architecture.
444 MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
446 /** Sets a miscellaneous register. */
447 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
450 /** Sets a misc. register, including any side effects the write
451 * might have as defined by the architecture.
453 void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
455 /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
458 uint64_t readRegOtherThread(unsigned misc_reg,
459 ThreadID tid = InvalidThreadID);
461 /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
464 void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
467 /** Reads the commit PC of a specific thread. */
469 pcState(ThreadID tid)
474 /** Sets the commit PC of a specific thread. */
476 pcState(const TheISA::PCState &newPC, ThreadID tid)
481 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
482 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
483 MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
485 /** Function to add instruction onto the head of the list of the
486 * instructions. Used when new instructions are fetched.
488 ListIt addInst(DynInstPtr &inst);
490 /** Function to tell the CPU that an instruction has completed. */
491 void instDone(DynInstPtr inst, ThreadID tid);
493 /** Add Instructions to the CPU Remove List*/
494 void addToRemoveList(DynInstPtr &inst);
496 /** Remove an instruction from CPU */
497 void removeInst(DynInstPtr &inst);
499 /** Remove all instructions younger than the given sequence number. */
500 void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
502 /** Removes the instruction pointed to by the iterator. */
503 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
505 /** Cleans up all instructions on the instruction remove list. */
506 void cleanUpRemovedInsts();
508 /** Cleans up all instructions on the request remove list. */
509 void cleanUpRemovedReqs();
511 /** Cleans up all instructions on the CPU event remove list. */
512 void cleanUpRemovedEvents();
514 /** Debug function to print all instructions on the list. */
517 /** Forwards an instruction read to the appropriate data
518 * resource (indexes into Resource Pool thru "dataPortIdx")
520 Fault read(DynInstPtr inst, Addr addr,
521 uint8_t *data, unsigned size, unsigned flags);
523 /** Forwards an instruction write. to the appropriate data
524 * resource (indexes into Resource Pool thru "dataPortIdx")
526 Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
527 Addr addr, unsigned flags, uint64_t *write_res = NULL);
529 /** Executes a syscall.*/
530 void syscall(int64_t callnum, ThreadID tid);
533 /** Per-Thread List of all the instructions in flight. */
534 std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
536 /** List of all the instructions that will be removed at the end of this
539 std::queue<ListIt> removeList;
541 /** List of all the resource requests that will be removed at the end
544 std::queue<ResourceRequest*> reqRemoveList;
546 /** List of all the cpu event requests that will be removed at the end of
549 std::queue<Event*> cpuEventRemoveList;
551 /** Records if instructions need to be removed this cycle due to
552 * being retired or squashed.
554 bool removeInstsThisCycle;
556 /** True if there is non-speculative Inst Active In Pipeline. Lets any
557 * execution unit know, NOT to execute while the instruction is active.
559 bool nonSpecInstActive[ThePipeline::MaxThreads];
561 /** Instruction Seq. Num of current non-speculative instruction. */
562 InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
564 /** Instruction Seq. Num of last instruction squashed in pipeline */
565 InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
567 /** Last Cycle that the CPU squashed instruction end. */
568 Tick lastSquashCycle[ThePipeline::MaxThreads];
570 std::list<ThreadID> fetchPriorityList;
573 /** Active Threads List */
574 std::list<ThreadID> activeThreads;
576 /** Ready Threads List */
577 std::list<ThreadID> readyThreads;
579 /** Suspended Threads List */
580 std::list<ThreadID> suspendedThreads;
582 /** Halted Threads List */
583 std::list<ThreadID> haltedThreads;
585 /** Thread Status Functions */
586 bool isThreadActive(ThreadID tid);
587 bool isThreadReady(ThreadID tid);
588 bool isThreadSuspended(ThreadID tid);
591 /** The activity recorder; used to tell if the CPU has any
592 * activity remaining or if it can go to idle and deschedule
595 ActivityRecorder activityRec;
598 /** Number of Active Threads in the CPU */
599 ThreadID numActiveThreads() { return activeThreads.size(); }
601 /** Thread id of active thread
602 * Only used for SwitchOnCacheMiss model.
603 * Assumes only 1 thread active
605 ThreadID activeThreadId()
607 if (numActiveThreads() > 0)
608 return activeThreads.front();
610 return InvalidThreadID;
614 /** Records that there was time buffer activity this cycle. */
615 void activityThisCycle() { activityRec.activity(); }
617 /** Changes a stage's status to active within the activity recorder. */
618 void activateStage(const int idx)
619 { activityRec.activateStage(idx); }
621 /** Changes a stage's status to inactive within the activity recorder. */
622 void deactivateStage(const int idx)
623 { activityRec.deactivateStage(idx); }
625 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
629 virtual void wakeup();
632 // LL/SC debug functionality
633 unsigned stCondFails;
635 unsigned readStCondFailures()
636 { return stCondFails; }
638 unsigned setStCondFailures(unsigned st_fails)
639 { return stCondFails = st_fails; }
641 /** Returns a pointer to a thread context. */
642 ThreadContext *tcBase(ThreadID tid = 0)
644 return thread[tid]->getTC();
647 /** Count the Total Instructions Committed in the CPU. */
648 virtual Counter totalInstructions() const
652 for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
653 total += thread[tid]->numInst;
659 /** Pointer to the system. */
662 /** Pointer to physical memory. */
663 PhysicalMemory *physmem;
666 /** The global sequence number counter. */
667 InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
670 /** The global event number counter. */
671 InstSeqNum cpuEventNum;
673 /** Number of resource requests active in CPU **/
674 unsigned resReqCount;
677 /** Counter of how many stages have completed switching out. */
680 /** Pointers to all of the threads in the CPU. */
681 std::vector<Thread *> thread;
683 /** Pointer to the icache interface. */
684 MemInterface *icacheInterface;
686 /** Pointer to the dcache interface. */
687 MemInterface *dcacheInterface;
689 /** Whether or not the CPU should defer its registration. */
690 bool deferRegistration;
692 /** Per-Stage Instruction Tracing */
695 /** The cycle that the CPU was last running, used for statistics. */
696 Tick lastRunningCycle;
698 void updateContextSwitchStats();
699 unsigned instsPerSwitch;
700 Stats::Average instsPerCtxtSwitch;
701 Stats::Scalar numCtxtSwitches;
703 /** Update Thread , used for statistic purposes*/
704 inline void tickThreadStats();
706 /** Per-Thread Tick */
707 Stats::Vector threadCycles;
710 Stats::Scalar smtCycles;
712 /** Stat for total number of times the CPU is descheduled. */
713 Stats::Scalar timesIdled;
715 /** Stat for total number of cycles the CPU spends descheduled or no
718 Stats::Scalar idleCycles;
720 /** Stat for total number of cycles the CPU is active. */
721 Stats::Scalar runCycles;
723 /** Percentage of cycles a stage was active */
724 Stats::Formula activity;
726 /** Instruction Mix Stats */
727 Stats::Scalar comLoads;
728 Stats::Scalar comStores;
729 Stats::Scalar comBranches;
730 Stats::Scalar comNops;
731 Stats::Scalar comNonSpec;
732 Stats::Scalar comInts;
733 Stats::Scalar comFloats;
735 /** Stat for the number of committed instructions per thread. */
736 Stats::Vector committedInsts;
738 /** Stat for the number of committed instructions per thread. */
739 Stats::Vector smtCommittedInsts;
741 /** Stat for the total number of committed instructions. */
742 Stats::Scalar totalCommittedInsts;
744 /** Stat for the CPI per thread. */
747 /** Stat for the SMT-CPI per thread. */
748 Stats::Formula smtCpi;
750 /** Stat for the total CPI. */
751 Stats::Formula totalCpi;
753 /** Stat for the IPC per thread. */
756 /** Stat for the total IPC. */
757 Stats::Formula smtIpc;
759 /** Stat for the total IPC. */
760 Stats::Formula totalIpc;
763 #endif // __CPU_O3_CPU_HH__