src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/registers.hh"
  43 #include "arch/types.hh"
  44 #include "base/statistics.hh"
  45 #include "base/types.hh"
  46 #include "config/full_system.hh"
  47 #include "config/the_isa.hh"
  48 #include "cpu/inorder/inorder_dyn_inst.hh"
  49 #include "cpu/inorder/pipeline_stage.hh"
  50 #include "cpu/inorder/pipeline_traits.hh"
  51 #include "cpu/inorder/reg_dep_map.hh"
  52 #include "cpu/inorder/thread_state.hh"
  53 #include "cpu/o3/dep_graph.hh"
  54 #include "cpu/o3/rename_map.hh"
  55 #include "cpu/activity.hh"
  56 #include "cpu/base.hh"
  57 #include "cpu/simple_thread.hh"
  58 #include "cpu/timebuf.hh"
  59 #include "mem/packet.hh"
  60 #include "mem/port.hh"
  61 #include "mem/request.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/process.hh"
  64
  65 class ThreadContext;
  66 class MemInterface;
  67 class MemObject;
  68 class Process;
  69 class ResourcePool;
  70
  71 class InOrderCPU : public BaseCPU
  72 {
  73
  74   protected:
  75     typedef ThePipeline::Params Params;
  76     typedef InOrderThreadState Thread;
  77
  78    //ISA TypeDefs
  79     typedef TheISA::IntReg IntReg;
  80     typedef TheISA::FloatReg FloatReg;
  81     typedef TheISA::FloatRegBits FloatRegBits;
  82     typedef TheISA::MiscReg MiscReg;
  83     typedef TheISA::RegIndex RegIndex;
  84
  85     //DynInstPtr TypeDefs
  86     typedef ThePipeline::DynInstPtr DynInstPtr;
  87     typedef std::list<DynInstPtr>::iterator ListIt;
  88
  89     //TimeBuffer TypeDefs
  90     typedef TimeBuffer<InterStageStruct> StageQueue;
  91
  92     friend class Resource;
  93
  94   public:
  95     /** Constructs a CPU with the given parameters. */
  96     InOrderCPU(Params *params);
  97     /* Destructor */
  98     ~InOrderCPU();
  99
 100     /** CPU ID */
 101     int cpu_id;
 102
 103     // SE Mode ASIDs
 104     ThreadID asid[ThePipeline::MaxThreads];
 105
 106     /** Type of core that this is */
 107     std::string coreType;
 108
 109     // Only need for SE MODE
 110     enum ThreadModel {
 111         Single,
 112         SMT,
 113         SwitchOnCacheMiss
 114     };
 115
 116     ThreadModel threadModel;
 117
 118     int readCpuId() { return cpu_id; }
 119
 120     void setCpuId(int val) { cpu_id = val; }
 121
 122     Params *cpu_params;
 123
 124   public:
 125     enum Status {
 126         Running,
 127         Idle,
 128         Halted,
 129         Blocked,
 130         SwitchedOut
 131     };
 132
 133     /** Overall CPU status. */
 134     Status _status;
 135   private:
 136     /** Define TickEvent for the CPU */
 137     class TickEvent : public Event
 138     {
 139       private:
 140         /** Pointer to the CPU. */
 141         InOrderCPU *cpu;
 142
 143       public:
 144         /** Constructs a tick event. */
 145         TickEvent(InOrderCPU *c);
 146
 147         /** Processes a tick event, calling tick() on the CPU. */
 148         void process();
 149
 150         /** Returns the description of the tick event. */
 151         const char *description();
 152     };
 153
 154     /** The tick event used for scheduling CPU ticks. */
 155     TickEvent tickEvent;
 156
 157     /** Schedule tick event, regardless of its current state. */
 158     void scheduleTickEvent(int delay)
 159     {
 160         assert(!tickEvent.scheduled() || tickEvent.squashed());
 161         reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
 162     }
 163
 164     /** Unschedule tick event, regardless of its current state. */
 165     void unscheduleTickEvent()
 166     {
 167         if (tickEvent.scheduled())
 168             tickEvent.squash();
 169     }
 170
 171   public:
 172     // List of Events That can be scheduled from
 173     // within the CPU.
 174     // NOTE(1): The Resource Pool also uses this event list
 175     // to schedule events broadcast to all resources interfaces
 176     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 177     // pool event.
 178     enum CPUEventType {
 179         ActivateThread,
 180         ActivateNextReadyThread,
 181         DeactivateThread,
 182         HaltThread,
 183         SuspendThread,
 184         Trap,
 185         InstGraduated,
 186         SquashFromMemStall,
 187         UpdatePCs,
 188         NumCPUEvents
 189     };
 190
 191     static std::string eventNames[NumCPUEvents];
 192
 193     enum CPUEventPri {
 194         InOrderCPU_Pri                 = Event::CPU_Tick_Pri,
 195         ActivateNextReadyThread_Pri    = Event::CPU_Tick_Pri + 10
 196     };
 197
 198     /** Define CPU Event */
 199     class CPUEvent : public Event
 200     {
 201       protected:
 202         InOrderCPU *cpu;
 203
 204       public:
 205         CPUEventType cpuEventType;
 206         ThreadID tid;
 207         DynInstPtr inst;
 208         Fault fault;
 209         unsigned vpe;
 210
 211       public:
 212         /** Constructs a CPU event. */
 213         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 214                  ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
 215
 216         /** Set Type of Event To Be Scheduled */
 217         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 218                       DynInstPtr _inst)
 219         {
 220             fault = _fault;
 221             cpuEventType = e_type;
 222             tid = _tid;
 223             inst = _inst;
 224             vpe = 0;
 225         }
 226
 227         /** Processes a CPU event. */
 228         void process();
 229
 230         /** Returns the description of the CPU event. */
 231         const char *description();
 232
 233         /** Schedule Event */
 234         void scheduleEvent(int delay);
 235
 236         /** Unschedule This Event */
 237         void unscheduleEvent();
 238     };
 239
 240     /** Schedule a CPU Event */
 241     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 242                           DynInstPtr inst, unsigned delay = 0,
 243                           CPUEventPri event_pri = InOrderCPU_Pri);
 244
 245   public:
 246     /** Interface between the CPU and CPU resources. */
 247     ResourcePool *resPool;
 248
 249     /** Instruction used to signify that there is no *real* instruction in
 250         buffer slot */
 251     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 252     DynInstPtr dummyBufferInst;
 253     DynInstPtr dummyReqInst;
 254
 255     /** Used by resources to signify a denied access to a resource. */
 256     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 257
 258     /** Identifies the resource id that identifies a fetch
 259      * access unit.
 260      */
 261     unsigned fetchPortIdx;
 262
 263     /** Identifies the resource id that identifies a ITB       */
 264     unsigned itbIdx;
 265
 266     /** Identifies the resource id that identifies a data
 267      * access unit.
 268      */
 269     unsigned dataPortIdx;
 270
 271     /** Identifies the resource id that identifies a DTB       */
 272     unsigned dtbIdx;
 273
 274     /** The Pipeline Stages for the CPU */
 275     PipelineStage *pipelineStage[ThePipeline::NumStages];
 276
 277     /** Width (processing bandwidth) of each stage */
 278     int stageWidth;
 279
 280     /** Program Counters */
 281     TheISA::PCState pc[ThePipeline::MaxThreads];
 282
 283     /** Last Committed PC */
 284     TheISA::PCState lastCommittedPC[ThePipeline::MaxThreads];
 285
 286     /** The Register File for the CPU */
 287     union {
 288         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 289         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 290     } floatRegs;
 291     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 292
 293     /** ISA state */
 294     TheISA::ISA isa[ThePipeline::MaxThreads];
 295
 296     /** Dependency Tracker for Integer & Floating Point Regs */
 297     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 298
 299     /** Register Types Used in Dependency Tracking */
 300     enum RegType { IntType, FloatType, MiscType, NumRegTypes};
 301
 302     /** Global communication structure */
 303     TimeBuffer<TimeStruct> timeBuffer;
 304
 305     /** Communication structure that sits in between pipeline stages */
 306     StageQueue *stageQueue[ThePipeline::NumStages-1];
 307
 308     TheISA::TLB *getITBPtr();
 309     TheISA::TLB *getDTBPtr();
 310
 311     /** Accessor Type for the SkedCache */
 312     typedef uint32_t SkedID;
 313
 314     /** Cache of Instruction Schedule using the instruction's name as a key */
 315     static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
 316
 317     typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 318
 319     /** Initialized to last iterator in map, signifying a invalid entry
 320         on map searches
 321     */
 322     SkedCacheIt endOfSkedIt;
 323
 324     ThePipeline::RSkedPtr frontEndSked;
 325
 326     /** Add a new instruction schedule to the schedule cache */
 327     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 328     {
 329         SkedID sked_id = genSkedID(inst);
 330         assert(skedCache.find(sked_id) == skedCache.end());
 331         skedCache[sked_id] = inst_sked;
 332     }
 333
 334
 335     /** Find a instruction schedule */
 336     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 337     {
 338         SkedID sked_id = genSkedID(inst);
 339         SkedCacheIt lookup_it = skedCache.find(sked_id);
 340
 341         if (lookup_it != endOfSkedIt) {
 342             return (*lookup_it).second;
 343         } else {
 344             return NULL;
 345         }
 346     }
 347
 348     static const uint8_t INST_OPCLASS                       = 26;
 349     static const uint8_t INST_LOAD                          = 25;
 350     static const uint8_t INST_STORE                         = 24;
 351     static const uint8_t INST_CONTROL                       = 23;
 352     static const uint8_t INST_NONSPEC                       = 22;
 353     static const uint8_t INST_DEST_REGS                     = 18;
 354     static const uint8_t INST_SRC_REGS                      = 14;
 355     static const uint8_t INST_SPLIT_DATA                    = 13;
 356
 357     inline SkedID genSkedID(DynInstPtr inst)
 358     {
 359         SkedID id = 0;
 360         id = (inst->opClass() << INST_OPCLASS) |
 361             (inst->isLoad() << INST_LOAD) |
 362             (inst->isStore() << INST_STORE) |
 363             (inst->isControl() << INST_CONTROL) |
 364             (inst->isNonSpeculative() << INST_NONSPEC) |
 365             (inst->numDestRegs() << INST_DEST_REGS) |
 366             (inst->numSrcRegs() << INST_SRC_REGS) |
 367             (inst->splitInst << INST_SPLIT_DATA);
 368         return id;
 369     }
 370
 371     ThePipeline::RSkedPtr createFrontEndSked();
 372     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 373
 374     class StageScheduler {
 375       private:
 376         ThePipeline::RSkedPtr rsked;
 377         int stageNum;
 378         int nextTaskPriority;
 379
 380       public:
 381         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 382             : rsked(_rsked), stageNum(stage_num),
 383               nextTaskPriority(0)
 384         { }
 385
 386         void needs(int unit, int request) {
 387             rsked->push(new ScheduleEntry(
 388                             stageNum, nextTaskPriority++, unit, request
 389                             ));
 390         }
 391
 392         void needs(int unit, int request, int param) {
 393             rsked->push(new ScheduleEntry(
 394                             stageNum, nextTaskPriority++, unit, request, param
 395                             ));
 396         }
 397     };
 398
 399   public:
 400
 401     /** Registers statistics. */
 402     void regStats();
 403
 404     /** Ticks CPU, calling tick() on each stage, and checking the overall
 405      *  activity to see if the CPU should deschedule itself.
 406      */
 407     void tick();
 408
 409     /** Initialize the CPU */
 410     void init();
 411
 412     /** Get a Memory Port */
 413     Port* getPort(const std::string &if_name, int idx = 0);
 414
 415 #if FULL_SYSTEM
 416     /** HW return from error interrupt. */
 417     Fault hwrei(ThreadID tid);
 418
 419     bool simPalCheck(int palFunc, ThreadID tid);
 420
 421     /** Returns the Fault for any valid interrupt. */
 422     Fault getInterrupts();
 423
 424     /** Processes any an interrupt fault. */
 425     void processInterrupts(Fault interrupt);
 426
 427     /** Halts the CPU. */
 428     void halt() { panic("Halt not implemented!\n"); }
 429
 430     /** Update the Virt and Phys ports of all ThreadContexts to
 431      * reflect change in memory connections. */
 432     void updateMemPorts();
 433
 434     /** Check if this address is a valid instruction address. */
 435     bool validInstAddr(Addr addr) { return true; }
 436
 437     /** Check if this address is a valid data address. */
 438     bool validDataAddr(Addr addr) { return true; }
 439 #endif
 440
 441     /** Schedule a trap on the CPU */
 442     void trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
 443
 444     /** Perform trap to Handle Given Fault */
 445     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 446
 447     /** Schedule thread activation on the CPU */
 448     void activateContext(ThreadID tid, int delay = 0);
 449
 450     /** Add Thread to Active Threads List. */
 451     void activateThread(ThreadID tid);
 452
 453     /** Activate Thread In Each Pipeline Stage */
 454     void activateThreadInPipeline(ThreadID tid);
 455
 456     /** Schedule Thread Activation from Ready List */
 457     void activateNextReadyContext(int delay = 0);
 458
 459     /** Add Thread From Ready List to Active Threads List. */
 460     void activateNextReadyThread();
 461
 462     /** Schedule a thread deactivation on the CPU */
 463     void deactivateContext(ThreadID tid, int delay = 0);
 464
 465     /** Remove from Active Thread List */
 466     void deactivateThread(ThreadID tid);
 467
 468     /** Schedule a thread suspension on the CPU */
 469     void suspendContext(ThreadID tid, int delay = 0);
 470
 471     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 472     void suspendThread(ThreadID tid);
 473
 474     /** Schedule a thread halt on the CPU */
 475     void haltContext(ThreadID tid, int delay = 0);
 476
 477     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 478      *  Threads List
 479      */
 480     void haltThread(ThreadID tid);
 481
 482     /** squashFromMemStall() - sets up a squash event
 483      *  squashDueToMemStall() - squashes pipeline
 484      *  @note: maybe squashContext/squashThread would be better?
 485      */
 486     void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
 487     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 488
 489     void removePipelineStalls(ThreadID tid);
 490     void squashThreadInPipeline(ThreadID tid);
 491     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 492
 493     PipelineStage* getPipeStage(int stage_num);
 494
 495     int
 496     contextId()
 497     {
 498         hack_once("return a bogus context id");
 499         return 0;
 500     }
 501
 502     /** Update The Order In Which We Process Threads. */
 503     void updateThreadPriority();
 504
 505     /** Switches a Pipeline Stage to Active. (Unused currently) */
 506     void switchToActive(int stage_idx)
 507     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 508
 509     /** Get the current instruction sequence number, and increment it. */
 510     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 511     { return globalSeqNum[tid]++; }
 512
 513     /** Get the current instruction sequence number, and increment it. */
 514     InstSeqNum nextInstSeqNum(ThreadID tid)
 515     { return globalSeqNum[tid]; }
 516
 517     /** Increment Instruction Sequence Number */
 518     void incrInstSeqNum(ThreadID tid)
 519     { globalSeqNum[tid]++; }
 520
 521     /** Set Instruction Sequence Number */
 522     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 523     {
 524         globalSeqNum[tid] = seq_num;
 525     }
 526
 527     /** Get & Update Next Event Number */
 528     InstSeqNum getNextEventNum()
 529     {
 530 #ifdef DEBUG
 531         return cpuEventNum++;
 532 #else
 533         return 0;
 534 #endif
 535     }
 536
 537     /** Register file accessors  */
 538     uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
 539
 540     FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
 541
 542     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 543
 544     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 545
 546     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 547
 548     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 549
 550     RegType inline getRegType(RegIndex reg_idx)
 551     {
 552         if (reg_idx < TheISA::FP_Base_DepTag)
 553             return IntType;
 554         else if (reg_idx < TheISA::Ctrl_Base_DepTag)
 555             return FloatType;
 556         else
 557             return MiscType;
 558     }
 559
 560     RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
 561
 562     /** Reads a miscellaneous register. */
 563     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 564
 565     /** Reads a misc. register, including any side effects the read
 566      * might have as defined by the architecture.
 567      */
 568     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 569
 570     /** Sets a miscellaneous register. */
 571     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 572                             ThreadID tid = 0);
 573
 574     /** Sets a misc. register, including any side effects the write
 575      * might have as defined by the architecture.
 576      */
 577     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 578
 579     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 580      *  target thread
 581      */
 582     uint64_t readRegOtherThread(unsigned misc_reg,
 583                                 ThreadID tid = InvalidThreadID);
 584
 585     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 586      * target thread
 587      */
 588     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 589                            ThreadID tid);
 590
 591     /** Reads the commit PC of a specific thread. */
 592     TheISA::PCState
 593     pcState(ThreadID tid)
 594     {
 595         return pc[tid];
 596     }
 597
 598     /** Sets the commit PC of a specific thread. */
 599     void
 600     pcState(const TheISA::PCState &newPC, ThreadID tid)
 601     {
 602         pc[tid] = newPC;
 603     }
 604
 605     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 606     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 607     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 608
 609     /** Function to add instruction onto the head of the list of the
 610      *  instructions.  Used when new instructions are fetched.
 611      */
 612     ListIt addInst(DynInstPtr inst);
 613
 614     /** Find instruction on instruction list */
 615     ListIt findInst(InstSeqNum seq_num, ThreadID tid);
 616
 617     /** Function to tell the CPU that an instruction has completed. */
 618     void instDone(DynInstPtr inst, ThreadID tid);
 619
 620     /** Add Instructions to the CPU Remove List*/
 621     void addToRemoveList(DynInstPtr inst);
 622
 623     /** Remove an instruction from CPU */
 624     void removeInst(DynInstPtr inst);
 625
 626     /** Remove all instructions younger than the given sequence number. */
 627     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 628
 629     /** Removes the instruction pointed to by the iterator. */
 630     inline void squashInstIt(const ListIt inst_it, ThreadID tid);
 631
 632     /** Cleans up all instructions on the instruction remove list. */
 633     void cleanUpRemovedInsts();
 634
 635     /** Cleans up all events on the CPU event remove list. */
 636     void cleanUpRemovedEvents();
 637
 638     /** Debug function to print all instructions on the list. */
 639     void dumpInsts();
 640
 641     /** Forwards an instruction read to the appropriate data
 642      *  resource (indexes into Resource Pool thru "dataPortIdx")
 643      */
 644     Fault read(DynInstPtr inst, Addr addr,
 645                uint8_t *data, unsigned size, unsigned flags);
 646
 647     /** Forwards an instruction write. to the appropriate data
 648      *  resource (indexes into Resource Pool thru "dataPortIdx")
 649      */
 650     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 651                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 652
 653     /** Executes a syscall.*/
 654     void syscall(int64_t callnum, ThreadID tid);
 655
 656   public:
 657     /** Per-Thread List of all the instructions in flight. */
 658     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 659
 660     /** List of all the instructions that will be removed at the end of this
 661      *  cycle.
 662      */
 663     std::queue<ListIt> removeList;
 664
 665     /** List of all the cpu event requests that will be removed at the end of
 666      *  the current cycle.
 667      */
 668     std::queue<Event*> cpuEventRemoveList;
 669
 670     /** Records if instructions need to be removed this cycle due to
 671      *  being retired or squashed.
 672      */
 673     bool removeInstsThisCycle;
 674
 675     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 676      * execution unit know, NOT to execute while the instruction is active.
 677      */
 678     bool nonSpecInstActive[ThePipeline::MaxThreads];
 679
 680     /** Instruction Seq. Num of current non-speculative instruction. */
 681     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 682
 683     /** Instruction Seq. Num of last instruction squashed in pipeline */
 684     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 685
 686     /** Last Cycle that the CPU squashed instruction end. */
 687     Tick lastSquashCycle[ThePipeline::MaxThreads];
 688
 689     std::list<ThreadID> fetchPriorityList;
 690
 691   protected:
 692     /** Active Threads List */
 693     std::list<ThreadID> activeThreads;
 694
 695     /** Ready Threads List */
 696     std::list<ThreadID> readyThreads;
 697
 698     /** Suspended Threads List */
 699     std::list<ThreadID> suspendedThreads;
 700
 701     /** Halted Threads List */
 702     std::list<ThreadID> haltedThreads;
 703
 704     /** Thread Status Functions */
 705     bool isThreadActive(ThreadID tid);
 706     bool isThreadReady(ThreadID tid);
 707     bool isThreadSuspended(ThreadID tid);
 708
 709   private:
 710     /** The activity recorder; used to tell if the CPU has any
 711      * activity remaining or if it can go to idle and deschedule
 712      * itself.
 713      */
 714     ActivityRecorder activityRec;
 715
 716   public:
 717     /** Number of Active Threads in the CPU */
 718     ThreadID numActiveThreads() { return activeThreads.size(); }
 719
 720     /** Thread id of active thread
 721      *  Only used for SwitchOnCacheMiss model.
 722      *  Assumes only 1 thread active
 723      */
 724     ThreadID activeThreadId()
 725     {
 726         if (numActiveThreads() > 0)
 727             return activeThreads.front();
 728         else
 729             return InvalidThreadID;
 730     }
 731
 732
 733     /** Records that there was time buffer activity this cycle. */
 734     void activityThisCycle() { activityRec.activity(); }
 735
 736     /** Changes a stage's status to active within the activity recorder. */
 737     void activateStage(const int idx)
 738     { activityRec.activateStage(idx); }
 739
 740     /** Changes a stage's status to inactive within the activity recorder. */
 741     void deactivateStage(const int idx)
 742     { activityRec.deactivateStage(idx); }
 743
 744     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 745     void wakeCPU();
 746
 747 #if FULL_SYSTEM
 748     virtual void wakeup();
 749 #endif
 750
 751     // LL/SC debug functionality
 752     unsigned stCondFails;
 753
 754     unsigned readStCondFailures()
 755     { return stCondFails; }
 756
 757     unsigned setStCondFailures(unsigned st_fails)
 758     { return stCondFails = st_fails; }
 759
 760     /** Returns a pointer to a thread context. */
 761     ThreadContext *tcBase(ThreadID tid = 0)
 762     {
 763         return thread[tid]->getTC();
 764     }
 765
 766     /** Count the Total Instructions Committed in the CPU. */
 767     virtual Counter totalInstructions() const
 768     {
 769         Counter total(0);
 770
 771         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 772             total += thread[tid]->numInst;
 773
 774         return total;
 775     }
 776
 777 #if FULL_SYSTEM
 778     /** Pointer to the system. */
 779     System *system;
 780
 781     /** Pointer to physical memory. */
 782     PhysicalMemory *physmem;
 783 #endif
 784
 785     /** The global sequence number counter. */
 786     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 787
 788 #ifdef DEBUG
 789     /** The global event number counter. */
 790     InstSeqNum cpuEventNum;
 791
 792     /** Number of resource requests active in CPU **/
 793     unsigned resReqCount;
 794 #endif
 795
 796     /** Counter of how many stages have completed switching out. */
 797     int switchCount;
 798
 799     /** Pointers to all of the threads in the CPU. */
 800     std::vector<Thread *> thread;
 801
 802     /** Pointer to the icache interface. */
 803     MemInterface *icacheInterface;
 804
 805     /** Pointer to the dcache interface. */
 806     MemInterface *dcacheInterface;
 807
 808     /** Whether or not the CPU should defer its registration. */
 809     bool deferRegistration;
 810
 811     /** Per-Stage Instruction Tracing */
 812     bool stageTracing;
 813
 814     /** The cycle that the CPU was last running, used for statistics. */
 815     Tick lastRunningCycle;
 816
 817     void updateContextSwitchStats();
 818     unsigned instsPerSwitch;
 819     Stats::Average instsPerCtxtSwitch;
 820     Stats::Scalar numCtxtSwitches;
 821
 822     /** Update Thread , used for statistic purposes*/
 823     inline void tickThreadStats();
 824
 825     /** Per-Thread Tick */
 826     Stats::Vector threadCycles;
 827
 828     /** Tick for SMT */
 829     Stats::Scalar smtCycles;
 830
 831     /** Stat for total number of times the CPU is descheduled. */
 832     Stats::Scalar timesIdled;
 833
 834     /** Stat for total number of cycles the CPU spends descheduled or no
 835      *  stages active.
 836      */
 837     Stats::Scalar idleCycles;
 838
 839     /** Stat for total number of cycles the CPU is active. */
 840     Stats::Scalar runCycles;
 841
 842     /** Percentage of cycles a stage was active */
 843     Stats::Formula activity;
 844
 845     /** Instruction Mix Stats */
 846     Stats::Scalar comLoads;
 847     Stats::Scalar comStores;
 848     Stats::Scalar comBranches;
 849     Stats::Scalar comNops;
 850     Stats::Scalar comNonSpec;
 851     Stats::Scalar comInts;
 852     Stats::Scalar comFloats;
 853
 854     /** Stat for the number of committed instructions per thread. */
 855     Stats::Vector committedInsts;
 856
 857     /** Stat for the number of committed instructions per thread. */
 858     Stats::Vector smtCommittedInsts;
 859
 860     /** Stat for the total number of committed instructions. */
 861     Stats::Scalar totalCommittedInsts;
 862
 863     /** Stat for the CPI per thread. */
 864     Stats::Formula cpi;
 865
 866     /** Stat for the SMT-CPI per thread. */
 867     Stats::Formula smtCpi;
 868
 869     /** Stat for the total CPI. */
 870     Stats::Formula totalCpi;
 871
 872     /** Stat for the IPC per thread. */
 873     Stats::Formula ipc;
 874
 875     /** Stat for the total IPC. */
 876     Stats::Formula smtIpc;
 877
 878     /** Stat for the total IPC. */
 879     Stats::Formula totalIpc;
 880 };
 881
 882 #endif // __CPU_O3_CPU_HH__