2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_CPU_HH__
33 #define __CPU_INORDER_CPU_HH__
41 #include "arch/isa_traits.hh"
42 #include "base/statistics.hh"
43 #include "base/timebuf.hh"
44 #include "config/full_system.hh"
45 #include "cpu/activity.hh"
46 #include "cpu/base.hh"
47 #include "cpu/simple_thread.hh"
48 #include "cpu/inorder/inorder_dyn_inst.hh"
49 #include "cpu/inorder/pipeline_traits.hh"
50 #include "cpu/inorder/pipeline_stage.hh"
51 #include "cpu/inorder/thread_state.hh"
52 #include "cpu/inorder/reg_dep_map.hh"
53 #include "cpu/o3/dep_graph.hh"
54 #include "cpu/o3/rename_map.hh"
55 #include "mem/packet.hh"
56 #include "mem/port.hh"
57 #include "mem/request.hh"
58 #include "sim/eventq.hh"
59 #include "sim/process.hh"
67 class InOrderCPU : public BaseCPU
71 typedef ThePipeline::Params Params;
72 typedef InOrderThreadState Thread;
75 typedef TheISA::IntReg IntReg;
76 typedef TheISA::FloatReg FloatReg;
77 typedef TheISA::FloatRegBits FloatRegBits;
78 typedef TheISA::MiscReg MiscReg;
79 typedef TheISA::RegFile RegFile;
82 typedef ThePipeline::DynInstPtr DynInstPtr;
83 typedef std::list<DynInstPtr>::iterator ListIt;
86 typedef TimeBuffer<InterStageStruct> StageQueue;
88 friend class Resource;
91 /** Constructs a CPU with the given parameters. */
92 InOrderCPU(Params *params);
97 /** Type of core that this is */
100 int readCpuId() { return cpu_id; }
102 void setCpuId(int val) { cpu_id = val; }
115 /** Overall CPU status. */
119 /** Define TickEvent for the CPU */
120 class TickEvent : public Event
123 /** Pointer to the CPU. */
127 /** Constructs a tick event. */
128 TickEvent(InOrderCPU *c);
130 /** Processes a tick event, calling tick() on the CPU. */
133 /** Returns the description of the tick event. */
134 const char *description();
137 /** The tick event used for scheduling CPU ticks. */
140 /** Schedule tick event, regardless of its current state. */
141 void scheduleTickEvent(int delay)
143 if (tickEvent.squashed())
144 mainEventQueue.reschedule(&tickEvent, nextCycle(curTick + ticks(delay)));
145 else if (!tickEvent.scheduled())
146 mainEventQueue.schedule(&tickEvent, nextCycle(curTick + ticks(delay)));
149 /** Unschedule tick event, regardless of its current state. */
150 void unscheduleTickEvent()
152 if (tickEvent.scheduled())
157 // List of Events That can be scheduled from
159 // NOTE(1): The Resource Pool also uses this event list
160 // to schedule events broadcast to all resources interfaces
161 // NOTE(2): CPU Events usually need to schedule a corresponding resource
178 static std::string eventNames[NumCPUEvents];
180 /** Define CPU Event */
181 class CPUEvent : public Event
187 CPUEventType cpuEventType;
193 /** Constructs a CPU event. */
194 CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
195 unsigned _tid, unsigned _vpe);
197 /** Set Type of Event To Be Scheduled */
198 void setEvent(CPUEventType e_type, Fault _fault, unsigned _tid, unsigned _vpe)
201 cpuEventType = e_type;
206 /** Processes a resource event. */
207 virtual void process();
209 /** Returns the description of the resource event. */
210 const char *description();
212 /** Schedule Event */
213 void scheduleEvent(int delay);
215 /** Unschedule This Event */
216 void unscheduleEvent();
219 /** Schedule a CPU Event */
220 void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, unsigned tid,
221 unsigned vpe, unsigned delay = 0);
224 /** Interface between the CPU and CPU resources. */
225 ResourcePool *resPool;
227 /** Instruction used to signify that there is no *real* instruction in buffer slot */
228 DynInstPtr dummyBufferInst;
230 /** Used by resources to signify a denied access to a resource. */
231 ResourceRequest *dummyReq;
233 /** Identifies the resource id that identifies a fetch
236 unsigned fetchPortIdx;
238 /** Identifies the resource id that identifies a ITB */
241 /** Identifies the resource id that identifies a data
244 unsigned dataPortIdx;
246 /** Identifies the resource id that identifies a DTB */
249 /** The Pipeline Stages for the CPU */
250 PipelineStage *pipelineStage[ThePipeline::NumStages];
252 /** Program Counters */
253 TheISA::IntReg PC[ThePipeline::MaxThreads];
254 TheISA::IntReg nextPC[ThePipeline::MaxThreads];
255 TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
257 /** The Register File for the CPU */
258 TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];;
259 TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];;
260 TheISA::MiscRegFile miscRegFile;
262 /** Dependency Tracker for Integer & Floating Point Regs */
263 RegDepMap archRegDepMap[ThePipeline::MaxThreads];
265 /** Global communication structure */
266 TimeBuffer<TimeStruct> timeBuffer;
268 /** Communication structure that sits in between pipeline stages */
269 StageQueue *stageQueue[ThePipeline::NumStages-1];
271 TheISA::TLB *getITBPtr();
272 TheISA::TLB *getDTBPtr();
276 /** Registers statistics. */
279 /** Ticks CPU, calling tick() on each stage, and checking the overall
280 * activity to see if the CPU should deschedule itself.
284 /** Initialize the CPU */
287 /** Reset State in the CPU */
290 /** Get a Memory Port */
291 Port* getPort(const std::string &if_name, int idx = 0);
293 /** trap() - sets up a trap event on the cpuTraps to handle given fault.
294 * trapCPU() - Traps to handle given fault
296 void trap(Fault fault, unsigned tid, int delay = 0);
297 void trapCPU(Fault fault, unsigned tid);
299 /** Setup CPU to insert a thread's context */
300 void insertThread(unsigned tid);
302 /** Remove all of a thread's context from CPU */
303 void removeThread(unsigned tid);
305 /** Add Thread to Active Threads List. */
306 void activateContext(unsigned tid, int delay = 0);
307 void activateThread(unsigned tid);
309 /** Remove Thread from Active Threads List */
310 void suspendContext(unsigned tid, int delay = 0);
311 void suspendThread(unsigned tid);
313 /** Remove Thread from Active Threads List &&
314 * Remove Thread Context from CPU.
316 void deallocateContext(unsigned tid, int delay = 0);
317 void deallocateThread(unsigned tid);
318 void deactivateThread(unsigned tid);
320 PipelineStage* getPipeStage(int stage_num);
325 hack_once("return a bogus context id");
329 /** Remove Thread from Active Threads List &&
330 * Remove Thread Context from CPU.
332 void haltContext(unsigned tid, int delay = 0);
334 void removePipelineStalls(unsigned tid);
336 void squashThreadInPipeline(unsigned tid);
338 /// Notify the CPU to enable a virtual processor element.
339 virtual void enableVirtProcElement(unsigned vpe);
340 void enableVPEs(unsigned vpe);
342 /// Notify the CPU to disable a virtual processor element.
343 virtual void disableVirtProcElement(unsigned tid, unsigned vpe);
344 void disableVPEs(unsigned tid, unsigned vpe);
346 /// Notify the CPU that multithreading is enabled.
347 virtual void enableMultiThreading(unsigned vpe);
348 void enableThreads(unsigned vpe);
350 /// Notify the CPU that multithreading is disabled.
351 virtual void disableMultiThreading(unsigned tid, unsigned vpe);
352 void disableThreads(unsigned tid, unsigned vpe);
354 /** Activate a Thread When CPU Resources are Available. */
355 void activateWhenReady(int tid);
357 /** Add or Remove a Thread Context in the CPU. */
358 void doContextSwitch();
360 /** Update The Order In Which We Process Threads. */
361 void updateThreadPriority();
363 /** Switches a Pipeline Stage to Active. (Unused currently) */
364 void switchToActive(int stage_idx)
365 { /*pipelineStage[stage_idx]->switchToActive();*/ }
367 /** Get the current instruction sequence number, and increment it. */
368 InstSeqNum getAndIncrementInstSeq(unsigned tid)
369 { return globalSeqNum[tid]++; }
371 /** Get the current instruction sequence number, and increment it. */
372 InstSeqNum nextInstSeqNum(unsigned tid)
373 { return globalSeqNum[tid]; }
375 /** Increment Instruction Sequence Number */
376 void incrInstSeqNum(unsigned tid)
377 { globalSeqNum[tid]++; }
379 /** Set Instruction Sequence Number */
380 void setInstSeqNum(unsigned tid, InstSeqNum seq_num)
382 globalSeqNum[tid] = seq_num;
385 /** Get & Update Next Event Number */
386 InstSeqNum getNextEventNum()
388 return cpuEventNum++;
391 /** Get instruction asid. */
392 int getInstAsid(unsigned tid)
393 { return thread[tid]->getInstAsid(); }
395 /** Get data asid. */
396 int getDataAsid(unsigned tid)
397 { return thread[tid]->getDataAsid(); }
399 /** Register file accessors */
400 uint64_t readIntReg(int reg_idx, unsigned tid);
402 FloatReg readFloatReg(int reg_idx, unsigned tid,
403 int width = TheISA::SingleWidth);
405 FloatRegBits readFloatRegBits(int reg_idx, unsigned tid,
406 int width = TheISA::SingleWidth);
408 void setIntReg(int reg_idx, uint64_t val, unsigned tid);
410 void setFloatReg(int reg_idx, FloatReg val, unsigned tid,
411 int width = TheISA::SingleWidth);
413 void setFloatRegBits(int reg_idx, FloatRegBits val, unsigned tid,
414 int width = TheISA::SingleWidth);
416 /** Reads a miscellaneous register. */
417 MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0);
419 /** Reads a misc. register, including any side effects the read
420 * might have as defined by the architecture.
422 MiscReg readMiscReg(int misc_reg, unsigned tid = 0);
424 /** Sets a miscellaneous register. */
425 void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0);
427 /** Sets a misc. register, including any side effects the write
428 * might have as defined by the architecture.
430 void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0);
432 /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
435 uint64_t readRegOtherThread(unsigned misc_reg, unsigned tid = -1);
437 /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
440 void setRegOtherThread(unsigned misc_reg, const MiscReg &val, unsigned tid);
442 /** Reads the commit PC of a specific thread. */
443 uint64_t readPC(unsigned tid);
445 /** Sets the commit PC of a specific thread. */
446 void setPC(Addr new_PC, unsigned tid);
448 /** Reads the next PC of a specific thread. */
449 uint64_t readNextPC(unsigned tid);
451 /** Sets the next PC of a specific thread. */
452 void setNextPC(uint64_t val, unsigned tid);
454 /** Reads the next NPC of a specific thread. */
455 uint64_t readNextNPC(unsigned tid);
457 /** Sets the next NPC of a specific thread. */
458 void setNextNPC(uint64_t val, unsigned tid);
460 /** Function to add instruction onto the head of the list of the
461 * instructions. Used when new instructions are fetched.
463 ListIt addInst(DynInstPtr &inst);
465 /** Function to tell the CPU that an instruction has completed. */
466 void instDone(DynInstPtr inst, unsigned tid);
468 /** Add Instructions to the CPU Remove List*/
469 void addToRemoveList(DynInstPtr &inst);
471 /** Remove an instruction from CPU */
472 void removeInst(DynInstPtr &inst);
474 /** Remove all instructions younger than the given sequence number. */
475 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
477 /** Removes the instruction pointed to by the iterator. */
478 inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
480 /** Cleans up all instructions on the instruction remove list. */
481 void cleanUpRemovedInsts();
483 /** Cleans up all instructions on the request remove list. */
484 void cleanUpRemovedReqs();
486 /** Cleans up all instructions on the CPU event remove list. */
487 void cleanUpRemovedEvents();
489 /** Debug function to print all instructions on the list. */
492 /** Forwards an instruction read to the appropriate data
493 * resource (indexes into Resource Pool thru "dataPortIdx")
495 Fault read(DynInstPtr inst);
497 /** Forwards an instruction write. to the appropriate data
498 * resource (indexes into Resource Pool thru "dataPortIdx")
500 Fault write(DynInstPtr inst, uint64_t *res = NULL);
502 /** Forwards an instruction prefetch to the appropriate data
503 * resource (indexes into Resource Pool thru "dataPortIdx")
505 void prefetch(DynInstPtr inst);
507 /** Forwards an instruction writeHint to the appropriate data
508 * resource (indexes into Resource Pool thru "dataPortIdx")
510 void writeHint(DynInstPtr inst);
512 /** Executes a syscall.*/
513 void syscall(int64_t callnum, int tid);
516 /** Per-Thread List of all the instructions in flight. */
517 std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
519 /** List of all the instructions that will be removed at the end of this
522 std::queue<ListIt> removeList;
524 /** List of all the resource requests that will be removed at the end of this
527 std::queue<ResourceRequest*> reqRemoveList;
529 /** List of all the cpu event requests that will be removed at the end of
532 std::queue<Event*> cpuEventRemoveList;
534 /** Records if instructions need to be removed this cycle due to
535 * being retired or squashed.
537 bool removeInstsThisCycle;
539 /** True if there is non-speculative Inst Active In Pipeline. Lets any
540 * execution unit know, NOT to execute while the instruction is active.
542 bool nonSpecInstActive[ThePipeline::MaxThreads];
544 /** Instruction Seq. Num of current non-speculative instruction. */
545 InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
547 /** Instruction Seq. Num of last instruction squashed in pipeline */
548 InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
550 /** Last Cycle that the CPU squashed instruction end. */
551 Tick lastSquashCycle[ThePipeline::MaxThreads];
553 std::list<unsigned> fetchPriorityList;
556 /** Active Threads List */
557 std::list<unsigned> activeThreads;
559 /** Current Threads List */
560 std::list<unsigned> currentThreads;
562 /** Suspended Threads List */
563 std::list<unsigned> suspendedThreads;
565 /** Thread Status Functions (Unused Currently) */
566 bool isThreadInCPU(unsigned tid);
567 bool isThreadActive(unsigned tid);
568 bool isThreadSuspended(unsigned tid);
569 void addToCurrentThreads(unsigned tid);
570 void removeFromCurrentThreads(unsigned tid);
573 /** The activity recorder; used to tell if the CPU has any
574 * activity remaining or if it can go to idle and deschedule
577 ActivityRecorder activityRec;
580 void readFunctional(Addr addr, uint32_t &buffer);
582 /** Number of Active Threads in the CPU */
583 int numActiveThreads() { return activeThreads.size(); }
585 /** Records that there was time buffer activity this cycle. */
586 void activityThisCycle() { activityRec.activity(); }
588 /** Changes a stage's status to active within the activity recorder. */
589 void activateStage(const int idx)
590 { activityRec.activateStage(idx); }
592 /** Changes a stage's status to inactive within the activity recorder. */
593 void deactivateStage(const int idx)
594 { activityRec.deactivateStage(idx); }
596 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
599 /** Gets a free thread id. Use if thread ids change across system. */
602 // LL/SC debug functionality
603 unsigned stCondFails;
604 unsigned readStCondFailures() { return stCondFails; }
605 unsigned setStCondFailures(unsigned st_fails) { return stCondFails = st_fails; }
607 /** Returns a pointer to a thread context. */
608 ThreadContext *tcBase(unsigned tid = 0)
610 return thread[tid]->getTC();
613 /** Count the Total Instructions Committed in the CPU. */
614 virtual Counter totalInstructions() const
618 for (int i=0; i < thread.size(); i++)
619 total += thread[i]->numInst;
624 /** The global sequence number counter. */
625 InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
627 /** The global event number counter. */
628 InstSeqNum cpuEventNum;
630 /** Counter of how many stages have completed switching out. */
633 /** Pointers to all of the threads in the CPU. */
634 std::vector<Thread *> thread;
636 /** Pointer to the icache interface. */
637 MemInterface *icacheInterface;
639 /** Pointer to the dcache interface. */
640 MemInterface *dcacheInterface;
642 /** Whether or not the CPU should defer its registration. */
643 bool deferRegistration;
645 /** Per-Stage Instruction Tracing */
648 /** Is there a context switch pending? */
651 /** Threads Scheduled to Enter CPU */
652 std::list<int> cpuWaitList;
654 /** The cycle that the CPU was last running, used for statistics. */
655 Tick lastRunningCycle;
657 /** Number of Threads the CPU can process */
660 /** Number of Virtual Processors the CPU can process */
661 unsigned numVirtProcs;
663 /** Update Thread , used for statistic purposes*/
664 inline void tickThreadStats();
666 /** Per-Thread Tick */
667 Stats::Vector threadCycles;
670 Stats::Scalar smtCycles;
672 /** Stat for total number of times the CPU is descheduled. */
673 Stats::Scalar timesIdled;
675 /** Stat for total number of cycles the CPU spends descheduled. */
676 Stats::Scalar idleCycles;
678 /** Stat for the number of committed instructions per thread. */
679 Stats::Vector committedInsts;
681 /** Stat for the number of committed instructions per thread. */
682 Stats::Vector smtCommittedInsts;
684 /** Stat for the total number of committed instructions. */
685 Stats::Scalar totalCommittedInsts;
687 /** Stat for the CPI per thread. */
690 /** Stat for the SMT-CPI per thread. */
691 Stats::Formula smtCpi;
693 /** Stat for the total CPI. */
694 Stats::Formula totalCpi;
696 /** Stat for the IPC per thread. */
699 /** Stat for the total IPC. */
700 Stats::Formula smtIpc;
702 /** Stat for the total IPC. */
703 Stats::Formula totalIpc;
706 #endif // __CPU_O3_CPU_HH__