src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2012-2013 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2007 MIPS Technologies, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Korey Sewell
  42  *
  43  */
  44
  45 #ifndef __CPU_INORDER_CPU_HH__
  46 #define __CPU_INORDER_CPU_HH__
  47
  48 #include <iostream>
  49 #include <list>
  50 #include <queue>
  51 #include <set>
  52 #include <vector>
  53
  54 #include "arch/isa_traits.hh"
  55 #include "arch/registers.hh"
  56 #include "arch/types.hh"
  57 #include "base/statistics.hh"
  58 #include "base/types.hh"
  59 #include "config/the_isa.hh"
  60 #include "cpu/inorder/inorder_dyn_inst.hh"
  61 #include "cpu/inorder/pipeline_stage.hh"
  62 #include "cpu/inorder/pipeline_traits.hh"
  63 #include "cpu/inorder/reg_dep_map.hh"
  64 #include "cpu/inorder/thread_state.hh"
  65 #include "cpu/o3/dep_graph.hh"
  66 #include "cpu/o3/rename_map.hh"
  67 #include "cpu/activity.hh"
  68 #include "cpu/base.hh"
  69 #include "cpu/reg_class.hh"
  70 #include "cpu/simple_thread.hh"
  71 #include "cpu/timebuf.hh"
  72 #include "mem/packet.hh"
  73 #include "mem/port.hh"
  74 #include "mem/request.hh"
  75 #include "sim/eventq.hh"
  76 #include "sim/process.hh"
  77
  78 class CacheUnit;
  79 class ThreadContext;
  80 class MemInterface;
  81 class MemObject;
  82 class Process;
  83 class ResourcePool;
  84
  85 class InOrderCPU : public BaseCPU
  86 {
  87
  88   protected:
  89     typedef ThePipeline::Params Params;
  90     typedef InOrderThreadState Thread;
  91
  92    //ISA TypeDefs
  93     typedef TheISA::IntReg IntReg;
  94     typedef TheISA::FloatReg FloatReg;
  95     typedef TheISA::FloatRegBits FloatRegBits;
  96     typedef TheISA::MiscReg MiscReg;
  97     typedef TheISA::RegIndex RegIndex;
  98
  99     //DynInstPtr TypeDefs
 100     typedef ThePipeline::DynInstPtr DynInstPtr;
 101     typedef std::list<DynInstPtr>::iterator ListIt;
 102
 103     //TimeBuffer TypeDefs
 104     typedef TimeBuffer<InterStageStruct> StageQueue;
 105
 106     friend class Resource;
 107
 108   public:
 109     /** Constructs a CPU with the given parameters. */
 110     InOrderCPU(Params *params);
 111     /* Destructor */
 112     ~InOrderCPU();
 113
 114     void verifyMemoryMode() const;
 115
 116     /** Return a reference to the data port. */
 117     virtual MasterPort &getDataPort() { return dataPort; }
 118
 119     /** Return a reference to the instruction port. */
 120     virtual MasterPort &getInstPort() { return instPort; }
 121
 122     /** CPU ID */
 123     int cpu_id;
 124
 125     // SE Mode ASIDs
 126     ThreadID asid[ThePipeline::MaxThreads];
 127
 128     /** Type of core that this is */
 129     std::string coreType;
 130
 131     // Only need for SE MODE
 132     enum ThreadModel {
 133         Single,
 134         SMT,
 135         SwitchOnCacheMiss
 136     };
 137
 138     ThreadModel threadModel;
 139
 140     int readCpuId() { return cpu_id; }
 141
 142     void setCpuId(int val) { cpu_id = val; }
 143
 144     Params *cpu_params;
 145
 146   public:
 147     enum Status {
 148         Running,
 149         Idle,
 150         Halted,
 151         Blocked,
 152         SwitchedOut
 153     };
 154
 155     /** Overall CPU status. */
 156     Status _status;
 157   private:
 158
 159     /**
 160      * CachePort class for the in-order CPU, interacting with a
 161      * specific CacheUnit in the pipeline.
 162      */
 163     class CachePort : public MasterPort
 164     {
 165
 166       private:
 167         /** Pointer to cache unit */
 168         CacheUnit *cacheUnit;
 169
 170       public:
 171         /** Default constructor. */
 172         CachePort(CacheUnit *_cacheUnit, const std::string& name);
 173
 174       protected:
 175
 176         /** Timing version of receive */
 177         bool recvTimingResp(PacketPtr pkt);
 178
 179         /** Handles doing a retry of a failed timing request. */
 180         void recvRetry();
 181
 182         /** Ignoring snoops for now. */
 183         void recvTimingSnoopReq(PacketPtr pkt) { }
 184     };
 185
 186     /** Define TickEvent for the CPU */
 187     class TickEvent : public Event
 188     {
 189       private:
 190         /** Pointer to the CPU. */
 191         InOrderCPU *cpu;
 192
 193       public:
 194         /** Constructs a tick event. */
 195         TickEvent(InOrderCPU *c);
 196
 197         /** Processes a tick event, calling tick() on the CPU. */
 198         void process();
 199
 200         /** Returns the description of the tick event. */
 201         const char *description() const;
 202     };
 203
 204     /** The tick event used for scheduling CPU ticks. */
 205     TickEvent tickEvent;
 206
 207     /** Schedule tick event, regardless of its current state. */
 208     void scheduleTickEvent(Cycles delay)
 209     {
 210         assert(!tickEvent.scheduled() || tickEvent.squashed());
 211         reschedule(&tickEvent, clockEdge(delay), true);
 212     }
 213
 214     /** Unschedule tick event, regardless of its current state. */
 215     void unscheduleTickEvent()
 216     {
 217         if (tickEvent.scheduled())
 218             tickEvent.squash();
 219     }
 220
 221   public:
 222     // List of Events That can be scheduled from
 223     // within the CPU.
 224     // NOTE(1): The Resource Pool also uses this event list
 225     // to schedule events broadcast to all resources interfaces
 226     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 227     // pool event.
 228     enum CPUEventType {
 229         ActivateThread,
 230         ActivateNextReadyThread,
 231         DeactivateThread,
 232         HaltThread,
 233         SuspendThread,
 234         Trap,
 235         Syscall,
 236         SquashFromMemStall,
 237         UpdatePCs,
 238         NumCPUEvents
 239     };
 240
 241     static std::string eventNames[NumCPUEvents];
 242
 243     enum CPUEventPri {
 244         InOrderCPU_Pri                 = Event::CPU_Tick_Pri,
 245         Syscall_Pri                    = Event::CPU_Tick_Pri + 9,
 246         ActivateNextReadyThread_Pri    = Event::CPU_Tick_Pri + 10
 247     };
 248
 249     /** Define CPU Event */
 250     class CPUEvent : public Event
 251     {
 252       protected:
 253         InOrderCPU *cpu;
 254
 255       public:
 256         CPUEventType cpuEventType;
 257         ThreadID tid;
 258         DynInstPtr inst;
 259         Fault fault;
 260         unsigned vpe;
 261         short syscall_num;
 262
 263       public:
 264         /** Constructs a CPU event. */
 265         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 266                  ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
 267
 268         /** Set Type of Event To Be Scheduled */
 269         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 270                       DynInstPtr _inst)
 271         {
 272             fault = _fault;
 273             cpuEventType = e_type;
 274             tid = _tid;
 275             inst = _inst;
 276             vpe = 0;
 277         }
 278
 279         /** Processes a CPU event. */
 280         void process();
 281
 282         /** Returns the description of the CPU event. */
 283         const char *description() const;
 284
 285         /** Schedule Event */
 286         void scheduleEvent(Cycles delay);
 287
 288         /** Unschedule This Event */
 289         void unscheduleEvent();
 290     };
 291
 292     /** Schedule a CPU Event */
 293     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 294                           DynInstPtr inst, Cycles delay = Cycles(0),
 295                           CPUEventPri event_pri = InOrderCPU_Pri);
 296
 297   public:
 298
 299     /** Width (processing bandwidth) of each stage */
 300     int stageWidth;
 301
 302     /** Interface between the CPU and CPU resources. */
 303     ResourcePool *resPool;
 304
 305     /** Instruction used to signify that there is no *real* instruction in
 306         buffer slot */
 307     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 308     DynInstPtr dummyBufferInst;
 309     DynInstPtr dummyReqInst;
 310     DynInstPtr dummyTrapInst[ThePipeline::MaxThreads];
 311
 312     /** Used by resources to signify a denied access to a resource. */
 313     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 314
 315     /** The Pipeline Stages for the CPU */
 316     PipelineStage *pipelineStage[ThePipeline::NumStages];
 317
 318     /** Program Counters */
 319     TheISA::PCState pc[ThePipeline::MaxThreads];
 320
 321     /** Last Committed PC */
 322     TheISA::PCState lastCommittedPC[ThePipeline::MaxThreads];
 323
 324     /** The Register File for the CPU */
 325     union {
 326         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 327         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 328     } floatRegs;
 329     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 330
 331     /** ISA state */
 332     std::vector<TheISA::ISA *> isa;
 333
 334     /** Dependency Tracker for Integer & Floating Point Regs */
 335     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 336
 337     /** Global communication structure */
 338     TimeBuffer<TimeStruct> timeBuffer;
 339
 340     /** Communication structure that sits in between pipeline stages */
 341     StageQueue *stageQueue[ThePipeline::NumStages-1];
 342
 343     TheISA::TLB *getITBPtr();
 344     TheISA::TLB *getDTBPtr();
 345
 346     TheISA::Decoder *getDecoderPtr(unsigned tid);
 347
 348     /** Accessor Type for the SkedCache */
 349     typedef uint32_t SkedID;
 350
 351     /** Cache of Instruction Schedule using the instruction's name as a key */
 352     static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
 353
 354     typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 355
 356     /** Initialized to last iterator in map, signifying a invalid entry
 357         on map searches
 358     */
 359     SkedCacheIt endOfSkedIt;
 360
 361     ThePipeline::RSkedPtr frontEndSked;
 362     ThePipeline::RSkedPtr faultSked;
 363
 364     /** Add a new instruction schedule to the schedule cache */
 365     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 366     {
 367         SkedID sked_id = genSkedID(inst);
 368         assert(skedCache.find(sked_id) == skedCache.end());
 369         skedCache[sked_id] = inst_sked;
 370     }
 371
 372
 373     /** Find a instruction schedule */
 374     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 375     {
 376         SkedID sked_id = genSkedID(inst);
 377         SkedCacheIt lookup_it = skedCache.find(sked_id);
 378
 379         if (lookup_it != endOfSkedIt) {
 380             return (*lookup_it).second;
 381         } else {
 382             return NULL;
 383         }
 384     }
 385
 386     static const uint8_t INST_OPCLASS                       = 26;
 387     static const uint8_t INST_LOAD                          = 25;
 388     static const uint8_t INST_STORE                         = 24;
 389     static const uint8_t INST_CONTROL                       = 23;
 390     static const uint8_t INST_NONSPEC                       = 22;
 391     static const uint8_t INST_DEST_REGS                     = 18;
 392     static const uint8_t INST_SRC_REGS                      = 14;
 393     static const uint8_t INST_SPLIT_DATA                    = 13;
 394
 395     inline SkedID genSkedID(DynInstPtr inst)
 396     {
 397         SkedID id = 0;
 398         id = (inst->opClass() << INST_OPCLASS) |
 399             (inst->isLoad() << INST_LOAD) |
 400             (inst->isStore() << INST_STORE) |
 401             (inst->isControl() << INST_CONTROL) |
 402             (inst->isNonSpeculative() << INST_NONSPEC) |
 403             (inst->numDestRegs() << INST_DEST_REGS) |
 404             (inst->numSrcRegs() << INST_SRC_REGS) |
 405             (inst->splitInst << INST_SPLIT_DATA);
 406         return id;
 407     }
 408
 409     ThePipeline::RSkedPtr createFrontEndSked();
 410     ThePipeline::RSkedPtr createFaultSked();
 411     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 412
 413     class StageScheduler {
 414       private:
 415         ThePipeline::RSkedPtr rsked;
 416         int stageNum;
 417         int nextTaskPriority;
 418
 419       public:
 420         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 421             : rsked(_rsked), stageNum(stage_num),
 422               nextTaskPriority(0)
 423         { }
 424
 425         void needs(int unit, int request) {
 426             rsked->push(new ScheduleEntry(
 427                             stageNum, nextTaskPriority++, unit, request
 428                             ));
 429         }
 430
 431         void needs(int unit, int request, int param) {
 432             rsked->push(new ScheduleEntry(
 433                             stageNum, nextTaskPriority++, unit, request, param
 434                             ));
 435         }
 436     };
 437
 438   private:
 439
 440     /** Data port. Note that it has to appear after the resPool. */
 441     CachePort dataPort;
 442
 443     /** Instruction port. Note that it has to appear after the resPool. */
 444     CachePort instPort;
 445
 446   public:
 447
 448     /** Registers statistics. */
 449     void regStats();
 450
 451     /** Ticks CPU, calling tick() on each stage, and checking the overall
 452      *  activity to see if the CPU should deschedule itself.
 453      */
 454     void tick();
 455
 456     /** Initialize the CPU */
 457     void init();
 458
 459     /** HW return from error interrupt. */
 460     Fault hwrei(ThreadID tid);
 461
 462     bool simPalCheck(int palFunc, ThreadID tid);
 463
 464     void checkForInterrupts();
 465
 466     /** Returns the Fault for any valid interrupt. */
 467     Fault getInterrupts();
 468
 469     /** Processes any an interrupt fault. */
 470     void processInterrupts(Fault interrupt);
 471
 472     /** Halts the CPU. */
 473     void halt() { panic("Halt not implemented!\n"); }
 474
 475     /** Check if this address is a valid instruction address. */
 476     bool validInstAddr(Addr addr) { return true; }
 477
 478     /** Check if this address is a valid data address. */
 479     bool validDataAddr(Addr addr) { return true; }
 480
 481     /** Schedule a syscall on the CPU */
 482     void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
 483                         Cycles delay = Cycles(0));
 484
 485     /** Executes a syscall.*/
 486     void syscall(int64_t callnum, ThreadID tid);
 487
 488     /** Schedule a trap on the CPU */
 489     void trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
 490                      Cycles delay = Cycles(0));
 491
 492     /** Perform trap to Handle Given Fault */
 493     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 494
 495     /** Schedule thread activation on the CPU */
 496     void activateContext(ThreadID tid, Cycles delay = Cycles(0));
 497
 498     /** Add Thread to Active Threads List. */
 499     void activateThread(ThreadID tid);
 500
 501     /** Activate Thread In Each Pipeline Stage */
 502     void activateThreadInPipeline(ThreadID tid);
 503
 504     /** Schedule Thread Activation from Ready List */
 505     void activateNextReadyContext(Cycles delay = Cycles(0));
 506
 507     /** Add Thread From Ready List to Active Threads List. */
 508     void activateNextReadyThread();
 509
 510     /** Schedule a thread deactivation on the CPU */
 511     void deactivateContext(ThreadID tid, Cycles delay = Cycles(0));
 512
 513     /** Remove from Active Thread List */
 514     void deactivateThread(ThreadID tid);
 515
 516     /** Schedule a thread suspension on the CPU */
 517   void suspendContext(ThreadID tid);
 518
 519     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 520     void suspendThread(ThreadID tid);
 521
 522     /** Schedule a thread halt on the CPU */
 523     void haltContext(ThreadID tid);
 524
 525     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 526      *  Threads List
 527      */
 528     void haltThread(ThreadID tid);
 529
 530     /** squashFromMemStall() - sets up a squash event
 531      *  squashDueToMemStall() - squashes pipeline
 532      *  @note: maybe squashContext/squashThread would be better?
 533      */
 534     void squashFromMemStall(DynInstPtr inst, ThreadID tid,
 535                             Cycles delay = Cycles(0));
 536     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 537
 538     void removePipelineStalls(ThreadID tid);
 539     void squashThreadInPipeline(ThreadID tid);
 540     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 541
 542     PipelineStage* getPipeStage(int stage_num);
 543
 544     int
 545     contextId()
 546     {
 547         hack_once("return a bogus context id");
 548         return 0;
 549     }
 550
 551     /** Update The Order In Which We Process Threads. */
 552     void updateThreadPriority();
 553
 554     /** Switches a Pipeline Stage to Active. (Unused currently) */
 555     void switchToActive(int stage_idx)
 556     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 557
 558     /** Get the current instruction sequence number, and increment it. */
 559     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 560     { return globalSeqNum[tid]++; }
 561
 562     /** Get the current instruction sequence number, and increment it. */
 563     InstSeqNum nextInstSeqNum(ThreadID tid)
 564     { return globalSeqNum[tid]; }
 565
 566     /** Increment Instruction Sequence Number */
 567     void incrInstSeqNum(ThreadID tid)
 568     { globalSeqNum[tid]++; }
 569
 570     /** Set Instruction Sequence Number */
 571     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 572     {
 573         globalSeqNum[tid] = seq_num;
 574     }
 575
 576     /** Get & Update Next Event Number */
 577     InstSeqNum getNextEventNum()
 578     {
 579 #ifdef DEBUG
 580         return cpuEventNum++;
 581 #else
 582         return 0;
 583 #endif
 584     }
 585
 586     /** Register file accessors  */
 587     uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
 588
 589     FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
 590
 591     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 592
 593     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 594
 595     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 596
 597     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 598
 599     RegIndex flattenRegIdx(RegIndex reg_idx, RegClass &reg_type, ThreadID tid);
 600
 601     /** Reads a miscellaneous register. */
 602     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 603
 604     /** Reads a misc. register, including any side effects the read
 605      * might have as defined by the architecture.
 606      */
 607     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 608
 609     /** Sets a miscellaneous register. */
 610     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 611                             ThreadID tid = 0);
 612
 613     /** Sets a misc. register, including any side effects the write
 614      * might have as defined by the architecture.
 615      */
 616     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 617
 618     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 619      *  target thread
 620      */
 621     uint64_t readRegOtherThread(unsigned misc_reg,
 622                                 ThreadID tid = InvalidThreadID);
 623
 624     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 625      * target thread
 626      */
 627     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 628                            ThreadID tid);
 629
 630     /** Reads the commit PC of a specific thread. */
 631     TheISA::PCState
 632     pcState(ThreadID tid)
 633     {
 634         return pc[tid];
 635     }
 636
 637     /** Sets the commit PC of a specific thread. */
 638     void
 639     pcState(const TheISA::PCState &newPC, ThreadID tid)
 640     {
 641         pc[tid] = newPC;
 642     }
 643
 644     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 645     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 646     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 647
 648     /** Function to add instruction onto the head of the list of the
 649      *  instructions.  Used when new instructions are fetched.
 650      */
 651     ListIt addInst(DynInstPtr inst);
 652
 653     /** Find instruction on instruction list */
 654     ListIt findInst(InstSeqNum seq_num, ThreadID tid);
 655
 656     /** Function to tell the CPU that an instruction has completed. */
 657     void instDone(DynInstPtr inst, ThreadID tid);
 658
 659     /** Add Instructions to the CPU Remove List*/
 660     void addToRemoveList(DynInstPtr inst);
 661
 662     /** Remove an instruction from CPU */
 663     void removeInst(DynInstPtr inst);
 664
 665     /** Remove all instructions younger than the given sequence number. */
 666     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 667
 668     /** Removes the instruction pointed to by the iterator. */
 669     inline void squashInstIt(const ListIt inst_it, ThreadID tid);
 670
 671     /** Cleans up all instructions on the instruction remove list. */
 672     void cleanUpRemovedInsts();
 673
 674     /** Cleans up all events on the CPU event remove list. */
 675     void cleanUpRemovedEvents();
 676
 677     /** Debug function to print all instructions on the list. */
 678     void dumpInsts();
 679
 680     /** Forwards an instruction read to the appropriate data
 681      *  resource (indexes into Resource Pool thru "dataPortIdx")
 682      */
 683     Fault read(DynInstPtr inst, Addr addr,
 684                uint8_t *data, unsigned size, unsigned flags);
 685
 686     /** Forwards an instruction write. to the appropriate data
 687      *  resource (indexes into Resource Pool thru "dataPortIdx")
 688      */
 689     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 690                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 691
 692   public:
 693     /** Per-Thread List of all the instructions in flight. */
 694     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 695
 696     /** List of all the instructions that will be removed at the end of this
 697      *  cycle.
 698      */
 699     std::queue<ListIt> removeList;
 700
 701     bool trapPending[ThePipeline::MaxThreads];
 702
 703     /** List of all the cpu event requests that will be removed at the end of
 704      *  the current cycle.
 705      */
 706     std::queue<Event*> cpuEventRemoveList;
 707
 708     /** Records if instructions need to be removed this cycle due to
 709      *  being retired or squashed.
 710      */
 711     bool removeInstsThisCycle;
 712
 713     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 714      * execution unit know, NOT to execute while the instruction is active.
 715      */
 716     bool nonSpecInstActive[ThePipeline::MaxThreads];
 717
 718     /** Instruction Seq. Num of current non-speculative instruction. */
 719     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 720
 721     /** Instruction Seq. Num of last instruction squashed in pipeline */
 722     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 723
 724     /** Last Cycle that the CPU squashed instruction end. */
 725     Tick lastSquashCycle[ThePipeline::MaxThreads];
 726
 727     std::list<ThreadID> fetchPriorityList;
 728
 729   protected:
 730     /** Active Threads List */
 731     std::list<ThreadID> activeThreads;
 732
 733     /** Ready Threads List */
 734     std::list<ThreadID> readyThreads;
 735
 736     /** Suspended Threads List */
 737     std::list<ThreadID> suspendedThreads;
 738
 739     /** Halted Threads List */
 740     std::list<ThreadID> haltedThreads;
 741
 742     /** Thread Status Functions */
 743     bool isThreadActive(ThreadID tid);
 744     bool isThreadReady(ThreadID tid);
 745     bool isThreadSuspended(ThreadID tid);
 746
 747   private:
 748     /** The activity recorder; used to tell if the CPU has any
 749      * activity remaining or if it can go to idle and deschedule
 750      * itself.
 751      */
 752     ActivityRecorder activityRec;
 753
 754   public:
 755     /** Number of Active Threads in the CPU */
 756     ThreadID numActiveThreads() { return activeThreads.size(); }
 757
 758     /** Thread id of active thread
 759      *  Only used for SwitchOnCacheMiss model.
 760      *  Assumes only 1 thread active
 761      */
 762     ThreadID activeThreadId()
 763     {
 764         if (numActiveThreads() > 0)
 765             return activeThreads.front();
 766         else
 767             return InvalidThreadID;
 768     }
 769
 770
 771     /** Records that there was time buffer activity this cycle. */
 772     void activityThisCycle() { activityRec.activity(); }
 773
 774     /** Changes a stage's status to active within the activity recorder. */
 775     void activateStage(const int idx)
 776     { activityRec.activateStage(idx); }
 777
 778     /** Changes a stage's status to inactive within the activity recorder. */
 779     void deactivateStage(const int idx)
 780     { activityRec.deactivateStage(idx); }
 781
 782     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 783     void wakeCPU();
 784
 785     virtual void wakeup();
 786
 787     /* LL/SC debug functionality
 788     unsigned stCondFails;
 789
 790     unsigned readStCondFailures()
 791     { return stCondFails; }
 792
 793     unsigned setStCondFailures(unsigned st_fails)
 794     { return stCondFails = st_fails; }
 795     */
 796
 797     /** Returns a pointer to a thread context. */
 798     ThreadContext *tcBase(ThreadID tid = 0)
 799     {
 800         return thread[tid]->getTC();
 801     }
 802
 803     /** Count the Total Instructions Committed in the CPU. */
 804     virtual Counter totalInsts() const
 805     {
 806         Counter total(0);
 807
 808         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 809             total += thread[tid]->numInst;
 810
 811         return total;
 812     }
 813
 814     /** Count the Total Ops Committed in the CPU. */
 815     virtual Counter totalOps() const
 816     {
 817         Counter total(0);
 818
 819         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 820             total += thread[tid]->numOp;
 821
 822         return total;
 823     }
 824
 825     /** Pointer to the system. */
 826     System *system;
 827
 828     /** The global sequence number counter. */
 829     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 830
 831 #ifdef DEBUG
 832     /** The global event number counter. */
 833     InstSeqNum cpuEventNum;
 834
 835     /** Number of resource requests active in CPU **/
 836     unsigned resReqCount;
 837 #endif
 838
 839     Addr lockAddr;
 840
 841     /** Temporary fix for the lock flag, works in the UP case. */
 842     bool lockFlag;
 843
 844     /** Counter of how many stages have completed draining */
 845     int drainCount;
 846
 847     /** Pointers to all of the threads in the CPU. */
 848     std::vector<Thread *> thread;
 849
 850     /** Per-Stage Instruction Tracing */
 851     bool stageTracing;
 852
 853     /** The cycle that the CPU was last running, used for statistics. */
 854     Tick lastRunningCycle;
 855
 856     void updateContextSwitchStats();
 857     unsigned instsPerSwitch;
 858     Stats::Average instsPerCtxtSwitch;
 859     Stats::Scalar numCtxtSwitches;
 860
 861     /** Update Thread , used for statistic purposes*/
 862     inline void tickThreadStats();
 863
 864     /** Per-Thread Tick */
 865     Stats::Vector threadCycles;
 866
 867     /** Tick for SMT */
 868     Stats::Scalar smtCycles;
 869
 870     /** Stat for total number of times the CPU is descheduled. */
 871     Stats::Scalar timesIdled;
 872
 873     /** Stat for total number of cycles the CPU spends descheduled or no
 874      *  stages active.
 875      */
 876     Stats::Scalar idleCycles;
 877
 878     /** Stat for total number of cycles the CPU is active. */
 879     Stats::Scalar runCycles;
 880
 881     /** Percentage of cycles a stage was active */
 882     Stats::Formula activity;
 883
 884     /** Instruction Mix Stats */
 885     Stats::Scalar comLoads;
 886     Stats::Scalar comStores;
 887     Stats::Scalar comBranches;
 888     Stats::Scalar comNops;
 889     Stats::Scalar comNonSpec;
 890     Stats::Scalar comInts;
 891     Stats::Scalar comFloats;
 892
 893     /** Stat for the number of committed instructions per thread. */
 894     Stats::Vector committedInsts;
 895
 896     /** Stat for the number of committed ops per thread. */
 897     Stats::Vector committedOps;
 898
 899     /** Stat for the number of committed instructions per thread. */
 900     Stats::Vector smtCommittedInsts;
 901
 902     /** Stat for the total number of committed instructions. */
 903     Stats::Scalar totalCommittedInsts;
 904
 905     /** Stat for the CPI per thread. */
 906     Stats::Formula cpi;
 907
 908     /** Stat for the SMT-CPI per thread. */
 909     Stats::Formula smtCpi;
 910
 911     /** Stat for the total CPI. */
 912     Stats::Formula totalCpi;
 913
 914     /** Stat for the IPC per thread. */
 915     Stats::Formula ipc;
 916
 917     /** Stat for the total IPC. */
 918     Stats::Formula smtIpc;
 919
 920     /** Stat for the total IPC. */
 921     Stats::Formula totalIpc;
 922 };
 923
 924 #endif // __CPU_O3_CPU_HH__