src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/registers.hh"
  43 #include "arch/types.hh"
  44 #include "base/statistics.hh"
  45 #include "base/types.hh"
  46 #include "config/full_system.hh"
  47 #include "config/the_isa.hh"
  48 #include "cpu/inorder/inorder_dyn_inst.hh"
  49 #include "cpu/inorder/pipeline_stage.hh"
  50 #include "cpu/inorder/pipeline_traits.hh"
  51 #include "cpu/inorder/reg_dep_map.hh"
  52 #include "cpu/inorder/thread_state.hh"
  53 #include "cpu/o3/dep_graph.hh"
  54 #include "cpu/o3/rename_map.hh"
  55 #include "cpu/activity.hh"
  56 #include "cpu/base.hh"
  57 #include "cpu/simple_thread.hh"
  58 #include "cpu/timebuf.hh"
  59 #include "mem/packet.hh"
  60 #include "mem/port.hh"
  61 #include "mem/request.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/process.hh"
  64
  65 class ThreadContext;
  66 class MemInterface;
  67 class MemObject;
  68 class Process;
  69 class ResourcePool;
  70
  71 class InOrderCPU : public BaseCPU
  72 {
  73
  74   protected:
  75     typedef ThePipeline::Params Params;
  76     typedef InOrderThreadState Thread;
  77
  78    //ISA TypeDefs
  79     typedef TheISA::IntReg IntReg;
  80     typedef TheISA::FloatReg FloatReg;
  81     typedef TheISA::FloatRegBits FloatRegBits;
  82     typedef TheISA::MiscReg MiscReg;
  83     typedef TheISA::RegIndex RegIndex;
  84
  85     //DynInstPtr TypeDefs
  86     typedef ThePipeline::DynInstPtr DynInstPtr;
  87     typedef std::list<DynInstPtr>::iterator ListIt;
  88
  89     //TimeBuffer TypeDefs
  90     typedef TimeBuffer<InterStageStruct> StageQueue;
  91
  92     friend class Resource;
  93
  94   public:
  95     /** Constructs a CPU with the given parameters. */
  96     InOrderCPU(Params *params);
  97     /* Destructor */
  98     ~InOrderCPU();
  99
 100     /** CPU ID */
 101     int cpu_id;
 102
 103     // SE Mode ASIDs
 104     ThreadID asid[ThePipeline::MaxThreads];
 105
 106     /** Type of core that this is */
 107     std::string coreType;
 108
 109     // Only need for SE MODE
 110     enum ThreadModel {
 111         Single,
 112         SMT,
 113         SwitchOnCacheMiss
 114     };
 115
 116     ThreadModel threadModel;
 117
 118     int readCpuId() { return cpu_id; }
 119
 120     void setCpuId(int val) { cpu_id = val; }
 121
 122     Params *cpu_params;
 123
 124   public:
 125     enum Status {
 126         Running,
 127         Idle,
 128         Halted,
 129         Blocked,
 130         SwitchedOut
 131     };
 132
 133     /** Overall CPU status. */
 134     Status _status;
 135   private:
 136     /** Define TickEvent for the CPU */
 137     class TickEvent : public Event
 138     {
 139       private:
 140         /** Pointer to the CPU. */
 141         InOrderCPU *cpu;
 142
 143       public:
 144         /** Constructs a tick event. */
 145         TickEvent(InOrderCPU *c);
 146
 147         /** Processes a tick event, calling tick() on the CPU. */
 148         void process();
 149
 150         /** Returns the description of the tick event. */
 151         const char *description();
 152     };
 153
 154     /** The tick event used for scheduling CPU ticks. */
 155     TickEvent tickEvent;
 156
 157     /** Schedule tick event, regardless of its current state. */
 158     void scheduleTickEvent(int delay)
 159     {
 160         assert(!tickEvent.scheduled() || tickEvent.squashed());
 161         reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
 162     }
 163
 164     /** Unschedule tick event, regardless of its current state. */
 165     void unscheduleTickEvent()
 166     {
 167         if (tickEvent.scheduled())
 168             tickEvent.squash();
 169     }
 170
 171   public:
 172     // List of Events That can be scheduled from
 173     // within the CPU.
 174     // NOTE(1): The Resource Pool also uses this event list
 175     // to schedule events broadcast to all resources interfaces
 176     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 177     // pool event.
 178     enum CPUEventType {
 179         ActivateThread,
 180         ActivateNextReadyThread,
 181         DeactivateThread,
 182         HaltThread,
 183         SuspendThread,
 184         Trap,
 185         Syscall,
 186         SquashFromMemStall,
 187         UpdatePCs,
 188         NumCPUEvents
 189     };
 190
 191     static std::string eventNames[NumCPUEvents];
 192
 193     enum CPUEventPri {
 194         InOrderCPU_Pri                 = Event::CPU_Tick_Pri,
 195         Syscall_Pri                    = Event::CPU_Tick_Pri + 9,
 196         ActivateNextReadyThread_Pri    = Event::CPU_Tick_Pri + 10
 197     };
 198
 199     /** Define CPU Event */
 200     class CPUEvent : public Event
 201     {
 202       protected:
 203         InOrderCPU *cpu;
 204
 205       public:
 206         CPUEventType cpuEventType;
 207         ThreadID tid;
 208         DynInstPtr inst;
 209         Fault fault;
 210         unsigned vpe;
 211         short syscall_num;
 212
 213       public:
 214         /** Constructs a CPU event. */
 215         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 216                  ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
 217
 218         /** Set Type of Event To Be Scheduled */
 219         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 220                       DynInstPtr _inst)
 221         {
 222             fault = _fault;
 223             cpuEventType = e_type;
 224             tid = _tid;
 225             inst = _inst;
 226             vpe = 0;
 227         }
 228
 229         /** Processes a CPU event. */
 230         void process();
 231
 232         /** Returns the description of the CPU event. */
 233         const char *description();
 234
 235         /** Schedule Event */
 236         void scheduleEvent(int delay);
 237
 238         /** Unschedule This Event */
 239         void unscheduleEvent();
 240     };
 241
 242     /** Schedule a CPU Event */
 243     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 244                           DynInstPtr inst, unsigned delay = 0,
 245                           CPUEventPri event_pri = InOrderCPU_Pri);
 246
 247   public:
 248     /** Interface between the CPU and CPU resources. */
 249     ResourcePool *resPool;
 250
 251     /** Instruction used to signify that there is no *real* instruction in
 252         buffer slot */
 253     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 254     DynInstPtr dummyBufferInst;
 255     DynInstPtr dummyReqInst;
 256     DynInstPtr dummyTrapInst[ThePipeline::MaxThreads];
 257
 258     /** Used by resources to signify a denied access to a resource. */
 259     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 260
 261     /** Identifies the resource id that identifies a fetch
 262      * access unit.
 263      */
 264     unsigned fetchPortIdx;
 265
 266     /** Identifies the resource id that identifies a data
 267      * access unit.
 268      */
 269     unsigned dataPortIdx;
 270
 271     /** The Pipeline Stages for the CPU */
 272     PipelineStage *pipelineStage[ThePipeline::NumStages];
 273
 274     /** Width (processing bandwidth) of each stage */
 275     int stageWidth;
 276
 277     /** Program Counters */
 278     TheISA::PCState pc[ThePipeline::MaxThreads];
 279
 280     /** Last Committed PC */
 281     TheISA::PCState lastCommittedPC[ThePipeline::MaxThreads];
 282
 283     /** The Register File for the CPU */
 284     union {
 285         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 286         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 287     } floatRegs;
 288     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 289
 290     /** ISA state */
 291     TheISA::ISA isa[ThePipeline::MaxThreads];
 292
 293     /** Dependency Tracker for Integer & Floating Point Regs */
 294     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 295
 296     /** Register Types Used in Dependency Tracking */
 297     enum RegType { IntType, FloatType, MiscType, NumRegTypes};
 298
 299     /** Global communication structure */
 300     TimeBuffer<TimeStruct> timeBuffer;
 301
 302     /** Communication structure that sits in between pipeline stages */
 303     StageQueue *stageQueue[ThePipeline::NumStages-1];
 304
 305     TheISA::TLB *getITBPtr();
 306     TheISA::TLB *getDTBPtr();
 307
 308     Decoder *getDecoderPtr();
 309
 310     /** Accessor Type for the SkedCache */
 311     typedef uint32_t SkedID;
 312
 313     /** Cache of Instruction Schedule using the instruction's name as a key */
 314     static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
 315
 316     typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 317
 318     /** Initialized to last iterator in map, signifying a invalid entry
 319         on map searches
 320     */
 321     SkedCacheIt endOfSkedIt;
 322
 323     ThePipeline::RSkedPtr frontEndSked;
 324     ThePipeline::RSkedPtr faultSked;
 325
 326     /** Add a new instruction schedule to the schedule cache */
 327     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 328     {
 329         SkedID sked_id = genSkedID(inst);
 330         assert(skedCache.find(sked_id) == skedCache.end());
 331         skedCache[sked_id] = inst_sked;
 332     }
 333
 334
 335     /** Find a instruction schedule */
 336     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 337     {
 338         SkedID sked_id = genSkedID(inst);
 339         SkedCacheIt lookup_it = skedCache.find(sked_id);
 340
 341         if (lookup_it != endOfSkedIt) {
 342             return (*lookup_it).second;
 343         } else {
 344             return NULL;
 345         }
 346     }
 347
 348     static const uint8_t INST_OPCLASS                       = 26;
 349     static const uint8_t INST_LOAD                          = 25;
 350     static const uint8_t INST_STORE                         = 24;
 351     static const uint8_t INST_CONTROL                       = 23;
 352     static const uint8_t INST_NONSPEC                       = 22;
 353     static const uint8_t INST_DEST_REGS                     = 18;
 354     static const uint8_t INST_SRC_REGS                      = 14;
 355     static const uint8_t INST_SPLIT_DATA                    = 13;
 356
 357     inline SkedID genSkedID(DynInstPtr inst)
 358     {
 359         SkedID id = 0;
 360         id = (inst->opClass() << INST_OPCLASS) |
 361             (inst->isLoad() << INST_LOAD) |
 362             (inst->isStore() << INST_STORE) |
 363             (inst->isControl() << INST_CONTROL) |
 364             (inst->isNonSpeculative() << INST_NONSPEC) |
 365             (inst->numDestRegs() << INST_DEST_REGS) |
 366             (inst->numSrcRegs() << INST_SRC_REGS) |
 367             (inst->splitInst << INST_SPLIT_DATA);
 368         return id;
 369     }
 370
 371     ThePipeline::RSkedPtr createFrontEndSked();
 372     ThePipeline::RSkedPtr createFaultSked();
 373     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 374
 375     class StageScheduler {
 376       private:
 377         ThePipeline::RSkedPtr rsked;
 378         int stageNum;
 379         int nextTaskPriority;
 380
 381       public:
 382         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 383             : rsked(_rsked), stageNum(stage_num),
 384               nextTaskPriority(0)
 385         { }
 386
 387         void needs(int unit, int request) {
 388             rsked->push(new ScheduleEntry(
 389                             stageNum, nextTaskPriority++, unit, request
 390                             ));
 391         }
 392
 393         void needs(int unit, int request, int param) {
 394             rsked->push(new ScheduleEntry(
 395                             stageNum, nextTaskPriority++, unit, request, param
 396                             ));
 397         }
 398     };
 399
 400   public:
 401
 402     /** Registers statistics. */
 403     void regStats();
 404
 405     /** Ticks CPU, calling tick() on each stage, and checking the overall
 406      *  activity to see if the CPU should deschedule itself.
 407      */
 408     void tick();
 409
 410     /** Initialize the CPU */
 411     void init();
 412
 413     /** Get a Memory Port */
 414     Port* getPort(const std::string &if_name, int idx = 0);
 415
 416     /** HW return from error interrupt. */
 417     Fault hwrei(ThreadID tid);
 418
 419     bool simPalCheck(int palFunc, ThreadID tid);
 420
 421     void checkForInterrupts();
 422
 423     /** Returns the Fault for any valid interrupt. */
 424     Fault getInterrupts();
 425
 426     /** Processes any an interrupt fault. */
 427     void processInterrupts(Fault interrupt);
 428
 429     /** Halts the CPU. */
 430     void halt() { panic("Halt not implemented!\n"); }
 431
 432     /** Update the Virt and Phys ports of all ThreadContexts to
 433      * reflect change in memory connections. */
 434     void updateMemPorts();
 435
 436     /** Check if this address is a valid instruction address. */
 437     bool validInstAddr(Addr addr) { return true; }
 438
 439     /** Check if this address is a valid data address. */
 440     bool validDataAddr(Addr addr) { return true; }
 441
 442     /** Schedule a syscall on the CPU */
 443     void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
 444                         int delay = 0);
 445
 446     /** Executes a syscall.*/
 447     void syscall(int64_t callnum, ThreadID tid);
 448
 449     /** Schedule a trap on the CPU */
 450     void trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
 451
 452     /** Perform trap to Handle Given Fault */
 453     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 454
 455     /** Schedule thread activation on the CPU */
 456     void activateContext(ThreadID tid, int delay = 0);
 457
 458     /** Add Thread to Active Threads List. */
 459     void activateThread(ThreadID tid);
 460
 461     /** Activate Thread In Each Pipeline Stage */
 462     void activateThreadInPipeline(ThreadID tid);
 463
 464     /** Schedule Thread Activation from Ready List */
 465     void activateNextReadyContext(int delay = 0);
 466
 467     /** Add Thread From Ready List to Active Threads List. */
 468     void activateNextReadyThread();
 469
 470     /** Schedule a thread deactivation on the CPU */
 471     void deactivateContext(ThreadID tid, int delay = 0);
 472
 473     /** Remove from Active Thread List */
 474     void deactivateThread(ThreadID tid);
 475
 476     /** Schedule a thread suspension on the CPU */
 477     void suspendContext(ThreadID tid, int delay = 0);
 478
 479     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 480     void suspendThread(ThreadID tid);
 481
 482     /** Schedule a thread halt on the CPU */
 483     void haltContext(ThreadID tid, int delay = 0);
 484
 485     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 486      *  Threads List
 487      */
 488     void haltThread(ThreadID tid);
 489
 490     /** squashFromMemStall() - sets up a squash event
 491      *  squashDueToMemStall() - squashes pipeline
 492      *  @note: maybe squashContext/squashThread would be better?
 493      */
 494     void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
 495     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 496
 497     void removePipelineStalls(ThreadID tid);
 498     void squashThreadInPipeline(ThreadID tid);
 499     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 500
 501     PipelineStage* getPipeStage(int stage_num);
 502
 503     int
 504     contextId()
 505     {
 506         hack_once("return a bogus context id");
 507         return 0;
 508     }
 509
 510     /** Update The Order In Which We Process Threads. */
 511     void updateThreadPriority();
 512
 513     /** Switches a Pipeline Stage to Active. (Unused currently) */
 514     void switchToActive(int stage_idx)
 515     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 516
 517     /** Get the current instruction sequence number, and increment it. */
 518     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 519     { return globalSeqNum[tid]++; }
 520
 521     /** Get the current instruction sequence number, and increment it. */
 522     InstSeqNum nextInstSeqNum(ThreadID tid)
 523     { return globalSeqNum[tid]; }
 524
 525     /** Increment Instruction Sequence Number */
 526     void incrInstSeqNum(ThreadID tid)
 527     { globalSeqNum[tid]++; }
 528
 529     /** Set Instruction Sequence Number */
 530     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 531     {
 532         globalSeqNum[tid] = seq_num;
 533     }
 534
 535     /** Get & Update Next Event Number */
 536     InstSeqNum getNextEventNum()
 537     {
 538 #ifdef DEBUG
 539         return cpuEventNum++;
 540 #else
 541         return 0;
 542 #endif
 543     }
 544
 545     /** Register file accessors  */
 546     uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
 547
 548     FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
 549
 550     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 551
 552     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 553
 554     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 555
 556     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 557
 558     RegType inline getRegType(RegIndex reg_idx)
 559     {
 560         if (reg_idx < TheISA::FP_Base_DepTag)
 561             return IntType;
 562         else if (reg_idx < TheISA::Ctrl_Base_DepTag)
 563             return FloatType;
 564         else
 565             return MiscType;
 566     }
 567
 568     RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
 569
 570     /** Reads a miscellaneous register. */
 571     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 572
 573     /** Reads a misc. register, including any side effects the read
 574      * might have as defined by the architecture.
 575      */
 576     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 577
 578     /** Sets a miscellaneous register. */
 579     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 580                             ThreadID tid = 0);
 581
 582     /** Sets a misc. register, including any side effects the write
 583      * might have as defined by the architecture.
 584      */
 585     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 586
 587     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 588      *  target thread
 589      */
 590     uint64_t readRegOtherThread(unsigned misc_reg,
 591                                 ThreadID tid = InvalidThreadID);
 592
 593     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 594      * target thread
 595      */
 596     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 597                            ThreadID tid);
 598
 599     /** Reads the commit PC of a specific thread. */
 600     TheISA::PCState
 601     pcState(ThreadID tid)
 602     {
 603         return pc[tid];
 604     }
 605
 606     /** Sets the commit PC of a specific thread. */
 607     void
 608     pcState(const TheISA::PCState &newPC, ThreadID tid)
 609     {
 610         pc[tid] = newPC;
 611     }
 612
 613     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 614     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 615     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 616
 617     /** Function to add instruction onto the head of the list of the
 618      *  instructions.  Used when new instructions are fetched.
 619      */
 620     ListIt addInst(DynInstPtr inst);
 621
 622     /** Find instruction on instruction list */
 623     ListIt findInst(InstSeqNum seq_num, ThreadID tid);
 624
 625     /** Function to tell the CPU that an instruction has completed. */
 626     void instDone(DynInstPtr inst, ThreadID tid);
 627
 628     /** Add Instructions to the CPU Remove List*/
 629     void addToRemoveList(DynInstPtr inst);
 630
 631     /** Remove an instruction from CPU */
 632     void removeInst(DynInstPtr inst);
 633
 634     /** Remove all instructions younger than the given sequence number. */
 635     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 636
 637     /** Removes the instruction pointed to by the iterator. */
 638     inline void squashInstIt(const ListIt inst_it, ThreadID tid);
 639
 640     /** Cleans up all instructions on the instruction remove list. */
 641     void cleanUpRemovedInsts();
 642
 643     /** Cleans up all events on the CPU event remove list. */
 644     void cleanUpRemovedEvents();
 645
 646     /** Debug function to print all instructions on the list. */
 647     void dumpInsts();
 648
 649     /** Forwards an instruction read to the appropriate data
 650      *  resource (indexes into Resource Pool thru "dataPortIdx")
 651      */
 652     Fault read(DynInstPtr inst, Addr addr,
 653                uint8_t *data, unsigned size, unsigned flags);
 654
 655     /** Forwards an instruction write. to the appropriate data
 656      *  resource (indexes into Resource Pool thru "dataPortIdx")
 657      */
 658     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 659                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 660
 661   public:
 662     /** Per-Thread List of all the instructions in flight. */
 663     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 664
 665     /** List of all the instructions that will be removed at the end of this
 666      *  cycle.
 667      */
 668     std::queue<ListIt> removeList;
 669
 670     bool trapPending[ThePipeline::MaxThreads];
 671
 672     /** List of all the cpu event requests that will be removed at the end of
 673      *  the current cycle.
 674      */
 675     std::queue<Event*> cpuEventRemoveList;
 676
 677     /** Records if instructions need to be removed this cycle due to
 678      *  being retired or squashed.
 679      */
 680     bool removeInstsThisCycle;
 681
 682     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 683      * execution unit know, NOT to execute while the instruction is active.
 684      */
 685     bool nonSpecInstActive[ThePipeline::MaxThreads];
 686
 687     /** Instruction Seq. Num of current non-speculative instruction. */
 688     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 689
 690     /** Instruction Seq. Num of last instruction squashed in pipeline */
 691     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 692
 693     /** Last Cycle that the CPU squashed instruction end. */
 694     Tick lastSquashCycle[ThePipeline::MaxThreads];
 695
 696     std::list<ThreadID> fetchPriorityList;
 697
 698   protected:
 699     /** Active Threads List */
 700     std::list<ThreadID> activeThreads;
 701
 702     /** Ready Threads List */
 703     std::list<ThreadID> readyThreads;
 704
 705     /** Suspended Threads List */
 706     std::list<ThreadID> suspendedThreads;
 707
 708     /** Halted Threads List */
 709     std::list<ThreadID> haltedThreads;
 710
 711     /** Thread Status Functions */
 712     bool isThreadActive(ThreadID tid);
 713     bool isThreadReady(ThreadID tid);
 714     bool isThreadSuspended(ThreadID tid);
 715
 716   private:
 717     /** The activity recorder; used to tell if the CPU has any
 718      * activity remaining or if it can go to idle and deschedule
 719      * itself.
 720      */
 721     ActivityRecorder activityRec;
 722
 723   public:
 724     /** Number of Active Threads in the CPU */
 725     ThreadID numActiveThreads() { return activeThreads.size(); }
 726
 727     /** Thread id of active thread
 728      *  Only used for SwitchOnCacheMiss model.
 729      *  Assumes only 1 thread active
 730      */
 731     ThreadID activeThreadId()
 732     {
 733         if (numActiveThreads() > 0)
 734             return activeThreads.front();
 735         else
 736             return InvalidThreadID;
 737     }
 738
 739
 740     /** Records that there was time buffer activity this cycle. */
 741     void activityThisCycle() { activityRec.activity(); }
 742
 743     /** Changes a stage's status to active within the activity recorder. */
 744     void activateStage(const int idx)
 745     { activityRec.activateStage(idx); }
 746
 747     /** Changes a stage's status to inactive within the activity recorder. */
 748     void deactivateStage(const int idx)
 749     { activityRec.deactivateStage(idx); }
 750
 751     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 752     void wakeCPU();
 753
 754     virtual void wakeup();
 755
 756     /* LL/SC debug functionality
 757     unsigned stCondFails;
 758
 759     unsigned readStCondFailures()
 760     { return stCondFails; }
 761
 762     unsigned setStCondFailures(unsigned st_fails)
 763     { return stCondFails = st_fails; }
 764     */
 765
 766     /** Returns a pointer to a thread context. */
 767     ThreadContext *tcBase(ThreadID tid = 0)
 768     {
 769         return thread[tid]->getTC();
 770     }
 771
 772     /** Count the Total Instructions Committed in the CPU. */
 773     virtual Counter totalInstructions() const
 774     {
 775         Counter total(0);
 776
 777         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 778             total += thread[tid]->numInst;
 779
 780         return total;
 781     }
 782
 783 #if FULL_SYSTEM
 784     /** Pointer to the system. */
 785     System *system;
 786 #endif
 787
 788     /** The global sequence number counter. */
 789     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 790
 791 #ifdef DEBUG
 792     /** The global event number counter. */
 793     InstSeqNum cpuEventNum;
 794
 795     /** Number of resource requests active in CPU **/
 796     unsigned resReqCount;
 797 #endif
 798
 799     Addr lockAddr;
 800
 801     /** Temporary fix for the lock flag, works in the UP case. */
 802     bool lockFlag;
 803
 804     /** Counter of how many stages have completed draining */
 805     int drainCount;
 806
 807     /** Pointers to all of the threads in the CPU. */
 808     std::vector<Thread *> thread;
 809
 810     /** Pointer to the icache interface. */
 811     MemInterface *icacheInterface;
 812
 813     /** Pointer to the dcache interface. */
 814     MemInterface *dcacheInterface;
 815
 816     /** Whether or not the CPU should defer its registration. */
 817     bool deferRegistration;
 818
 819     /** Per-Stage Instruction Tracing */
 820     bool stageTracing;
 821
 822     /** The cycle that the CPU was last running, used for statistics. */
 823     Tick lastRunningCycle;
 824
 825     void updateContextSwitchStats();
 826     unsigned instsPerSwitch;
 827     Stats::Average instsPerCtxtSwitch;
 828     Stats::Scalar numCtxtSwitches;
 829
 830     /** Update Thread , used for statistic purposes*/
 831     inline void tickThreadStats();
 832
 833     /** Per-Thread Tick */
 834     Stats::Vector threadCycles;
 835
 836     /** Tick for SMT */
 837     Stats::Scalar smtCycles;
 838
 839     /** Stat for total number of times the CPU is descheduled. */
 840     Stats::Scalar timesIdled;
 841
 842     /** Stat for total number of cycles the CPU spends descheduled or no
 843      *  stages active.
 844      */
 845     Stats::Scalar idleCycles;
 846
 847     /** Stat for total number of cycles the CPU is active. */
 848     Stats::Scalar runCycles;
 849
 850     /** Percentage of cycles a stage was active */
 851     Stats::Formula activity;
 852
 853     /** Instruction Mix Stats */
 854     Stats::Scalar comLoads;
 855     Stats::Scalar comStores;
 856     Stats::Scalar comBranches;
 857     Stats::Scalar comNops;
 858     Stats::Scalar comNonSpec;
 859     Stats::Scalar comInts;
 860     Stats::Scalar comFloats;
 861
 862     /** Stat for the number of committed instructions per thread. */
 863     Stats::Vector committedInsts;
 864
 865     /** Stat for the number of committed instructions per thread. */
 866     Stats::Vector smtCommittedInsts;
 867
 868     /** Stat for the total number of committed instructions. */
 869     Stats::Scalar totalCommittedInsts;
 870
 871     /** Stat for the CPI per thread. */
 872     Stats::Formula cpi;
 873
 874     /** Stat for the SMT-CPI per thread. */
 875     Stats::Formula smtCpi;
 876
 877     /** Stat for the total CPI. */
 878     Stats::Formula totalCpi;
 879
 880     /** Stat for the IPC per thread. */
 881     Stats::Formula ipc;
 882
 883     /** Stat for the total IPC. */
 884     Stats::Formula smtIpc;
 885
 886     /** Stat for the total IPC. */
 887     Stats::Formula totalIpc;
 888 };
 889
 890 #endif // __CPU_O3_CPU_HH__