src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/registers.hh"
  43 #include "arch/types.hh"
  44 #include "base/statistics.hh"
  45 #include "base/types.hh"
  46 #include "config/full_system.hh"
  47 #include "config/the_isa.hh"
  48 #include "cpu/inorder/inorder_dyn_inst.hh"
  49 #include "cpu/inorder/pipeline_stage.hh"
  50 #include "cpu/inorder/pipeline_traits.hh"
  51 #include "cpu/inorder/reg_dep_map.hh"
  52 #include "cpu/inorder/thread_state.hh"
  53 #include "cpu/o3/dep_graph.hh"
  54 #include "cpu/o3/rename_map.hh"
  55 #include "cpu/activity.hh"
  56 #include "cpu/base.hh"
  57 #include "cpu/simple_thread.hh"
  58 #include "cpu/timebuf.hh"
  59 #include "mem/packet.hh"
  60 #include "mem/port.hh"
  61 #include "mem/request.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/process.hh"
  64
  65 class ThreadContext;
  66 class MemInterface;
  67 class MemObject;
  68 class Process;
  69 class ResourcePool;
  70
  71 class InOrderCPU : public BaseCPU
  72 {
  73
  74   protected:
  75     typedef ThePipeline::Params Params;
  76     typedef InOrderThreadState Thread;
  77
  78    //ISA TypeDefs
  79     typedef TheISA::IntReg IntReg;
  80     typedef TheISA::FloatReg FloatReg;
  81     typedef TheISA::FloatRegBits FloatRegBits;
  82     typedef TheISA::MiscReg MiscReg;
  83     typedef TheISA::RegIndex RegIndex;
  84
  85     //DynInstPtr TypeDefs
  86     typedef ThePipeline::DynInstPtr DynInstPtr;
  87     typedef std::list<DynInstPtr>::iterator ListIt;
  88
  89     //TimeBuffer TypeDefs
  90     typedef TimeBuffer<InterStageStruct> StageQueue;
  91
  92     friend class Resource;
  93
  94   public:
  95     /** Constructs a CPU with the given parameters. */
  96     InOrderCPU(Params *params);
  97     /* Destructor */
  98     ~InOrderCPU();
  99
 100     /** CPU ID */
 101     int cpu_id;
 102
 103     // SE Mode ASIDs
 104     ThreadID asid[ThePipeline::MaxThreads];
 105
 106     /** Type of core that this is */
 107     std::string coreType;
 108
 109     // Only need for SE MODE
 110     enum ThreadModel {
 111         Single,
 112         SMT,
 113         SwitchOnCacheMiss
 114     };
 115
 116     ThreadModel threadModel;
 117
 118     int readCpuId() { return cpu_id; }
 119
 120     void setCpuId(int val) { cpu_id = val; }
 121
 122     Params *cpu_params;
 123
 124   public:
 125     enum Status {
 126         Running,
 127         Idle,
 128         Halted,
 129         Blocked,
 130         SwitchedOut
 131     };
 132
 133     /** Overall CPU status. */
 134     Status _status;
 135   private:
 136     /** Define TickEvent for the CPU */
 137     class TickEvent : public Event
 138     {
 139       private:
 140         /** Pointer to the CPU. */
 141         InOrderCPU *cpu;
 142
 143       public:
 144         /** Constructs a tick event. */
 145         TickEvent(InOrderCPU *c);
 146
 147         /** Processes a tick event, calling tick() on the CPU. */
 148         void process();
 149
 150         /** Returns the description of the tick event. */
 151         const char *description();
 152     };
 153
 154     /** The tick event used for scheduling CPU ticks. */
 155     TickEvent tickEvent;
 156
 157     /** Schedule tick event, regardless of its current state. */
 158     void scheduleTickEvent(int delay)
 159     {
 160         assert(!tickEvent.scheduled() || tickEvent.squashed());
 161         reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
 162     }
 163
 164     /** Unschedule tick event, regardless of its current state. */
 165     void unscheduleTickEvent()
 166     {
 167         if (tickEvent.scheduled())
 168             tickEvent.squash();
 169     }
 170
 171   public:
 172     // List of Events That can be scheduled from
 173     // within the CPU.
 174     // NOTE(1): The Resource Pool also uses this event list
 175     // to schedule events broadcast to all resources interfaces
 176     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 177     // pool event.
 178     enum CPUEventType {
 179         ActivateThread,
 180         ActivateNextReadyThread,
 181         DeactivateThread,
 182         HaltThread,
 183         SuspendThread,
 184         Trap,
 185         InstGraduated,
 186         SquashFromMemStall,
 187         UpdatePCs,
 188         NumCPUEvents
 189     };
 190
 191     static std::string eventNames[NumCPUEvents];
 192
 193     /** Define CPU Event */
 194     class CPUEvent : public Event
 195     {
 196       protected:
 197         InOrderCPU *cpu;
 198
 199       public:
 200         CPUEventType cpuEventType;
 201         ThreadID tid;
 202         DynInstPtr inst;
 203         Fault fault;
 204         unsigned vpe;
 205
 206       public:
 207         /** Constructs a CPU event. */
 208         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 209                  ThreadID _tid, DynInstPtr inst, unsigned event_pri_offset);
 210
 211         /** Set Type of Event To Be Scheduled */
 212         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 213                       DynInstPtr _inst)
 214         {
 215             fault = _fault;
 216             cpuEventType = e_type;
 217             tid = _tid;
 218             inst = _inst;
 219             vpe = 0;
 220         }
 221
 222         /** Processes a CPU event. */
 223         void process();
 224
 225         /** Returns the description of the CPU event. */
 226         const char *description();
 227
 228         /** Schedule Event */
 229         void scheduleEvent(int delay);
 230
 231         /** Unschedule This Event */
 232         void unscheduleEvent();
 233     };
 234
 235     /** Schedule a CPU Event */
 236     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 237                           DynInstPtr inst, unsigned delay = 0,
 238                           unsigned event_pri_offset = 0);
 239
 240   public:
 241     /** Interface between the CPU and CPU resources. */
 242     ResourcePool *resPool;
 243
 244     /** Instruction used to signify that there is no *real* instruction in
 245         buffer slot */
 246     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 247     DynInstPtr dummyBufferInst;
 248     DynInstPtr dummyReqInst;
 249
 250     /** Used by resources to signify a denied access to a resource. */
 251     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 252
 253     /** Identifies the resource id that identifies a fetch
 254      * access unit.
 255      */
 256     unsigned fetchPortIdx;
 257
 258     /** Identifies the resource id that identifies a ITB       */
 259     unsigned itbIdx;
 260
 261     /** Identifies the resource id that identifies a data
 262      * access unit.
 263      */
 264     unsigned dataPortIdx;
 265
 266     /** Identifies the resource id that identifies a DTB       */
 267     unsigned dtbIdx;
 268
 269     /** The Pipeline Stages for the CPU */
 270     PipelineStage *pipelineStage[ThePipeline::NumStages];
 271
 272     /** Width (processing bandwidth) of each stage */
 273     int stageWidth;
 274
 275     /** Program Counters */
 276     TheISA::PCState pc[ThePipeline::MaxThreads];
 277
 278     /** The Register File for the CPU */
 279     union {
 280         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 281         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 282     } floatRegs;
 283     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 284
 285     /** ISA state */
 286     TheISA::ISA isa[ThePipeline::MaxThreads];
 287
 288     /** Dependency Tracker for Integer & Floating Point Regs */
 289     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 290
 291     /** Global communication structure */
 292     TimeBuffer<TimeStruct> timeBuffer;
 293
 294     /** Communication structure that sits in between pipeline stages */
 295     StageQueue *stageQueue[ThePipeline::NumStages-1];
 296
 297     TheISA::TLB *getITBPtr();
 298     TheISA::TLB *getDTBPtr();
 299
 300     /** Accessor Type for the SkedCache */
 301     typedef uint32_t SkedID;
 302
 303     /** Cache of Instruction Schedule using the instruction's name as a key */
 304     static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
 305
 306     typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 307
 308     /** Initialized to last iterator in map, signifying a invalid entry
 309         on map searches
 310     */
 311     SkedCacheIt endOfSkedIt;
 312
 313     ThePipeline::RSkedPtr frontEndSked;
 314
 315     /** Add a new instruction schedule to the schedule cache */
 316     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 317     {
 318         SkedID sked_id = genSkedID(inst);
 319         assert(skedCache.find(sked_id) == skedCache.end());
 320         skedCache[sked_id] = inst_sked;
 321     }
 322
 323
 324     /** Find a instruction schedule */
 325     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 326     {
 327         SkedID sked_id = genSkedID(inst);
 328         SkedCacheIt lookup_it = skedCache.find(sked_id);
 329
 330         if (lookup_it != endOfSkedIt) {
 331             return (*lookup_it).second;
 332         } else {
 333             return NULL;
 334         }
 335     }
 336
 337     static const uint8_t INST_OPCLASS                       = 26;
 338     static const uint8_t INST_LOAD                          = 25;
 339     static const uint8_t INST_STORE                         = 24;
 340     static const uint8_t INST_CONTROL                       = 23;
 341     static const uint8_t INST_NONSPEC                       = 22;
 342     static const uint8_t INST_DEST_REGS                     = 18;
 343     static const uint8_t INST_SRC_REGS                      = 14;
 344
 345     inline SkedID genSkedID(DynInstPtr inst)
 346     {
 347         SkedID id = 0;
 348         id = (inst->opClass() << INST_OPCLASS) |
 349             (inst->isLoad() << INST_LOAD) |
 350             (inst->isStore() << INST_STORE) |
 351             (inst->isControl() << INST_CONTROL) |
 352             (inst->isNonSpeculative() << INST_NONSPEC) |
 353             (inst->numDestRegs() << INST_DEST_REGS) |
 354             (inst->numSrcRegs() << INST_SRC_REGS);
 355         return id;
 356     }
 357
 358     ThePipeline::RSkedPtr createFrontEndSked();
 359     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 360
 361     class StageScheduler {
 362       private:
 363         ThePipeline::RSkedPtr rsked;
 364         int stageNum;
 365         int nextTaskPriority;
 366
 367       public:
 368         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 369             : rsked(_rsked), stageNum(stage_num),
 370               nextTaskPriority(0)
 371         { }
 372
 373         void needs(int unit, int request) {
 374             rsked->push(new ScheduleEntry(
 375                             stageNum, nextTaskPriority++, unit, request
 376                             ));
 377         }
 378
 379         void needs(int unit, int request, int param) {
 380             rsked->push(new ScheduleEntry(
 381                             stageNum, nextTaskPriority++, unit, request, param
 382                             ));
 383         }
 384     };
 385
 386   public:
 387
 388     /** Registers statistics. */
 389     void regStats();
 390
 391     /** Ticks CPU, calling tick() on each stage, and checking the overall
 392      *  activity to see if the CPU should deschedule itself.
 393      */
 394     void tick();
 395
 396     /** Initialize the CPU */
 397     void init();
 398
 399     /** Get a Memory Port */
 400     Port* getPort(const std::string &if_name, int idx = 0);
 401
 402 #if FULL_SYSTEM
 403     /** HW return from error interrupt. */
 404     Fault hwrei(ThreadID tid);
 405
 406     bool simPalCheck(int palFunc, ThreadID tid);
 407
 408     /** Returns the Fault for any valid interrupt. */
 409     Fault getInterrupts();
 410
 411     /** Processes any an interrupt fault. */
 412     void processInterrupts(Fault interrupt);
 413
 414     /** Halts the CPU. */
 415     void halt() { panic("Halt not implemented!\n"); }
 416
 417     /** Update the Virt and Phys ports of all ThreadContexts to
 418      * reflect change in memory connections. */
 419     void updateMemPorts();
 420
 421     /** Check if this address is a valid instruction address. */
 422     bool validInstAddr(Addr addr) { return true; }
 423
 424     /** Check if this address is a valid data address. */
 425     bool validDataAddr(Addr addr) { return true; }
 426 #endif
 427
 428     /** trap() - sets up a trap event on the cpuTraps to handle given fault.
 429      *  trapCPU() - Traps to handle given fault
 430      */
 431     void trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
 432     void trapCPU(Fault fault, ThreadID tid, DynInstPtr inst);
 433
 434     /** Add Thread to Active Threads List. */
 435     void activateContext(ThreadID tid, int delay = 0);
 436     void activateThread(ThreadID tid);
 437     void activateThreadInPipeline(ThreadID tid);
 438
 439     /** Add Thread to Active Threads List. */
 440     void activateNextReadyContext(int delay = 0);
 441     void activateNextReadyThread();
 442
 443     /** Remove from Active Thread List */
 444     void deactivateContext(ThreadID tid, int delay = 0);
 445     void deactivateThread(ThreadID tid);
 446
 447     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 448     void suspendContext(ThreadID tid, int delay = 0);
 449     void suspendThread(ThreadID tid);
 450
 451     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 452      *  Threads List
 453      */
 454     void haltContext(ThreadID tid, int delay = 0);
 455     void haltThread(ThreadID tid);
 456
 457     /** squashFromMemStall() - sets up a squash event
 458      *  squashDueToMemStall() - squashes pipeline
 459      *  @note: maybe squashContext/squashThread would be better?
 460      */
 461     void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
 462     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 463
 464     void removePipelineStalls(ThreadID tid);
 465     void squashThreadInPipeline(ThreadID tid);
 466     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 467
 468     PipelineStage* getPipeStage(int stage_num);
 469
 470     int
 471     contextId()
 472     {
 473         hack_once("return a bogus context id");
 474         return 0;
 475     }
 476
 477     /** Update The Order In Which We Process Threads. */
 478     void updateThreadPriority();
 479
 480     /** Switches a Pipeline Stage to Active. (Unused currently) */
 481     void switchToActive(int stage_idx)
 482     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 483
 484     /** Get the current instruction sequence number, and increment it. */
 485     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 486     { return globalSeqNum[tid]++; }
 487
 488     /** Get the current instruction sequence number, and increment it. */
 489     InstSeqNum nextInstSeqNum(ThreadID tid)
 490     { return globalSeqNum[tid]; }
 491
 492     /** Increment Instruction Sequence Number */
 493     void incrInstSeqNum(ThreadID tid)
 494     { globalSeqNum[tid]++; }
 495
 496     /** Set Instruction Sequence Number */
 497     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 498     {
 499         globalSeqNum[tid] = seq_num;
 500     }
 501
 502     /** Get & Update Next Event Number */
 503     InstSeqNum getNextEventNum()
 504     {
 505 #ifdef DEBUG
 506         return cpuEventNum++;
 507 #else
 508         return 0;
 509 #endif
 510     }
 511
 512     /** Register file accessors  */
 513     uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
 514
 515     FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
 516
 517     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 518
 519     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 520
 521     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 522
 523     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 524
 525     RegIndex flattenRegIdx(RegIndex reg_idx, ThreadID tid);
 526
 527     /** Reads a miscellaneous register. */
 528     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 529
 530     /** Reads a misc. register, including any side effects the read
 531      * might have as defined by the architecture.
 532      */
 533     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 534
 535     /** Sets a miscellaneous register. */
 536     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 537                             ThreadID tid = 0);
 538
 539     /** Sets a misc. register, including any side effects the write
 540      * might have as defined by the architecture.
 541      */
 542     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 543
 544     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 545      *  target thread
 546      */
 547     uint64_t readRegOtherThread(unsigned misc_reg,
 548                                 ThreadID tid = InvalidThreadID);
 549
 550     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 551      * target thread
 552      */
 553     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 554                            ThreadID tid);
 555
 556     /** Reads the commit PC of a specific thread. */
 557     TheISA::PCState
 558     pcState(ThreadID tid)
 559     {
 560         return pc[tid];
 561     }
 562
 563     /** Sets the commit PC of a specific thread. */
 564     void
 565     pcState(const TheISA::PCState &newPC, ThreadID tid)
 566     {
 567         pc[tid] = newPC;
 568     }
 569
 570     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 571     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 572     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 573
 574     /** Function to add instruction onto the head of the list of the
 575      *  instructions.  Used when new instructions are fetched.
 576      */
 577     ListIt addInst(DynInstPtr &inst);
 578
 579     /** Function to tell the CPU that an instruction has completed. */
 580     void instDone(DynInstPtr inst, ThreadID tid);
 581
 582     /** Add Instructions to the CPU Remove List*/
 583     void addToRemoveList(DynInstPtr &inst);
 584
 585     /** Remove an instruction from CPU */
 586     void removeInst(DynInstPtr &inst);
 587
 588     /** Remove all instructions younger than the given sequence number. */
 589     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 590
 591     /** Removes the instruction pointed to by the iterator. */
 592     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 593
 594     /** Cleans up all instructions on the instruction remove list. */
 595     void cleanUpRemovedInsts();
 596
 597     /** Cleans up all events on the CPU event remove list. */
 598     void cleanUpRemovedEvents();
 599
 600     /** Debug function to print all instructions on the list. */
 601     void dumpInsts();
 602
 603     /** Forwards an instruction read to the appropriate data
 604      *  resource (indexes into Resource Pool thru "dataPortIdx")
 605      */
 606     Fault read(DynInstPtr inst, Addr addr,
 607                uint8_t *data, unsigned size, unsigned flags);
 608
 609     /** Forwards an instruction write. to the appropriate data
 610      *  resource (indexes into Resource Pool thru "dataPortIdx")
 611      */
 612     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 613                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 614
 615     /** Executes a syscall.*/
 616     void syscall(int64_t callnum, ThreadID tid);
 617
 618   public:
 619     /** Per-Thread List of all the instructions in flight. */
 620     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 621
 622     /** List of all the instructions that will be removed at the end of this
 623      *  cycle.
 624      */
 625     std::queue<ListIt> removeList;
 626
 627     /** List of all the cpu event requests that will be removed at the end of
 628      *  the current cycle.
 629      */
 630     std::queue<Event*> cpuEventRemoveList;
 631
 632     /** Records if instructions need to be removed this cycle due to
 633      *  being retired or squashed.
 634      */
 635     bool removeInstsThisCycle;
 636
 637     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 638      * execution unit know, NOT to execute while the instruction is active.
 639      */
 640     bool nonSpecInstActive[ThePipeline::MaxThreads];
 641
 642     /** Instruction Seq. Num of current non-speculative instruction. */
 643     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 644
 645     /** Instruction Seq. Num of last instruction squashed in pipeline */
 646     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 647
 648     /** Last Cycle that the CPU squashed instruction end. */
 649     Tick lastSquashCycle[ThePipeline::MaxThreads];
 650
 651     std::list<ThreadID> fetchPriorityList;
 652
 653   protected:
 654     /** Active Threads List */
 655     std::list<ThreadID> activeThreads;
 656
 657     /** Ready Threads List */
 658     std::list<ThreadID> readyThreads;
 659
 660     /** Suspended Threads List */
 661     std::list<ThreadID> suspendedThreads;
 662
 663     /** Halted Threads List */
 664     std::list<ThreadID> haltedThreads;
 665
 666     /** Thread Status Functions */
 667     bool isThreadActive(ThreadID tid);
 668     bool isThreadReady(ThreadID tid);
 669     bool isThreadSuspended(ThreadID tid);
 670
 671   private:
 672     /** The activity recorder; used to tell if the CPU has any
 673      * activity remaining or if it can go to idle and deschedule
 674      * itself.
 675      */
 676     ActivityRecorder activityRec;
 677
 678   public:
 679     /** Number of Active Threads in the CPU */
 680     ThreadID numActiveThreads() { return activeThreads.size(); }
 681
 682     /** Thread id of active thread
 683      *  Only used for SwitchOnCacheMiss model.
 684      *  Assumes only 1 thread active
 685      */
 686     ThreadID activeThreadId()
 687     {
 688         if (numActiveThreads() > 0)
 689             return activeThreads.front();
 690         else
 691             return InvalidThreadID;
 692     }
 693
 694
 695     /** Records that there was time buffer activity this cycle. */
 696     void activityThisCycle() { activityRec.activity(); }
 697
 698     /** Changes a stage's status to active within the activity recorder. */
 699     void activateStage(const int idx)
 700     { activityRec.activateStage(idx); }
 701
 702     /** Changes a stage's status to inactive within the activity recorder. */
 703     void deactivateStage(const int idx)
 704     { activityRec.deactivateStage(idx); }
 705
 706     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 707     void wakeCPU();
 708
 709 #if FULL_SYSTEM
 710     virtual void wakeup();
 711 #endif
 712
 713     // LL/SC debug functionality
 714     unsigned stCondFails;
 715
 716     unsigned readStCondFailures()
 717     { return stCondFails; }
 718
 719     unsigned setStCondFailures(unsigned st_fails)
 720     { return stCondFails = st_fails; }
 721
 722     /** Returns a pointer to a thread context. */
 723     ThreadContext *tcBase(ThreadID tid = 0)
 724     {
 725         return thread[tid]->getTC();
 726     }
 727
 728     /** Count the Total Instructions Committed in the CPU. */
 729     virtual Counter totalInstructions() const
 730     {
 731         Counter total(0);
 732
 733         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 734             total += thread[tid]->numInst;
 735
 736         return total;
 737     }
 738
 739 #if FULL_SYSTEM
 740     /** Pointer to the system. */
 741     System *system;
 742
 743     /** Pointer to physical memory. */
 744     PhysicalMemory *physmem;
 745 #endif
 746
 747     /** The global sequence number counter. */
 748     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 749
 750 #ifdef DEBUG
 751     /** The global event number counter. */
 752     InstSeqNum cpuEventNum;
 753
 754     /** Number of resource requests active in CPU **/
 755     unsigned resReqCount;
 756 #endif
 757
 758     /** Counter of how many stages have completed switching out. */
 759     int switchCount;
 760
 761     /** Pointers to all of the threads in the CPU. */
 762     std::vector<Thread *> thread;
 763
 764     /** Pointer to the icache interface. */
 765     MemInterface *icacheInterface;
 766
 767     /** Pointer to the dcache interface. */
 768     MemInterface *dcacheInterface;
 769
 770     /** Whether or not the CPU should defer its registration. */
 771     bool deferRegistration;
 772
 773     /** Per-Stage Instruction Tracing */
 774     bool stageTracing;
 775
 776     /** The cycle that the CPU was last running, used for statistics. */
 777     Tick lastRunningCycle;
 778
 779     void updateContextSwitchStats();
 780     unsigned instsPerSwitch;
 781     Stats::Average instsPerCtxtSwitch;
 782     Stats::Scalar numCtxtSwitches;
 783
 784     /** Update Thread , used for statistic purposes*/
 785     inline void tickThreadStats();
 786
 787     /** Per-Thread Tick */
 788     Stats::Vector threadCycles;
 789
 790     /** Tick for SMT */
 791     Stats::Scalar smtCycles;
 792
 793     /** Stat for total number of times the CPU is descheduled. */
 794     Stats::Scalar timesIdled;
 795
 796     /** Stat for total number of cycles the CPU spends descheduled or no
 797      *  stages active.
 798      */
 799     Stats::Scalar idleCycles;
 800
 801     /** Stat for total number of cycles the CPU is active. */
 802     Stats::Scalar runCycles;
 803
 804     /** Percentage of cycles a stage was active */
 805     Stats::Formula activity;
 806
 807     /** Instruction Mix Stats */
 808     Stats::Scalar comLoads;
 809     Stats::Scalar comStores;
 810     Stats::Scalar comBranches;
 811     Stats::Scalar comNops;
 812     Stats::Scalar comNonSpec;
 813     Stats::Scalar comInts;
 814     Stats::Scalar comFloats;
 815
 816     /** Stat for the number of committed instructions per thread. */
 817     Stats::Vector committedInsts;
 818
 819     /** Stat for the number of committed instructions per thread. */
 820     Stats::Vector smtCommittedInsts;
 821
 822     /** Stat for the total number of committed instructions. */
 823     Stats::Scalar totalCommittedInsts;
 824
 825     /** Stat for the CPI per thread. */
 826     Stats::Formula cpi;
 827
 828     /** Stat for the SMT-CPI per thread. */
 829     Stats::Formula smtCpi;
 830
 831     /** Stat for the total CPI. */
 832     Stats::Formula totalCpi;
 833
 834     /** Stat for the IPC per thread. */
 835     Stats::Formula ipc;
 836
 837     /** Stat for the total IPC. */
 838     Stats::Formula smtIpc;
 839
 840     /** Stat for the total IPC. */
 841     Stats::Formula totalIpc;
 842 };
 843
 844 #endif // __CPU_O3_CPU_HH__