src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007 MIPS Technologies, Inc.
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Korey Sewell
  41  *
  42  */
  43
  44 #ifndef __CPU_INORDER_CPU_HH__
  45 #define __CPU_INORDER_CPU_HH__
  46
  47 #include <iostream>
  48 #include <list>
  49 #include <queue>
  50 #include <set>
  51 #include <vector>
  52
  53 #include "arch/isa_traits.hh"
  54 #include "arch/registers.hh"
  55 #include "arch/types.hh"
  56 #include "base/statistics.hh"
  57 #include "base/types.hh"
  58 #include "config/the_isa.hh"
  59 #include "cpu/inorder/inorder_dyn_inst.hh"
  60 #include "cpu/inorder/pipeline_stage.hh"
  61 #include "cpu/inorder/pipeline_traits.hh"
  62 #include "cpu/inorder/reg_dep_map.hh"
  63 #include "cpu/inorder/thread_state.hh"
  64 #include "cpu/o3/dep_graph.hh"
  65 #include "cpu/o3/rename_map.hh"
  66 #include "cpu/activity.hh"
  67 #include "cpu/base.hh"
  68 #include "cpu/simple_thread.hh"
  69 #include "cpu/timebuf.hh"
  70 #include "mem/packet.hh"
  71 #include "mem/port.hh"
  72 #include "mem/request.hh"
  73 #include "sim/eventq.hh"
  74 #include "sim/process.hh"
  75
  76 class CacheUnit;
  77 class ThreadContext;
  78 class MemInterface;
  79 class MemObject;
  80 class Process;
  81 class ResourcePool;
  82
  83 class InOrderCPU : public BaseCPU
  84 {
  85
  86   protected:
  87     typedef ThePipeline::Params Params;
  88     typedef InOrderThreadState Thread;
  89
  90    //ISA TypeDefs
  91     typedef TheISA::IntReg IntReg;
  92     typedef TheISA::FloatReg FloatReg;
  93     typedef TheISA::FloatRegBits FloatRegBits;
  94     typedef TheISA::MiscReg MiscReg;
  95     typedef TheISA::RegIndex RegIndex;
  96
  97     //DynInstPtr TypeDefs
  98     typedef ThePipeline::DynInstPtr DynInstPtr;
  99     typedef std::list<DynInstPtr>::iterator ListIt;
 100
 101     //TimeBuffer TypeDefs
 102     typedef TimeBuffer<InterStageStruct> StageQueue;
 103
 104     friend class Resource;
 105
 106   public:
 107     /** Constructs a CPU with the given parameters. */
 108     InOrderCPU(Params *params);
 109     /* Destructor */
 110     ~InOrderCPU();
 111
 112     void verifyMemoryMode() const;
 113
 114     /** Return a reference to the data port. */
 115     virtual CpuPort &getDataPort() { return dataPort; }
 116
 117     /** Return a reference to the instruction port. */
 118     virtual CpuPort &getInstPort() { return instPort; }
 119
 120     /** CPU ID */
 121     int cpu_id;
 122
 123     // SE Mode ASIDs
 124     ThreadID asid[ThePipeline::MaxThreads];
 125
 126     /** Type of core that this is */
 127     std::string coreType;
 128
 129     // Only need for SE MODE
 130     enum ThreadModel {
 131         Single,
 132         SMT,
 133         SwitchOnCacheMiss
 134     };
 135
 136     ThreadModel threadModel;
 137
 138     int readCpuId() { return cpu_id; }
 139
 140     void setCpuId(int val) { cpu_id = val; }
 141
 142     Params *cpu_params;
 143
 144   public:
 145     enum Status {
 146         Running,
 147         Idle,
 148         Halted,
 149         Blocked,
 150         SwitchedOut
 151     };
 152
 153     /** Overall CPU status. */
 154     Status _status;
 155   private:
 156
 157     /**
 158      * CachePort class for the in-order CPU, interacting with a
 159      * specific CacheUnit in the pipeline.
 160      */
 161     class CachePort : public CpuPort
 162     {
 163
 164       private:
 165         /** Pointer to cache unit */
 166         CacheUnit *cacheUnit;
 167
 168       public:
 169         /** Default constructor. */
 170         CachePort(CacheUnit *_cacheUnit, const std::string& name);
 171
 172       protected:
 173
 174         /** Timing version of receive */
 175         bool recvTimingResp(PacketPtr pkt);
 176
 177         /** Handles doing a retry of a failed timing request. */
 178         void recvRetry();
 179
 180         /** Ignoring snoops for now. */
 181         void recvTimingSnoopReq(PacketPtr pkt) { }
 182     };
 183
 184     /** Define TickEvent for the CPU */
 185     class TickEvent : public Event
 186     {
 187       private:
 188         /** Pointer to the CPU. */
 189         InOrderCPU *cpu;
 190
 191       public:
 192         /** Constructs a tick event. */
 193         TickEvent(InOrderCPU *c);
 194
 195         /** Processes a tick event, calling tick() on the CPU. */
 196         void process();
 197
 198         /** Returns the description of the tick event. */
 199         const char *description() const;
 200     };
 201
 202     /** The tick event used for scheduling CPU ticks. */
 203     TickEvent tickEvent;
 204
 205     /** Schedule tick event, regardless of its current state. */
 206     void scheduleTickEvent(Cycles delay)
 207     {
 208         assert(!tickEvent.scheduled() || tickEvent.squashed());
 209         reschedule(&tickEvent, clockEdge(delay), true);
 210     }
 211
 212     /** Unschedule tick event, regardless of its current state. */
 213     void unscheduleTickEvent()
 214     {
 215         if (tickEvent.scheduled())
 216             tickEvent.squash();
 217     }
 218
 219   public:
 220     // List of Events That can be scheduled from
 221     // within the CPU.
 222     // NOTE(1): The Resource Pool also uses this event list
 223     // to schedule events broadcast to all resources interfaces
 224     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 225     // pool event.
 226     enum CPUEventType {
 227         ActivateThread,
 228         ActivateNextReadyThread,
 229         DeactivateThread,
 230         HaltThread,
 231         SuspendThread,
 232         Trap,
 233         Syscall,
 234         SquashFromMemStall,
 235         UpdatePCs,
 236         NumCPUEvents
 237     };
 238
 239     static std::string eventNames[NumCPUEvents];
 240
 241     enum CPUEventPri {
 242         InOrderCPU_Pri                 = Event::CPU_Tick_Pri,
 243         Syscall_Pri                    = Event::CPU_Tick_Pri + 9,
 244         ActivateNextReadyThread_Pri    = Event::CPU_Tick_Pri + 10
 245     };
 246
 247     /** Define CPU Event */
 248     class CPUEvent : public Event
 249     {
 250       protected:
 251         InOrderCPU *cpu;
 252
 253       public:
 254         CPUEventType cpuEventType;
 255         ThreadID tid;
 256         DynInstPtr inst;
 257         Fault fault;
 258         unsigned vpe;
 259         short syscall_num;
 260
 261       public:
 262         /** Constructs a CPU event. */
 263         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 264                  ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
 265
 266         /** Set Type of Event To Be Scheduled */
 267         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 268                       DynInstPtr _inst)
 269         {
 270             fault = _fault;
 271             cpuEventType = e_type;
 272             tid = _tid;
 273             inst = _inst;
 274             vpe = 0;
 275         }
 276
 277         /** Processes a CPU event. */
 278         void process();
 279
 280         /** Returns the description of the CPU event. */
 281         const char *description() const;
 282
 283         /** Schedule Event */
 284         void scheduleEvent(Cycles delay);
 285
 286         /** Unschedule This Event */
 287         void unscheduleEvent();
 288     };
 289
 290     /** Schedule a CPU Event */
 291     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 292                           DynInstPtr inst, Cycles delay = Cycles(0),
 293                           CPUEventPri event_pri = InOrderCPU_Pri);
 294
 295   public:
 296
 297     /** Width (processing bandwidth) of each stage */
 298     int stageWidth;
 299
 300     /** Interface between the CPU and CPU resources. */
 301     ResourcePool *resPool;
 302
 303     /** Instruction used to signify that there is no *real* instruction in
 304         buffer slot */
 305     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 306     DynInstPtr dummyBufferInst;
 307     DynInstPtr dummyReqInst;
 308     DynInstPtr dummyTrapInst[ThePipeline::MaxThreads];
 309
 310     /** Used by resources to signify a denied access to a resource. */
 311     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 312
 313     /** The Pipeline Stages for the CPU */
 314     PipelineStage *pipelineStage[ThePipeline::NumStages];
 315
 316     /** Program Counters */
 317     TheISA::PCState pc[ThePipeline::MaxThreads];
 318
 319     /** Last Committed PC */
 320     TheISA::PCState lastCommittedPC[ThePipeline::MaxThreads];
 321
 322     /** The Register File for the CPU */
 323     union {
 324         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 325         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 326     } floatRegs;
 327     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 328
 329     /** ISA state */
 330     std::vector<TheISA::ISA *> isa;
 331
 332     /** Dependency Tracker for Integer & Floating Point Regs */
 333     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 334
 335     /** Register Types Used in Dependency Tracking */
 336     enum RegType { IntType, FloatType, MiscType, NumRegTypes};
 337
 338     /** Global communication structure */
 339     TimeBuffer<TimeStruct> timeBuffer;
 340
 341     /** Communication structure that sits in between pipeline stages */
 342     StageQueue *stageQueue[ThePipeline::NumStages-1];
 343
 344     TheISA::TLB *getITBPtr();
 345     TheISA::TLB *getDTBPtr();
 346
 347     TheISA::Decoder *getDecoderPtr(unsigned tid);
 348
 349     /** Accessor Type for the SkedCache */
 350     typedef uint32_t SkedID;
 351
 352     /** Cache of Instruction Schedule using the instruction's name as a key */
 353     static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
 354
 355     typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 356
 357     /** Initialized to last iterator in map, signifying a invalid entry
 358         on map searches
 359     */
 360     SkedCacheIt endOfSkedIt;
 361
 362     ThePipeline::RSkedPtr frontEndSked;
 363     ThePipeline::RSkedPtr faultSked;
 364
 365     /** Add a new instruction schedule to the schedule cache */
 366     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 367     {
 368         SkedID sked_id = genSkedID(inst);
 369         assert(skedCache.find(sked_id) == skedCache.end());
 370         skedCache[sked_id] = inst_sked;
 371     }
 372
 373
 374     /** Find a instruction schedule */
 375     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 376     {
 377         SkedID sked_id = genSkedID(inst);
 378         SkedCacheIt lookup_it = skedCache.find(sked_id);
 379
 380         if (lookup_it != endOfSkedIt) {
 381             return (*lookup_it).second;
 382         } else {
 383             return NULL;
 384         }
 385     }
 386
 387     static const uint8_t INST_OPCLASS                       = 26;
 388     static const uint8_t INST_LOAD                          = 25;
 389     static const uint8_t INST_STORE                         = 24;
 390     static const uint8_t INST_CONTROL                       = 23;
 391     static const uint8_t INST_NONSPEC                       = 22;
 392     static const uint8_t INST_DEST_REGS                     = 18;
 393     static const uint8_t INST_SRC_REGS                      = 14;
 394     static const uint8_t INST_SPLIT_DATA                    = 13;
 395
 396     inline SkedID genSkedID(DynInstPtr inst)
 397     {
 398         SkedID id = 0;
 399         id = (inst->opClass() << INST_OPCLASS) |
 400             (inst->isLoad() << INST_LOAD) |
 401             (inst->isStore() << INST_STORE) |
 402             (inst->isControl() << INST_CONTROL) |
 403             (inst->isNonSpeculative() << INST_NONSPEC) |
 404             (inst->numDestRegs() << INST_DEST_REGS) |
 405             (inst->numSrcRegs() << INST_SRC_REGS) |
 406             (inst->splitInst << INST_SPLIT_DATA);
 407         return id;
 408     }
 409
 410     ThePipeline::RSkedPtr createFrontEndSked();
 411     ThePipeline::RSkedPtr createFaultSked();
 412     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 413
 414     class StageScheduler {
 415       private:
 416         ThePipeline::RSkedPtr rsked;
 417         int stageNum;
 418         int nextTaskPriority;
 419
 420       public:
 421         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 422             : rsked(_rsked), stageNum(stage_num),
 423               nextTaskPriority(0)
 424         { }
 425
 426         void needs(int unit, int request) {
 427             rsked->push(new ScheduleEntry(
 428                             stageNum, nextTaskPriority++, unit, request
 429                             ));
 430         }
 431
 432         void needs(int unit, int request, int param) {
 433             rsked->push(new ScheduleEntry(
 434                             stageNum, nextTaskPriority++, unit, request, param
 435                             ));
 436         }
 437     };
 438
 439   private:
 440
 441     /** Data port. Note that it has to appear after the resPool. */
 442     CachePort dataPort;
 443
 444     /** Instruction port. Note that it has to appear after the resPool. */
 445     CachePort instPort;
 446
 447   public:
 448
 449     /** Registers statistics. */
 450     void regStats();
 451
 452     /** Ticks CPU, calling tick() on each stage, and checking the overall
 453      *  activity to see if the CPU should deschedule itself.
 454      */
 455     void tick();
 456
 457     /** Initialize the CPU */
 458     void init();
 459
 460     /** HW return from error interrupt. */
 461     Fault hwrei(ThreadID tid);
 462
 463     bool simPalCheck(int palFunc, ThreadID tid);
 464
 465     void checkForInterrupts();
 466
 467     /** Returns the Fault for any valid interrupt. */
 468     Fault getInterrupts();
 469
 470     /** Processes any an interrupt fault. */
 471     void processInterrupts(Fault interrupt);
 472
 473     /** Halts the CPU. */
 474     void halt() { panic("Halt not implemented!\n"); }
 475
 476     /** Check if this address is a valid instruction address. */
 477     bool validInstAddr(Addr addr) { return true; }
 478
 479     /** Check if this address is a valid data address. */
 480     bool validDataAddr(Addr addr) { return true; }
 481
 482     /** Schedule a syscall on the CPU */
 483     void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
 484                         Cycles delay = Cycles(0));
 485
 486     /** Executes a syscall.*/
 487     void syscall(int64_t callnum, ThreadID tid);
 488
 489     /** Schedule a trap on the CPU */
 490     void trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
 491                      Cycles delay = Cycles(0));
 492
 493     /** Perform trap to Handle Given Fault */
 494     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 495
 496     /** Schedule thread activation on the CPU */
 497     void activateContext(ThreadID tid, Cycles delay = Cycles(0));
 498
 499     /** Add Thread to Active Threads List. */
 500     void activateThread(ThreadID tid);
 501
 502     /** Activate Thread In Each Pipeline Stage */
 503     void activateThreadInPipeline(ThreadID tid);
 504
 505     /** Schedule Thread Activation from Ready List */
 506     void activateNextReadyContext(Cycles delay = Cycles(0));
 507
 508     /** Add Thread From Ready List to Active Threads List. */
 509     void activateNextReadyThread();
 510
 511     /** Schedule a thread deactivation on the CPU */
 512     void deactivateContext(ThreadID tid, Cycles delay = Cycles(0));
 513
 514     /** Remove from Active Thread List */
 515     void deactivateThread(ThreadID tid);
 516
 517     /** Schedule a thread suspension on the CPU */
 518   void suspendContext(ThreadID tid);
 519
 520     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 521     void suspendThread(ThreadID tid);
 522
 523     /** Schedule a thread halt on the CPU */
 524     void haltContext(ThreadID tid);
 525
 526     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 527      *  Threads List
 528      */
 529     void haltThread(ThreadID tid);
 530
 531     /** squashFromMemStall() - sets up a squash event
 532      *  squashDueToMemStall() - squashes pipeline
 533      *  @note: maybe squashContext/squashThread would be better?
 534      */
 535     void squashFromMemStall(DynInstPtr inst, ThreadID tid,
 536                             Cycles delay = Cycles(0));
 537     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 538
 539     void removePipelineStalls(ThreadID tid);
 540     void squashThreadInPipeline(ThreadID tid);
 541     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 542
 543     PipelineStage* getPipeStage(int stage_num);
 544
 545     int
 546     contextId()
 547     {
 548         hack_once("return a bogus context id");
 549         return 0;
 550     }
 551
 552     /** Update The Order In Which We Process Threads. */
 553     void updateThreadPriority();
 554
 555     /** Switches a Pipeline Stage to Active. (Unused currently) */
 556     void switchToActive(int stage_idx)
 557     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 558
 559     /** Get the current instruction sequence number, and increment it. */
 560     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 561     { return globalSeqNum[tid]++; }
 562
 563     /** Get the current instruction sequence number, and increment it. */
 564     InstSeqNum nextInstSeqNum(ThreadID tid)
 565     { return globalSeqNum[tid]; }
 566
 567     /** Increment Instruction Sequence Number */
 568     void incrInstSeqNum(ThreadID tid)
 569     { globalSeqNum[tid]++; }
 570
 571     /** Set Instruction Sequence Number */
 572     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 573     {
 574         globalSeqNum[tid] = seq_num;
 575     }
 576
 577     /** Get & Update Next Event Number */
 578     InstSeqNum getNextEventNum()
 579     {
 580 #ifdef DEBUG
 581         return cpuEventNum++;
 582 #else
 583         return 0;
 584 #endif
 585     }
 586
 587     /** Register file accessors  */
 588     uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
 589
 590     FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
 591
 592     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 593
 594     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 595
 596     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 597
 598     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 599
 600     RegType inline getRegType(RegIndex reg_idx)
 601     {
 602         if (reg_idx < TheISA::FP_Base_DepTag)
 603             return IntType;
 604         else if (reg_idx < TheISA::Ctrl_Base_DepTag)
 605             return FloatType;
 606         else
 607             return MiscType;
 608     }
 609
 610     RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
 611
 612     /** Reads a miscellaneous register. */
 613     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 614
 615     /** Reads a misc. register, including any side effects the read
 616      * might have as defined by the architecture.
 617      */
 618     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 619
 620     /** Sets a miscellaneous register. */
 621     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 622                             ThreadID tid = 0);
 623
 624     /** Sets a misc. register, including any side effects the write
 625      * might have as defined by the architecture.
 626      */
 627     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 628
 629     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 630      *  target thread
 631      */
 632     uint64_t readRegOtherThread(unsigned misc_reg,
 633                                 ThreadID tid = InvalidThreadID);
 634
 635     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 636      * target thread
 637      */
 638     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 639                            ThreadID tid);
 640
 641     /** Reads the commit PC of a specific thread. */
 642     TheISA::PCState
 643     pcState(ThreadID tid)
 644     {
 645         return pc[tid];
 646     }
 647
 648     /** Sets the commit PC of a specific thread. */
 649     void
 650     pcState(const TheISA::PCState &newPC, ThreadID tid)
 651     {
 652         pc[tid] = newPC;
 653     }
 654
 655     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 656     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 657     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 658
 659     /** Function to add instruction onto the head of the list of the
 660      *  instructions.  Used when new instructions are fetched.
 661      */
 662     ListIt addInst(DynInstPtr inst);
 663
 664     /** Find instruction on instruction list */
 665     ListIt findInst(InstSeqNum seq_num, ThreadID tid);
 666
 667     /** Function to tell the CPU that an instruction has completed. */
 668     void instDone(DynInstPtr inst, ThreadID tid);
 669
 670     /** Add Instructions to the CPU Remove List*/
 671     void addToRemoveList(DynInstPtr inst);
 672
 673     /** Remove an instruction from CPU */
 674     void removeInst(DynInstPtr inst);
 675
 676     /** Remove all instructions younger than the given sequence number. */
 677     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 678
 679     /** Removes the instruction pointed to by the iterator. */
 680     inline void squashInstIt(const ListIt inst_it, ThreadID tid);
 681
 682     /** Cleans up all instructions on the instruction remove list. */
 683     void cleanUpRemovedInsts();
 684
 685     /** Cleans up all events on the CPU event remove list. */
 686     void cleanUpRemovedEvents();
 687
 688     /** Debug function to print all instructions on the list. */
 689     void dumpInsts();
 690
 691     /** Forwards an instruction read to the appropriate data
 692      *  resource (indexes into Resource Pool thru "dataPortIdx")
 693      */
 694     Fault read(DynInstPtr inst, Addr addr,
 695                uint8_t *data, unsigned size, unsigned flags);
 696
 697     /** Forwards an instruction write. to the appropriate data
 698      *  resource (indexes into Resource Pool thru "dataPortIdx")
 699      */
 700     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 701                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 702
 703   public:
 704     /** Per-Thread List of all the instructions in flight. */
 705     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 706
 707     /** List of all the instructions that will be removed at the end of this
 708      *  cycle.
 709      */
 710     std::queue<ListIt> removeList;
 711
 712     bool trapPending[ThePipeline::MaxThreads];
 713
 714     /** List of all the cpu event requests that will be removed at the end of
 715      *  the current cycle.
 716      */
 717     std::queue<Event*> cpuEventRemoveList;
 718
 719     /** Records if instructions need to be removed this cycle due to
 720      *  being retired or squashed.
 721      */
 722     bool removeInstsThisCycle;
 723
 724     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 725      * execution unit know, NOT to execute while the instruction is active.
 726      */
 727     bool nonSpecInstActive[ThePipeline::MaxThreads];
 728
 729     /** Instruction Seq. Num of current non-speculative instruction. */
 730     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 731
 732     /** Instruction Seq. Num of last instruction squashed in pipeline */
 733     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 734
 735     /** Last Cycle that the CPU squashed instruction end. */
 736     Tick lastSquashCycle[ThePipeline::MaxThreads];
 737
 738     std::list<ThreadID> fetchPriorityList;
 739
 740   protected:
 741     /** Active Threads List */
 742     std::list<ThreadID> activeThreads;
 743
 744     /** Ready Threads List */
 745     std::list<ThreadID> readyThreads;
 746
 747     /** Suspended Threads List */
 748     std::list<ThreadID> suspendedThreads;
 749
 750     /** Halted Threads List */
 751     std::list<ThreadID> haltedThreads;
 752
 753     /** Thread Status Functions */
 754     bool isThreadActive(ThreadID tid);
 755     bool isThreadReady(ThreadID tid);
 756     bool isThreadSuspended(ThreadID tid);
 757
 758   private:
 759     /** The activity recorder; used to tell if the CPU has any
 760      * activity remaining or if it can go to idle and deschedule
 761      * itself.
 762      */
 763     ActivityRecorder activityRec;
 764
 765   public:
 766     /** Number of Active Threads in the CPU */
 767     ThreadID numActiveThreads() { return activeThreads.size(); }
 768
 769     /** Thread id of active thread
 770      *  Only used for SwitchOnCacheMiss model.
 771      *  Assumes only 1 thread active
 772      */
 773     ThreadID activeThreadId()
 774     {
 775         if (numActiveThreads() > 0)
 776             return activeThreads.front();
 777         else
 778             return InvalidThreadID;
 779     }
 780
 781
 782     /** Records that there was time buffer activity this cycle. */
 783     void activityThisCycle() { activityRec.activity(); }
 784
 785     /** Changes a stage's status to active within the activity recorder. */
 786     void activateStage(const int idx)
 787     { activityRec.activateStage(idx); }
 788
 789     /** Changes a stage's status to inactive within the activity recorder. */
 790     void deactivateStage(const int idx)
 791     { activityRec.deactivateStage(idx); }
 792
 793     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 794     void wakeCPU();
 795
 796     virtual void wakeup();
 797
 798     /* LL/SC debug functionality
 799     unsigned stCondFails;
 800
 801     unsigned readStCondFailures()
 802     { return stCondFails; }
 803
 804     unsigned setStCondFailures(unsigned st_fails)
 805     { return stCondFails = st_fails; }
 806     */
 807
 808     /** Returns a pointer to a thread context. */
 809     ThreadContext *tcBase(ThreadID tid = 0)
 810     {
 811         return thread[tid]->getTC();
 812     }
 813
 814     /** Count the Total Instructions Committed in the CPU. */
 815     virtual Counter totalInsts() const
 816     {
 817         Counter total(0);
 818
 819         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 820             total += thread[tid]->numInst;
 821
 822         return total;
 823     }
 824
 825     /** Count the Total Ops Committed in the CPU. */
 826     virtual Counter totalOps() const
 827     {
 828         Counter total(0);
 829
 830         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 831             total += thread[tid]->numOp;
 832
 833         return total;
 834     }
 835
 836     /** Pointer to the system. */
 837     System *system;
 838
 839     /** The global sequence number counter. */
 840     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 841
 842 #ifdef DEBUG
 843     /** The global event number counter. */
 844     InstSeqNum cpuEventNum;
 845
 846     /** Number of resource requests active in CPU **/
 847     unsigned resReqCount;
 848 #endif
 849
 850     Addr lockAddr;
 851
 852     /** Temporary fix for the lock flag, works in the UP case. */
 853     bool lockFlag;
 854
 855     /** Counter of how many stages have completed draining */
 856     int drainCount;
 857
 858     /** Pointers to all of the threads in the CPU. */
 859     std::vector<Thread *> thread;
 860
 861     /** Per-Stage Instruction Tracing */
 862     bool stageTracing;
 863
 864     /** The cycle that the CPU was last running, used for statistics. */
 865     Tick lastRunningCycle;
 866
 867     void updateContextSwitchStats();
 868     unsigned instsPerSwitch;
 869     Stats::Average instsPerCtxtSwitch;
 870     Stats::Scalar numCtxtSwitches;
 871
 872     /** Update Thread , used for statistic purposes*/
 873     inline void tickThreadStats();
 874
 875     /** Per-Thread Tick */
 876     Stats::Vector threadCycles;
 877
 878     /** Tick for SMT */
 879     Stats::Scalar smtCycles;
 880
 881     /** Stat for total number of times the CPU is descheduled. */
 882     Stats::Scalar timesIdled;
 883
 884     /** Stat for total number of cycles the CPU spends descheduled or no
 885      *  stages active.
 886      */
 887     Stats::Scalar idleCycles;
 888
 889     /** Stat for total number of cycles the CPU is active. */
 890     Stats::Scalar runCycles;
 891
 892     /** Percentage of cycles a stage was active */
 893     Stats::Formula activity;
 894
 895     /** Instruction Mix Stats */
 896     Stats::Scalar comLoads;
 897     Stats::Scalar comStores;
 898     Stats::Scalar comBranches;
 899     Stats::Scalar comNops;
 900     Stats::Scalar comNonSpec;
 901     Stats::Scalar comInts;
 902     Stats::Scalar comFloats;
 903
 904     /** Stat for the number of committed instructions per thread. */
 905     Stats::Vector committedInsts;
 906
 907     /** Stat for the number of committed ops per thread. */
 908     Stats::Vector committedOps;
 909
 910     /** Stat for the number of committed instructions per thread. */
 911     Stats::Vector smtCommittedInsts;
 912
 913     /** Stat for the total number of committed instructions. */
 914     Stats::Scalar totalCommittedInsts;
 915
 916     /** Stat for the CPI per thread. */
 917     Stats::Formula cpi;
 918
 919     /** Stat for the SMT-CPI per thread. */
 920     Stats::Formula smtCpi;
 921
 922     /** Stat for the total CPI. */
 923     Stats::Formula totalCpi;
 924
 925     /** Stat for the IPC per thread. */
 926     Stats::Formula ipc;
 927
 928     /** Stat for the total IPC. */
 929     Stats::Formula smtIpc;
 930
 931     /** Stat for the total IPC. */
 932     Stats::Formula totalIpc;
 933 };
 934
 935 #endif // __CPU_O3_CPU_HH__