2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_CPU_HH__
33 #define __CPU_INORDER_CPU_HH__
41 #include "arch/isa_traits.hh"
42 #include "arch/types.hh"
43 #include "base/statistics.hh"
44 #include "base/timebuf.hh"
45 #include "base/types.hh"
46 #include "config/full_system.hh"
47 #include "cpu/activity.hh"
48 #include "cpu/base.hh"
49 #include "cpu/simple_thread.hh"
50 #include "cpu/inorder/inorder_dyn_inst.hh"
51 #include "cpu/inorder/pipeline_traits.hh"
52 #include "cpu/inorder/pipeline_stage.hh"
53 #include "cpu/inorder/thread_state.hh"
54 #include "cpu/inorder/reg_dep_map.hh"
55 #include "cpu/o3/dep_graph.hh"
56 #include "cpu/o3/rename_map.hh"
57 #include "mem/packet.hh"
58 #include "mem/port.hh"
59 #include "mem/request.hh"
60 #include "sim/eventq.hh"
61 #include "sim/process.hh"
69 class InOrderCPU : public BaseCPU
73 typedef ThePipeline::Params Params;
74 typedef InOrderThreadState Thread;
77 typedef TheISA::IntReg IntReg;
78 typedef TheISA::FloatReg FloatReg;
79 typedef TheISA::FloatRegBits FloatRegBits;
80 typedef TheISA::RegFile RegFile;
81 typedef TheISA::MiscReg MiscReg;
84 typedef ThePipeline::DynInstPtr DynInstPtr;
85 typedef std::list<DynInstPtr>::iterator ListIt;
88 typedef TimeBuffer<InterStageStruct> StageQueue;
90 friend class Resource;
93 /** Constructs a CPU with the given parameters. */
94 InOrderCPU(Params *params);
99 /** Type of core that this is */
100 std::string coreType;
102 int readCpuId() { return cpu_id; }
104 void setCpuId(int val) { cpu_id = val; }
117 /** Overall CPU status. */
121 /** Define TickEvent for the CPU */
122 class TickEvent : public Event
125 /** Pointer to the CPU. */
129 /** Constructs a tick event. */
130 TickEvent(InOrderCPU *c);
132 /** Processes a tick event, calling tick() on the CPU. */
135 /** Returns the description of the tick event. */
136 const char *description();
139 /** The tick event used for scheduling CPU ticks. */
142 /** Schedule tick event, regardless of its current state. */
143 void scheduleTickEvent(int delay)
145 if (tickEvent.squashed())
146 mainEventQueue.reschedule(&tickEvent, nextCycle(curTick + ticks(delay)));
147 else if (!tickEvent.scheduled())
148 mainEventQueue.schedule(&tickEvent, nextCycle(curTick + ticks(delay)));
151 /** Unschedule tick event, regardless of its current state. */
152 void unscheduleTickEvent()
154 if (tickEvent.scheduled())
159 // List of Events That can be scheduled from
161 // NOTE(1): The Resource Pool also uses this event list
162 // to schedule events broadcast to all resources interfaces
163 // NOTE(2): CPU Events usually need to schedule a corresponding resource
180 static std::string eventNames[NumCPUEvents];
182 /** Define CPU Event */
183 class CPUEvent : public Event
189 CPUEventType cpuEventType;
195 /** Constructs a CPU event. */
196 CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
197 ThreadID _tid, unsigned _vpe);
199 /** Set Type of Event To Be Scheduled */
200 void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
204 cpuEventType = e_type;
209 /** Processes a resource event. */
210 virtual void process();
212 /** Returns the description of the resource event. */
213 const char *description();
215 /** Schedule Event */
216 void scheduleEvent(int delay);
218 /** Unschedule This Event */
219 void unscheduleEvent();
222 /** Schedule a CPU Event */
223 void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
224 unsigned vpe, unsigned delay = 0);
227 /** Interface between the CPU and CPU resources. */
228 ResourcePool *resPool;
230 /** Instruction used to signify that there is no *real* instruction in buffer slot */
231 DynInstPtr dummyBufferInst;
233 /** Used by resources to signify a denied access to a resource. */
234 ResourceRequest *dummyReq;
236 /** Identifies the resource id that identifies a fetch
239 unsigned fetchPortIdx;
241 /** Identifies the resource id that identifies a ITB */
244 /** Identifies the resource id that identifies a data
247 unsigned dataPortIdx;
249 /** Identifies the resource id that identifies a DTB */
252 /** The Pipeline Stages for the CPU */
253 PipelineStage *pipelineStage[ThePipeline::NumStages];
255 /** Program Counters */
256 TheISA::IntReg PC[ThePipeline::MaxThreads];
257 TheISA::IntReg nextPC[ThePipeline::MaxThreads];
258 TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
260 /** The Register File for the CPU */
261 TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];;
262 TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];;
265 TheISA::ISA isa[ThePipeline::MaxThreads];
267 /** Dependency Tracker for Integer & Floating Point Regs */
268 RegDepMap archRegDepMap[ThePipeline::MaxThreads];
270 /** Global communication structure */
271 TimeBuffer<TimeStruct> timeBuffer;
273 /** Communication structure that sits in between pipeline stages */
274 StageQueue *stageQueue[ThePipeline::NumStages-1];
276 TheISA::TLB *getITBPtr();
277 TheISA::TLB *getDTBPtr();
281 /** Registers statistics. */
284 /** Ticks CPU, calling tick() on each stage, and checking the overall
285 * activity to see if the CPU should deschedule itself.
289 /** Initialize the CPU */
292 /** Reset State in the CPU */
295 /** Get a Memory Port */
296 Port* getPort(const std::string &if_name, int idx = 0);
298 /** trap() - sets up a trap event on the cpuTraps to handle given fault.
299 * trapCPU() - Traps to handle given fault
301 void trap(Fault fault, ThreadID tid, int delay = 0);
302 void trapCPU(Fault fault, ThreadID tid);
304 /** Setup CPU to insert a thread's context */
305 void insertThread(ThreadID tid);
307 /** Remove all of a thread's context from CPU */
308 void removeThread(ThreadID tid);
310 /** Add Thread to Active Threads List. */
311 void activateContext(ThreadID tid, int delay = 0);
312 void activateThread(ThreadID tid);
314 /** Remove Thread from Active Threads List */
315 void suspendContext(ThreadID tid, int delay = 0);
316 void suspendThread(ThreadID tid);
318 /** Remove Thread from Active Threads List &&
319 * Remove Thread Context from CPU.
321 void deallocateContext(ThreadID tid, int delay = 0);
322 void deallocateThread(ThreadID tid);
323 void deactivateThread(ThreadID tid);
325 PipelineStage* getPipeStage(int stage_num);
330 hack_once("return a bogus context id");
334 /** Remove Thread from Active Threads List &&
335 * Remove Thread Context from CPU.
337 void haltContext(ThreadID tid, int delay = 0);
339 void removePipelineStalls(ThreadID tid);
341 void squashThreadInPipeline(ThreadID tid);
343 /// Notify the CPU to enable a virtual processor element.
344 virtual void enableVirtProcElement(unsigned vpe);
345 void enableVPEs(unsigned vpe);
347 /// Notify the CPU to disable a virtual processor element.
348 virtual void disableVirtProcElement(ThreadID tid, unsigned vpe);
349 void disableVPEs(ThreadID tid, unsigned vpe);
351 /// Notify the CPU that multithreading is enabled.
352 virtual void enableMultiThreading(unsigned vpe);
353 void enableThreads(unsigned vpe);
355 /// Notify the CPU that multithreading is disabled.
356 virtual void disableMultiThreading(ThreadID tid, unsigned vpe);
357 void disableThreads(ThreadID tid, unsigned vpe);
359 /** Activate a Thread When CPU Resources are Available. */
360 void activateWhenReady(ThreadID tid);
362 /** Add or Remove a Thread Context in the CPU. */
363 void doContextSwitch();
365 /** Update The Order In Which We Process Threads. */
366 void updateThreadPriority();
368 /** Switches a Pipeline Stage to Active. (Unused currently) */
369 void switchToActive(int stage_idx)
370 { /*pipelineStage[stage_idx]->switchToActive();*/ }
372 /** Get the current instruction sequence number, and increment it. */
373 InstSeqNum getAndIncrementInstSeq(ThreadID tid)
374 { return globalSeqNum[tid]++; }
376 /** Get the current instruction sequence number, and increment it. */
377 InstSeqNum nextInstSeqNum(ThreadID tid)
378 { return globalSeqNum[tid]; }
380 /** Increment Instruction Sequence Number */
381 void incrInstSeqNum(ThreadID tid)
382 { globalSeqNum[tid]++; }
384 /** Set Instruction Sequence Number */
385 void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
387 globalSeqNum[tid] = seq_num;
390 /** Get & Update Next Event Number */
391 InstSeqNum getNextEventNum()
393 return cpuEventNum++;
396 /** Get instruction asid. */
397 int getInstAsid(ThreadID tid)
398 { return thread[tid]->getInstAsid(); }
400 /** Get data asid. */
401 int getDataAsid(ThreadID tid)
402 { return thread[tid]->getDataAsid(); }
404 /** Register file accessors */
405 uint64_t readIntReg(int reg_idx, ThreadID tid);
407 FloatReg readFloatReg(int reg_idx, ThreadID tid);
409 FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
411 void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
413 void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
415 void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid);
417 /** Reads a miscellaneous register. */
418 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
420 /** Reads a misc. register, including any side effects the read
421 * might have as defined by the architecture.
423 MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
425 /** Sets a miscellaneous register. */
426 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
429 /** Sets a misc. register, including any side effects the write
430 * might have as defined by the architecture.
432 void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
434 /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
437 uint64_t readRegOtherThread(unsigned misc_reg,
438 ThreadID tid = InvalidThreadID);
440 /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
443 void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
446 /** Reads the commit PC of a specific thread. */
447 uint64_t readPC(ThreadID tid);
449 /** Sets the commit PC of a specific thread. */
450 void setPC(Addr new_PC, ThreadID tid);
452 /** Reads the next PC of a specific thread. */
453 uint64_t readNextPC(ThreadID tid);
455 /** Sets the next PC of a specific thread. */
456 void setNextPC(uint64_t val, ThreadID tid);
458 /** Reads the next NPC of a specific thread. */
459 uint64_t readNextNPC(ThreadID tid);
461 /** Sets the next NPC of a specific thread. */
462 void setNextNPC(uint64_t val, ThreadID tid);
464 /** Function to add instruction onto the head of the list of the
465 * instructions. Used when new instructions are fetched.
467 ListIt addInst(DynInstPtr &inst);
469 /** Function to tell the CPU that an instruction has completed. */
470 void instDone(DynInstPtr inst, ThreadID tid);
472 /** Add Instructions to the CPU Remove List*/
473 void addToRemoveList(DynInstPtr &inst);
475 /** Remove an instruction from CPU */
476 void removeInst(DynInstPtr &inst);
478 /** Remove all instructions younger than the given sequence number. */
479 void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
481 /** Removes the instruction pointed to by the iterator. */
482 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
484 /** Cleans up all instructions on the instruction remove list. */
485 void cleanUpRemovedInsts();
487 /** Cleans up all instructions on the request remove list. */
488 void cleanUpRemovedReqs();
490 /** Cleans up all instructions on the CPU event remove list. */
491 void cleanUpRemovedEvents();
493 /** Debug function to print all instructions on the list. */
496 /** Forwards an instruction read to the appropriate data
497 * resource (indexes into Resource Pool thru "dataPortIdx")
500 Fault read(DynInstPtr inst, Addr addr, T &data, unsigned flags);
502 /** Forwards an instruction write. to the appropriate data
503 * resource (indexes into Resource Pool thru "dataPortIdx")
506 Fault write(DynInstPtr inst, T data, Addr addr, unsigned flags,
507 uint64_t *write_res = NULL);
509 /** Forwards an instruction prefetch to the appropriate data
510 * resource (indexes into Resource Pool thru "dataPortIdx")
512 void prefetch(DynInstPtr inst);
514 /** Forwards an instruction writeHint to the appropriate data
515 * resource (indexes into Resource Pool thru "dataPortIdx")
517 void writeHint(DynInstPtr inst);
519 /** Executes a syscall.*/
520 void syscall(int64_t callnum, ThreadID tid);
523 /** Per-Thread List of all the instructions in flight. */
524 std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
526 /** List of all the instructions that will be removed at the end of this
529 std::queue<ListIt> removeList;
531 /** List of all the resource requests that will be removed at the end of this
534 std::queue<ResourceRequest*> reqRemoveList;
536 /** List of all the cpu event requests that will be removed at the end of
539 std::queue<Event*> cpuEventRemoveList;
541 /** Records if instructions need to be removed this cycle due to
542 * being retired or squashed.
544 bool removeInstsThisCycle;
546 /** True if there is non-speculative Inst Active In Pipeline. Lets any
547 * execution unit know, NOT to execute while the instruction is active.
549 bool nonSpecInstActive[ThePipeline::MaxThreads];
551 /** Instruction Seq. Num of current non-speculative instruction. */
552 InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
554 /** Instruction Seq. Num of last instruction squashed in pipeline */
555 InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
557 /** Last Cycle that the CPU squashed instruction end. */
558 Tick lastSquashCycle[ThePipeline::MaxThreads];
560 std::list<ThreadID> fetchPriorityList;
563 /** Active Threads List */
564 std::list<ThreadID> activeThreads;
566 /** Current Threads List */
567 std::list<ThreadID> currentThreads;
569 /** Suspended Threads List */
570 std::list<ThreadID> suspendedThreads;
572 /** Thread Status Functions (Unused Currently) */
573 bool isThreadInCPU(ThreadID tid);
574 bool isThreadActive(ThreadID tid);
575 bool isThreadSuspended(ThreadID tid);
576 void addToCurrentThreads(ThreadID tid);
577 void removeFromCurrentThreads(ThreadID tid);
580 /** The activity recorder; used to tell if the CPU has any
581 * activity remaining or if it can go to idle and deschedule
584 ActivityRecorder activityRec;
587 void readFunctional(Addr addr, uint32_t &buffer);
589 /** Number of Active Threads in the CPU */
590 ThreadID numActiveThreads() { return activeThreads.size(); }
592 /** Records that there was time buffer activity this cycle. */
593 void activityThisCycle() { activityRec.activity(); }
595 /** Changes a stage's status to active within the activity recorder. */
596 void activateStage(const int idx)
597 { activityRec.activateStage(idx); }
599 /** Changes a stage's status to inactive within the activity recorder. */
600 void deactivateStage(const int idx)
601 { activityRec.deactivateStage(idx); }
603 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
606 /** Gets a free thread id. Use if thread ids change across system. */
607 ThreadID getFreeTid();
609 // LL/SC debug functionality
610 unsigned stCondFails;
611 unsigned readStCondFailures() { return stCondFails; }
612 unsigned setStCondFailures(unsigned st_fails) { return stCondFails = st_fails; }
614 /** Returns a pointer to a thread context. */
615 ThreadContext *tcBase(ThreadID tid = 0)
617 return thread[tid]->getTC();
620 /** Count the Total Instructions Committed in the CPU. */
621 virtual Counter totalInstructions() const
625 for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
626 total += thread[tid]->numInst;
631 /** The global sequence number counter. */
632 InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
634 /** The global event number counter. */
635 InstSeqNum cpuEventNum;
637 /** Counter of how many stages have completed switching out. */
640 /** Pointers to all of the threads in the CPU. */
641 std::vector<Thread *> thread;
643 /** Pointer to the icache interface. */
644 MemInterface *icacheInterface;
646 /** Pointer to the dcache interface. */
647 MemInterface *dcacheInterface;
649 /** Whether or not the CPU should defer its registration. */
650 bool deferRegistration;
652 /** Per-Stage Instruction Tracing */
655 /** Is there a context switch pending? */
658 /** Threads Scheduled to Enter CPU */
659 std::list<int> cpuWaitList;
661 /** The cycle that the CPU was last running, used for statistics. */
662 Tick lastRunningCycle;
664 /** Number of Virtual Processors the CPU can process */
665 unsigned numVirtProcs;
667 /** Update Thread , used for statistic purposes*/
668 inline void tickThreadStats();
670 /** Per-Thread Tick */
671 Stats::Vector threadCycles;
674 Stats::Scalar smtCycles;
676 /** Stat for total number of times the CPU is descheduled. */
677 Stats::Scalar timesIdled;
679 /** Stat for total number of cycles the CPU spends descheduled. */
680 Stats::Scalar idleCycles;
682 /** Stat for the number of committed instructions per thread. */
683 Stats::Vector committedInsts;
685 /** Stat for the number of committed instructions per thread. */
686 Stats::Vector smtCommittedInsts;
688 /** Stat for the total number of committed instructions. */
689 Stats::Scalar totalCommittedInsts;
691 /** Stat for the CPI per thread. */
694 /** Stat for the SMT-CPI per thread. */
695 Stats::Formula smtCpi;
697 /** Stat for the total CPI. */
698 Stats::Formula totalCpi;
700 /** Stat for the IPC per thread. */
703 /** Stat for the total IPC. */
704 Stats::Formula smtIpc;
706 /** Stat for the total IPC. */
707 Stats::Formula totalIpc;
710 #endif // __CPU_O3_CPU_HH__