src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/types.hh"
  43 #include "arch/registers.hh"
  44 #include "base/statistics.hh"
  45 #include "base/timebuf.hh"
  46 #include "base/types.hh"
  47 #include "config/full_system.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/activity.hh"
  50 #include "cpu/base.hh"
  51 #include "cpu/simple_thread.hh"
  52 #include "cpu/inorder/inorder_dyn_inst.hh"
  53 #include "cpu/inorder/pipeline_traits.hh"
  54 #include "cpu/inorder/pipeline_stage.hh"
  55 #include "cpu/inorder/thread_state.hh"
  56 #include "cpu/inorder/reg_dep_map.hh"
  57 #include "cpu/o3/dep_graph.hh"
  58 #include "cpu/o3/rename_map.hh"
  59 #include "mem/packet.hh"
  60 #include "mem/port.hh"
  61 #include "mem/request.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/process.hh"
  64
  65 class ThreadContext;
  66 class MemInterface;
  67 class MemObject;
  68 class Process;
  69 class ResourcePool;
  70
  71 class InOrderCPU : public BaseCPU
  72 {
  73
  74   protected:
  75     typedef ThePipeline::Params Params;
  76     typedef InOrderThreadState Thread;
  77
  78    //ISA TypeDefs
  79     typedef TheISA::IntReg IntReg;
  80     typedef TheISA::FloatReg FloatReg;
  81     typedef TheISA::FloatRegBits FloatRegBits;
  82     typedef TheISA::MiscReg MiscReg;
  83
  84     //DynInstPtr TypeDefs
  85     typedef ThePipeline::DynInstPtr DynInstPtr;
  86     typedef std::list<DynInstPtr>::iterator ListIt;
  87
  88     //TimeBuffer TypeDefs
  89     typedef TimeBuffer<InterStageStruct> StageQueue;
  90
  91     friend class Resource;
  92
  93   public:
  94     /** Constructs a CPU with the given parameters. */
  95     InOrderCPU(Params *params);
  96
  97     /** CPU ID */
  98     int cpu_id;
  99
 100     /** Type of core that this is */
 101     std::string coreType;
 102
 103     int readCpuId() { return cpu_id; }
 104
 105     void setCpuId(int val) { cpu_id = val; }
 106
 107     Params *cpu_params;
 108
 109   public:
 110     enum Status {
 111         Running,
 112         Idle,
 113         Halted,
 114         Blocked,
 115         SwitchedOut
 116     };
 117
 118     /** Overall CPU status. */
 119     Status _status;
 120
 121   private:
 122     /** Define TickEvent for the CPU */
 123     class TickEvent : public Event
 124     {
 125       private:
 126         /** Pointer to the CPU. */
 127         InOrderCPU *cpu;
 128
 129       public:
 130         /** Constructs a tick event. */
 131         TickEvent(InOrderCPU *c);
 132
 133         /** Processes a tick event, calling tick() on the CPU. */
 134         void process();
 135
 136         /** Returns the description of the tick event. */
 137         const char *description();
 138     };
 139
 140     /** The tick event used for scheduling CPU ticks. */
 141     TickEvent tickEvent;
 142
 143     /** Schedule tick event, regardless of its current state. */
 144     void scheduleTickEvent(int delay)
 145     {
 146         if (tickEvent.squashed())
 147           mainEventQueue.reschedule(&tickEvent, nextCycle(curTick + ticks(delay)));
 148         else if (!tickEvent.scheduled())
 149           mainEventQueue.schedule(&tickEvent, nextCycle(curTick + ticks(delay)));
 150     }
 151
 152     /** Unschedule tick event, regardless of its current state. */
 153     void unscheduleTickEvent()
 154     {
 155         if (tickEvent.scheduled())
 156             tickEvent.squash();
 157     }
 158
 159   public:
 160     // List of Events That can be scheduled from
 161     // within the CPU.
 162     // NOTE(1): The Resource Pool also uses this event list
 163     // to schedule events broadcast to all resources interfaces
 164     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 165     // pool event.
 166     enum CPUEventType {
 167         ActivateThread,
 168         DeallocateThread,
 169         SuspendThread,
 170         DisableThreads,
 171         EnableThreads,
 172         DisableVPEs,
 173         EnableVPEs,
 174         Trap,
 175         InstGraduated,
 176         SquashAll,
 177         UpdatePCs,
 178         NumCPUEvents
 179     };
 180
 181     static std::string eventNames[NumCPUEvents];
 182
 183     /** Define CPU Event */
 184     class CPUEvent : public Event
 185     {
 186       protected:
 187         InOrderCPU *cpu;
 188
 189       public:
 190         CPUEventType cpuEventType;
 191         ThreadID tid;
 192         unsigned vpe;
 193         Fault fault;
 194
 195       public:
 196         /** Constructs a CPU event. */
 197         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 198                  ThreadID _tid, unsigned _vpe);
 199
 200         /** Set Type of Event To Be Scheduled */
 201         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 202                       unsigned _vpe)
 203         {
 204             fault = _fault;
 205             cpuEventType = e_type;
 206             tid = _tid;
 207             vpe = _vpe;
 208         }
 209
 210         /** Processes a resource event. */
 211         virtual void process();
 212
 213         /** Returns the description of the resource event. */
 214         const char *description();
 215
 216         /** Schedule Event */
 217         void scheduleEvent(int delay);
 218
 219         /** Unschedule This Event */
 220         void unscheduleEvent();
 221     };
 222
 223     /** Schedule a CPU Event */
 224     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 225                           unsigned vpe, unsigned delay = 0);
 226
 227   public:
 228     /** Interface between the CPU and CPU resources. */
 229     ResourcePool *resPool;
 230
 231     /** Instruction used to signify that there is no *real* instruction in buffer slot */
 232     DynInstPtr dummyBufferInst;
 233
 234     /** Used by resources to signify a denied access to a resource. */
 235     ResourceRequest *dummyReq;
 236
 237     /** Identifies the resource id that identifies a fetch
 238      * access unit.
 239      */
 240     unsigned fetchPortIdx;
 241
 242     /** Identifies the resource id that identifies a ITB       */
 243     unsigned itbIdx;
 244
 245     /** Identifies the resource id that identifies a data
 246      * access unit.
 247      */
 248     unsigned dataPortIdx;
 249
 250     /** Identifies the resource id that identifies a DTB       */
 251     unsigned dtbIdx;
 252
 253     /** The Pipeline Stages for the CPU */
 254     PipelineStage *pipelineStage[ThePipeline::NumStages];
 255
 256     /** Program Counters */
 257     TheISA::IntReg PC[ThePipeline::MaxThreads];
 258     TheISA::IntReg nextPC[ThePipeline::MaxThreads];
 259     TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
 260
 261     /** The Register File for the CPU */
 262     union {
 263         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 264         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 265     } floatRegs;
 266     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 267
 268     /** ISA state */
 269     TheISA::ISA isa[ThePipeline::MaxThreads];
 270
 271     /** Dependency Tracker for Integer & Floating Point Regs */
 272     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 273
 274     /** Global communication structure */
 275     TimeBuffer<TimeStruct> timeBuffer;
 276
 277     /** Communication structure that sits in between pipeline stages */
 278     StageQueue *stageQueue[ThePipeline::NumStages-1];
 279
 280     TheISA::TLB *getITBPtr();
 281     TheISA::TLB *getDTBPtr();
 282
 283   public:
 284
 285     /** Registers statistics. */
 286     void regStats();
 287
 288     /** Ticks CPU, calling tick() on each stage, and checking the overall
 289      *  activity to see if the CPU should deschedule itself.
 290      */
 291     void tick();
 292
 293     /** Initialize the CPU */
 294     void init();
 295
 296     /** Reset State in the CPU */
 297     void reset();
 298
 299     /** Get a Memory Port */
 300     Port* getPort(const std::string &if_name, int idx = 0);
 301
 302 #if FULL_SYSTEM
 303     /** HW return from error interrupt. */
 304     Fault hwrei(ThreadID tid);
 305
 306     bool simPalCheck(int palFunc, ThreadID tid);
 307
 308     /** Returns the Fault for any valid interrupt. */
 309     Fault getInterrupts();
 310
 311     /** Processes any an interrupt fault. */
 312     void processInterrupts(Fault interrupt);
 313
 314     /** Halts the CPU. */
 315     void halt() { panic("Halt not implemented!\n"); }
 316
 317     /** Update the Virt and Phys ports of all ThreadContexts to
 318      * reflect change in memory connections. */
 319     void updateMemPorts();
 320
 321     /** Check if this address is a valid instruction address. */
 322     bool validInstAddr(Addr addr) { return true; }
 323
 324     /** Check if this address is a valid data address. */
 325     bool validDataAddr(Addr addr) { return true; }
 326 #endif
 327
 328     /** trap() - sets up a trap event on the cpuTraps to handle given fault.
 329      *  trapCPU() - Traps to handle given fault
 330      */
 331     void trap(Fault fault, ThreadID tid, int delay = 0);
 332     void trapCPU(Fault fault, ThreadID tid);
 333
 334     /** Setup CPU to insert a thread's context */
 335     void insertThread(ThreadID tid);
 336
 337     /** Remove all of a thread's context from CPU */
 338     void removeThread(ThreadID tid);
 339
 340     /** Add Thread to Active Threads List. */
 341     void activateContext(ThreadID tid, int delay = 0);
 342     void activateThread(ThreadID tid);
 343
 344     /** Remove Thread from Active Threads List */
 345     void suspendContext(ThreadID tid, int delay = 0);
 346     void suspendThread(ThreadID tid);
 347
 348     /** Remove Thread from Active Threads List &&
 349      *  Remove Thread Context from CPU.
 350      */
 351     void deallocateContext(ThreadID tid, int delay = 0);
 352     void deallocateThread(ThreadID tid);
 353     void deactivateThread(ThreadID tid);
 354
 355     PipelineStage* getPipeStage(int stage_num);
 356
 357     int
 358     contextId()
 359     {
 360         hack_once("return a bogus context id");
 361         return 0;
 362     }
 363
 364     /** Remove Thread from Active Threads List &&
 365      *  Remove Thread Context from CPU.
 366      */
 367     void haltContext(ThreadID tid, int delay = 0);
 368
 369     void removePipelineStalls(ThreadID tid);
 370
 371     void squashThreadInPipeline(ThreadID tid);
 372
 373     /// Notify the CPU to enable a virtual processor element.
 374     virtual void enableVirtProcElement(unsigned vpe);
 375     void enableVPEs(unsigned vpe);
 376
 377     /// Notify the CPU to disable a virtual processor element.
 378     virtual void disableVirtProcElement(ThreadID tid, unsigned vpe);
 379     void disableVPEs(ThreadID tid, unsigned vpe);
 380
 381     /// Notify the CPU that multithreading is enabled.
 382     virtual void enableMultiThreading(unsigned vpe);
 383     void enableThreads(unsigned vpe);
 384
 385     /// Notify the CPU that multithreading is disabled.
 386     virtual void disableMultiThreading(ThreadID tid, unsigned vpe);
 387     void disableThreads(ThreadID tid, unsigned vpe);
 388
 389     /** Activate a Thread When CPU Resources are Available. */
 390     void activateWhenReady(ThreadID tid);
 391
 392     /** Add or Remove a Thread Context in the CPU. */
 393     void doContextSwitch();
 394
 395     /** Update The Order In Which We Process Threads. */
 396     void updateThreadPriority();
 397
 398     /** Switches a Pipeline Stage to Active. (Unused currently) */
 399     void switchToActive(int stage_idx)
 400     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 401
 402     /** Get the current instruction sequence number, and increment it. */
 403     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 404     { return globalSeqNum[tid]++; }
 405
 406     /** Get the current instruction sequence number, and increment it. */
 407     InstSeqNum nextInstSeqNum(ThreadID tid)
 408     { return globalSeqNum[tid]; }
 409
 410     /** Increment Instruction Sequence Number */
 411     void incrInstSeqNum(ThreadID tid)
 412     { globalSeqNum[tid]++; }
 413
 414     /** Set Instruction Sequence Number */
 415     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 416     {
 417         globalSeqNum[tid] = seq_num;
 418     }
 419
 420     /** Get & Update Next Event Number */
 421     InstSeqNum getNextEventNum()
 422     {
 423         return cpuEventNum++;
 424     }
 425
 426     /** Register file accessors  */
 427     uint64_t readIntReg(int reg_idx, ThreadID tid);
 428
 429     FloatReg readFloatReg(int reg_idx, ThreadID tid);
 430
 431     FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
 432
 433     void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
 434
 435     void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
 436
 437     void setFloatRegBits(int reg_idx, FloatRegBits val,  ThreadID tid);
 438
 439     /** Reads a miscellaneous register. */
 440     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 441
 442     /** Reads a misc. register, including any side effects the read
 443      * might have as defined by the architecture.
 444      */
 445     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 446
 447     /** Sets a miscellaneous register. */
 448     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 449                             ThreadID tid = 0);
 450
 451     /** Sets a misc. register, including any side effects the write
 452      * might have as defined by the architecture.
 453      */
 454     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 455
 456     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 457      *  target thread
 458      */
 459     uint64_t readRegOtherThread(unsigned misc_reg,
 460                                 ThreadID tid = InvalidThreadID);
 461
 462     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 463      * target thread
 464      */
 465     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 466                            ThreadID tid);
 467
 468     /** Reads the commit PC of a specific thread. */
 469     uint64_t readPC(ThreadID tid);
 470
 471     /** Sets the commit PC of a specific thread. */
 472     void setPC(Addr new_PC, ThreadID tid);
 473
 474     /** Reads the next PC of a specific thread. */
 475     uint64_t readNextPC(ThreadID tid);
 476
 477     /** Sets the next PC of a specific thread. */
 478     void setNextPC(uint64_t val, ThreadID tid);
 479
 480     /** Reads the next NPC of a specific thread. */
 481     uint64_t readNextNPC(ThreadID tid);
 482
 483     /** Sets the next NPC of a specific thread. */
 484     void setNextNPC(uint64_t val, ThreadID tid);
 485
 486     /** Function to add instruction onto the head of the list of the
 487      *  instructions.  Used when new instructions are fetched.
 488      */
 489     ListIt addInst(DynInstPtr &inst);
 490
 491     /** Function to tell the CPU that an instruction has completed. */
 492     void instDone(DynInstPtr inst, ThreadID tid);
 493
 494     /** Add Instructions to the CPU Remove List*/
 495     void addToRemoveList(DynInstPtr &inst);
 496
 497     /** Remove an instruction from CPU */
 498     void removeInst(DynInstPtr &inst);
 499
 500     /** Remove all instructions younger than the given sequence number. */
 501     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 502
 503     /** Removes the instruction pointed to by the iterator. */
 504     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 505
 506     /** Cleans up all instructions on the instruction remove list. */
 507     void cleanUpRemovedInsts();
 508
 509     /** Cleans up all instructions on the request remove list. */
 510     void cleanUpRemovedReqs();
 511
 512     /** Cleans up all instructions on the CPU event remove list. */
 513     void cleanUpRemovedEvents();
 514
 515     /** Debug function to print all instructions on the list. */
 516     void dumpInsts();
 517
 518     /** Forwards an instruction read to the appropriate data
 519      *  resource (indexes into Resource Pool thru "dataPortIdx")
 520      */
 521     template <class T>
 522     Fault read(DynInstPtr inst, Addr addr, T &data, unsigned flags);
 523
 524     /** Forwards an instruction write. to the appropriate data
 525      *  resource (indexes into Resource Pool thru "dataPortIdx")
 526      */
 527     template <class T>
 528     Fault write(DynInstPtr inst, T data, Addr addr, unsigned flags,
 529                 uint64_t *write_res = NULL);
 530
 531     /** Forwards an instruction prefetch to the appropriate data
 532      *  resource (indexes into Resource Pool thru "dataPortIdx")
 533      */
 534     void prefetch(DynInstPtr inst);
 535
 536     /** Forwards an instruction writeHint to the appropriate data
 537      *  resource (indexes into Resource Pool thru "dataPortIdx")
 538      */
 539     void writeHint(DynInstPtr inst);
 540
 541     /** Executes a syscall.*/
 542     void syscall(int64_t callnum, ThreadID tid);
 543
 544   public:
 545     /** Per-Thread List of all the instructions in flight. */
 546     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 547
 548     /** List of all the instructions that will be removed at the end of this
 549      *  cycle.
 550      */
 551     std::queue<ListIt> removeList;
 552
 553     /** List of all the resource requests that will be removed at the end of this
 554      *  cycle.
 555      */
 556     std::queue<ResourceRequest*> reqRemoveList;
 557
 558     /** List of all the cpu event requests that will be removed at the end of
 559      *  the current cycle.
 560      */
 561     std::queue<Event*> cpuEventRemoveList;
 562
 563     /** Records if instructions need to be removed this cycle due to
 564      *  being retired or squashed.
 565      */
 566     bool removeInstsThisCycle;
 567
 568     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 569      * execution unit know, NOT to execute while the instruction is active.
 570      */
 571     bool nonSpecInstActive[ThePipeline::MaxThreads];
 572
 573     /** Instruction Seq. Num of current non-speculative instruction. */
 574     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 575
 576     /** Instruction Seq. Num of last instruction squashed in pipeline */
 577     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 578
 579     /** Last Cycle that the CPU squashed instruction end. */
 580     Tick lastSquashCycle[ThePipeline::MaxThreads];
 581
 582     std::list<ThreadID> fetchPriorityList;
 583
 584   protected:
 585     /** Active Threads List */
 586     std::list<ThreadID> activeThreads;
 587
 588     /** Current Threads List */
 589     std::list<ThreadID> currentThreads;
 590
 591     /** Suspended Threads List */
 592     std::list<ThreadID> suspendedThreads;
 593
 594     /** Thread Status Functions (Unused Currently) */
 595     bool isThreadInCPU(ThreadID tid);
 596     bool isThreadActive(ThreadID tid);
 597     bool isThreadSuspended(ThreadID tid);
 598     void addToCurrentThreads(ThreadID tid);
 599     void removeFromCurrentThreads(ThreadID tid);
 600
 601   private:
 602     /** The activity recorder; used to tell if the CPU has any
 603      * activity remaining or if it can go to idle and deschedule
 604      * itself.
 605      */
 606     ActivityRecorder activityRec;
 607
 608   public:
 609     /** Number of Active Threads in the CPU */
 610     ThreadID numActiveThreads() { return activeThreads.size(); }
 611
 612     /** Records that there was time buffer activity this cycle. */
 613     void activityThisCycle() { activityRec.activity(); }
 614
 615     /** Changes a stage's status to active within the activity recorder. */
 616     void activateStage(const int idx)
 617     { activityRec.activateStage(idx); }
 618
 619     /** Changes a stage's status to inactive within the activity recorder. */
 620     void deactivateStage(const int idx)
 621     { activityRec.deactivateStage(idx); }
 622
 623     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 624     void wakeCPU();
 625
 626 #if FULL_SYSTEM
 627     virtual void wakeup();
 628 #endif
 629
 630     /** Gets a free thread id. Use if thread ids change across system. */
 631     ThreadID getFreeTid();
 632
 633     // LL/SC debug functionality
 634     unsigned stCondFails;
 635     unsigned readStCondFailures() { return stCondFails; }
 636     unsigned setStCondFailures(unsigned st_fails) { return stCondFails = st_fails; }
 637
 638     /** Returns a pointer to a thread context. */
 639     ThreadContext *tcBase(ThreadID tid = 0)
 640     {
 641         return thread[tid]->getTC();
 642     }
 643
 644     /** Count the Total Instructions Committed in the CPU. */
 645     virtual Counter totalInstructions() const
 646     {
 647         Counter total(0);
 648
 649         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 650             total += thread[tid]->numInst;
 651
 652         return total;
 653     }
 654
 655 #if FULL_SYSTEM
 656     /** Pointer to the system. */
 657     System *system;
 658
 659     /** Pointer to physical memory. */
 660     PhysicalMemory *physmem;
 661 #endif
 662
 663     /** The global sequence number counter. */
 664     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 665
 666     /** The global event number counter. */
 667     InstSeqNum cpuEventNum;
 668
 669     /** Counter of how many stages have completed switching out. */
 670     int switchCount;
 671
 672     /** Pointers to all of the threads in the CPU. */
 673     std::vector<Thread *> thread;
 674
 675     /** Pointer to the icache interface. */
 676     MemInterface *icacheInterface;
 677
 678     /** Pointer to the dcache interface. */
 679     MemInterface *dcacheInterface;
 680
 681     /** Whether or not the CPU should defer its registration. */
 682     bool deferRegistration;
 683
 684     /** Per-Stage Instruction Tracing */
 685     bool stageTracing;
 686
 687     /** Is there a context switch pending? */
 688     bool contextSwitch;
 689
 690     /** Threads Scheduled to Enter CPU */
 691     std::list<int> cpuWaitList;
 692
 693     /** The cycle that the CPU was last running, used for statistics. */
 694     Tick lastRunningCycle;
 695
 696     /** Number of Virtual Processors the CPU can process */
 697     unsigned numVirtProcs;
 698
 699     /** Update Thread , used for statistic purposes*/
 700     inline void tickThreadStats();
 701
 702     /** Per-Thread Tick */
 703     Stats::Vector threadCycles;
 704
 705     /** Tick for SMT */
 706     Stats::Scalar smtCycles;
 707
 708     /** Stat for total number of times the CPU is descheduled. */
 709     Stats::Scalar timesIdled;
 710
 711     /** Stat for total number of cycles the CPU spends descheduled. */
 712     Stats::Scalar idleCycles;
 713
 714     /** Stat for the number of committed instructions per thread. */
 715     Stats::Vector committedInsts;
 716
 717     /** Stat for the number of committed instructions per thread. */
 718     Stats::Vector smtCommittedInsts;
 719
 720     /** Stat for the total number of committed instructions. */
 721     Stats::Scalar totalCommittedInsts;
 722
 723     /** Stat for the CPI per thread. */
 724     Stats::Formula cpi;
 725
 726     /** Stat for the SMT-CPI per thread. */
 727     Stats::Formula smtCpi;
 728
 729     /** Stat for the total CPI. */
 730     Stats::Formula totalCpi;
 731
 732     /** Stat for the IPC per thread. */
 733     Stats::Formula ipc;
 734
 735     /** Stat for the total IPC. */
 736     Stats::Formula smtIpc;
 737
 738     /** Stat for the total IPC. */
 739     Stats::Formula totalIpc;
 740 };
 741
 742 #endif // __CPU_O3_CPU_HH__