src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2012-2013 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2007 MIPS Technologies, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Korey Sewell
  42  *
  43  */
  44
  45 #ifndef __CPU_INORDER_CPU_HH__
  46 #define __CPU_INORDER_CPU_HH__
  47
  48 #include <iostream>
  49 #include <list>
  50 #include <queue>
  51 #include <set>
  52 #include <vector>
  53
  54 #include "arch/isa_traits.hh"
  55 #include "arch/registers.hh"
  56 #include "arch/types.hh"
  57 #include "base/statistics.hh"
  58 #include "base/types.hh"
  59 #include "config/the_isa.hh"
  60 #include "cpu/inorder/inorder_dyn_inst.hh"
  61 #include "cpu/inorder/pipeline_stage.hh"
  62 #include "cpu/inorder/pipeline_traits.hh"
  63 #include "cpu/inorder/reg_dep_map.hh"
  64 #include "cpu/inorder/thread_state.hh"
  65 #include "cpu/o3/dep_graph.hh"
  66 #include "cpu/o3/rename_map.hh"
  67 #include "cpu/activity.hh"
  68 #include "cpu/base.hh"
  69 #include "cpu/reg_class.hh"
  70 #include "cpu/simple_thread.hh"
  71 #include "cpu/timebuf.hh"
  72 #include "mem/packet.hh"
  73 #include "mem/port.hh"
  74 #include "mem/request.hh"
  75 #include "sim/eventq.hh"
  76 #include "sim/process.hh"
  77
  78 class CacheUnit;
  79 class ThreadContext;
  80 class MemInterface;
  81 class MemObject;
  82 class Process;
  83 class ResourcePool;
  84
  85 class InOrderCPU : public BaseCPU
  86 {
  87
  88   protected:
  89     typedef ThePipeline::Params Params;
  90     typedef InOrderThreadState Thread;
  91
  92    //ISA TypeDefs
  93     typedef TheISA::IntReg IntReg;
  94     typedef TheISA::FloatReg FloatReg;
  95     typedef TheISA::FloatRegBits FloatRegBits;
  96     typedef TheISA::CCReg CCReg;
  97     typedef TheISA::MiscReg MiscReg;
  98     typedef TheISA::RegIndex RegIndex;
  99
 100     //DynInstPtr TypeDefs
 101     typedef ThePipeline::DynInstPtr DynInstPtr;
 102     typedef std::list<DynInstPtr>::iterator ListIt;
 103
 104     //TimeBuffer TypeDefs
 105     typedef TimeBuffer<InterStageStruct> StageQueue;
 106
 107     friend class Resource;
 108
 109   public:
 110     /** Constructs a CPU with the given parameters. */
 111     InOrderCPU(Params *params);
 112     /* Destructor */
 113     ~InOrderCPU();
 114
 115     void verifyMemoryMode() const;
 116
 117     /** Return a reference to the data port. */
 118     virtual MasterPort &getDataPort() { return dataPort; }
 119
 120     /** Return a reference to the instruction port. */
 121     virtual MasterPort &getInstPort() { return instPort; }
 122
 123     /** CPU ID */
 124     int cpu_id;
 125
 126     // SE Mode ASIDs
 127     ThreadID asid[ThePipeline::MaxThreads];
 128
 129     /** Type of core that this is */
 130     std::string coreType;
 131
 132     // Only need for SE MODE
 133     enum ThreadModel {
 134         Single,
 135         SMT,
 136         SwitchOnCacheMiss
 137     };
 138
 139     ThreadModel threadModel;
 140
 141     int readCpuId() { return cpu_id; }
 142
 143     void setCpuId(int val) { cpu_id = val; }
 144
 145     Params *cpu_params;
 146
 147   public:
 148     enum Status {
 149         Running,
 150         Idle,
 151         Halted,
 152         Blocked,
 153         SwitchedOut
 154     };
 155
 156     /** Overall CPU status. */
 157     Status _status;
 158   private:
 159
 160     /**
 161      * CachePort class for the in-order CPU, interacting with a
 162      * specific CacheUnit in the pipeline.
 163      */
 164     class CachePort : public MasterPort
 165     {
 166
 167       private:
 168         /** Pointer to cache unit */
 169         CacheUnit *cacheUnit;
 170
 171       public:
 172         /** Default constructor. */
 173         CachePort(CacheUnit *_cacheUnit, const std::string& name);
 174
 175       protected:
 176
 177         /** Timing version of receive */
 178         bool recvTimingResp(PacketPtr pkt);
 179
 180         /** Handles doing a retry of a failed timing request. */
 181         void recvRetry();
 182
 183         /** Ignoring snoops for now. */
 184         void recvTimingSnoopReq(PacketPtr pkt) { }
 185     };
 186
 187     /** Define TickEvent for the CPU */
 188     class TickEvent : public Event
 189     {
 190       private:
 191         /** Pointer to the CPU. */
 192         InOrderCPU *cpu;
 193
 194       public:
 195         /** Constructs a tick event. */
 196         TickEvent(InOrderCPU *c);
 197
 198         /** Processes a tick event, calling tick() on the CPU. */
 199         void process();
 200
 201         /** Returns the description of the tick event. */
 202         const char *description() const;
 203     };
 204
 205     /** The tick event used for scheduling CPU ticks. */
 206     TickEvent tickEvent;
 207
 208     /** Schedule tick event, regardless of its current state. */
 209     void scheduleTickEvent(Cycles delay)
 210     {
 211         assert(!tickEvent.scheduled() || tickEvent.squashed());
 212         reschedule(&tickEvent, clockEdge(delay), true);
 213     }
 214
 215     /** Unschedule tick event, regardless of its current state. */
 216     void unscheduleTickEvent()
 217     {
 218         if (tickEvent.scheduled())
 219             tickEvent.squash();
 220     }
 221
 222   public:
 223     // List of Events That can be scheduled from
 224     // within the CPU.
 225     // NOTE(1): The Resource Pool also uses this event list
 226     // to schedule events broadcast to all resources interfaces
 227     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 228     // pool event.
 229     enum CPUEventType {
 230         ActivateThread,
 231         ActivateNextReadyThread,
 232         DeactivateThread,
 233         HaltThread,
 234         SuspendThread,
 235         Trap,
 236         Syscall,
 237         SquashFromMemStall,
 238         UpdatePCs,
 239         NumCPUEvents
 240     };
 241
 242     static std::string eventNames[NumCPUEvents];
 243
 244     enum CPUEventPri {
 245         InOrderCPU_Pri                 = Event::CPU_Tick_Pri,
 246         Syscall_Pri                    = Event::CPU_Tick_Pri + 9,
 247         ActivateNextReadyThread_Pri    = Event::CPU_Tick_Pri + 10
 248     };
 249
 250     /** Define CPU Event */
 251     class CPUEvent : public Event
 252     {
 253       protected:
 254         InOrderCPU *cpu;
 255
 256       public:
 257         CPUEventType cpuEventType;
 258         ThreadID tid;
 259         DynInstPtr inst;
 260         Fault fault;
 261         unsigned vpe;
 262         short syscall_num;
 263
 264       public:
 265         /** Constructs a CPU event. */
 266         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 267                  ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
 268
 269         /** Set Type of Event To Be Scheduled */
 270         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 271                       DynInstPtr _inst)
 272         {
 273             fault = _fault;
 274             cpuEventType = e_type;
 275             tid = _tid;
 276             inst = _inst;
 277             vpe = 0;
 278         }
 279
 280         /** Processes a CPU event. */
 281         void process();
 282
 283         /** Returns the description of the CPU event. */
 284         const char *description() const;
 285
 286         /** Schedule Event */
 287         void scheduleEvent(Cycles delay);
 288
 289         /** Unschedule This Event */
 290         void unscheduleEvent();
 291     };
 292
 293     /** Schedule a CPU Event */
 294     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 295                           DynInstPtr inst, Cycles delay = Cycles(0),
 296                           CPUEventPri event_pri = InOrderCPU_Pri);
 297
 298   public:
 299
 300     /** Width (processing bandwidth) of each stage */
 301     int stageWidth;
 302
 303     /** Interface between the CPU and CPU resources. */
 304     ResourcePool *resPool;
 305
 306     /** Instruction used to signify that there is no *real* instruction in
 307         buffer slot */
 308     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 309     DynInstPtr dummyBufferInst;
 310     DynInstPtr dummyReqInst;
 311     DynInstPtr dummyTrapInst[ThePipeline::MaxThreads];
 312
 313     /** Used by resources to signify a denied access to a resource. */
 314     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 315
 316     /** The Pipeline Stages for the CPU */
 317     PipelineStage *pipelineStage[ThePipeline::NumStages];
 318
 319     /** Program Counters */
 320     TheISA::PCState pc[ThePipeline::MaxThreads];
 321
 322     /** Last Committed PC */
 323     TheISA::PCState lastCommittedPC[ThePipeline::MaxThreads];
 324
 325     /** The Register File for the CPU */
 326     union {
 327         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 328         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 329     } floatRegs;
 330     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 331 #ifdef ISA_HAS_CC_REGS
 332     TheISA::CCReg ccRegs[ThePipeline::MaxThreads][TheISA::NumCCRegs];
 333 #endif
 334
 335     /** ISA state */
 336     std::vector<TheISA::ISA *> isa;
 337
 338     /** Dependency Tracker for Integer & Floating Point Regs */
 339     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 340
 341     /** Global communication structure */
 342     TimeBuffer<TimeStruct> timeBuffer;
 343
 344     /** Communication structure that sits in between pipeline stages */
 345     StageQueue *stageQueue[ThePipeline::NumStages-1];
 346
 347     TheISA::TLB *getITBPtr();
 348     TheISA::TLB *getDTBPtr();
 349
 350     TheISA::Decoder *getDecoderPtr(unsigned tid);
 351
 352     /** Accessor Type for the SkedCache */
 353     typedef uint32_t SkedID;
 354
 355     /** Cache of Instruction Schedule using the instruction's name as a key */
 356     static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
 357
 358     typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 359
 360     /** Initialized to last iterator in map, signifying a invalid entry
 361         on map searches
 362     */
 363     SkedCacheIt endOfSkedIt;
 364
 365     ThePipeline::RSkedPtr frontEndSked;
 366     ThePipeline::RSkedPtr faultSked;
 367
 368     /** Add a new instruction schedule to the schedule cache */
 369     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 370     {
 371         SkedID sked_id = genSkedID(inst);
 372         assert(skedCache.find(sked_id) == skedCache.end());
 373         skedCache[sked_id] = inst_sked;
 374     }
 375
 376
 377     /** Find a instruction schedule */
 378     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 379     {
 380         SkedID sked_id = genSkedID(inst);
 381         SkedCacheIt lookup_it = skedCache.find(sked_id);
 382
 383         if (lookup_it != endOfSkedIt) {
 384             return (*lookup_it).second;
 385         } else {
 386             return NULL;
 387         }
 388     }
 389
 390     static const uint8_t INST_OPCLASS                       = 26;
 391     static const uint8_t INST_LOAD                          = 25;
 392     static const uint8_t INST_STORE                         = 24;
 393     static const uint8_t INST_CONTROL                       = 23;
 394     static const uint8_t INST_NONSPEC                       = 22;
 395     static const uint8_t INST_DEST_REGS                     = 18;
 396     static const uint8_t INST_SRC_REGS                      = 14;
 397     static const uint8_t INST_SPLIT_DATA                    = 13;
 398
 399     inline SkedID genSkedID(DynInstPtr inst)
 400     {
 401         SkedID id = 0;
 402         id = (inst->opClass() << INST_OPCLASS) |
 403             (inst->isLoad() << INST_LOAD) |
 404             (inst->isStore() << INST_STORE) |
 405             (inst->isControl() << INST_CONTROL) |
 406             (inst->isNonSpeculative() << INST_NONSPEC) |
 407             (inst->numDestRegs() << INST_DEST_REGS) |
 408             (inst->numSrcRegs() << INST_SRC_REGS) |
 409             (inst->splitInst << INST_SPLIT_DATA);
 410         return id;
 411     }
 412
 413     ThePipeline::RSkedPtr createFrontEndSked();
 414     ThePipeline::RSkedPtr createFaultSked();
 415     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 416
 417     class StageScheduler {
 418       private:
 419         ThePipeline::RSkedPtr rsked;
 420         int stageNum;
 421         int nextTaskPriority;
 422
 423       public:
 424         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 425             : rsked(_rsked), stageNum(stage_num),
 426               nextTaskPriority(0)
 427         { }
 428
 429         void needs(int unit, int request) {
 430             rsked->push(new ScheduleEntry(
 431                             stageNum, nextTaskPriority++, unit, request
 432                             ));
 433         }
 434
 435         void needs(int unit, int request, int param) {
 436             rsked->push(new ScheduleEntry(
 437                             stageNum, nextTaskPriority++, unit, request, param
 438                             ));
 439         }
 440     };
 441
 442   private:
 443
 444     /** Data port. Note that it has to appear after the resPool. */
 445     CachePort dataPort;
 446
 447     /** Instruction port. Note that it has to appear after the resPool. */
 448     CachePort instPort;
 449
 450   public:
 451
 452     /** Registers statistics. */
 453     void regStats();
 454
 455     /** Ticks CPU, calling tick() on each stage, and checking the overall
 456      *  activity to see if the CPU should deschedule itself.
 457      */
 458     void tick();
 459
 460     /** Initialize the CPU */
 461     void init();
 462
 463     /** HW return from error interrupt. */
 464     Fault hwrei(ThreadID tid);
 465
 466     bool simPalCheck(int palFunc, ThreadID tid);
 467
 468     void checkForInterrupts();
 469
 470     /** Returns the Fault for any valid interrupt. */
 471     Fault getInterrupts();
 472
 473     /** Processes any an interrupt fault. */
 474     void processInterrupts(Fault interrupt);
 475
 476     /** Halts the CPU. */
 477     void halt() { panic("Halt not implemented!\n"); }
 478
 479     /** Check if this address is a valid instruction address. */
 480     bool validInstAddr(Addr addr) { return true; }
 481
 482     /** Check if this address is a valid data address. */
 483     bool validDataAddr(Addr addr) { return true; }
 484
 485     /** Schedule a syscall on the CPU */
 486     void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
 487                         Cycles delay = Cycles(0));
 488
 489     /** Executes a syscall.*/
 490     void syscall(int64_t callnum, ThreadID tid);
 491
 492     /** Schedule a trap on the CPU */
 493     void trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
 494                      Cycles delay = Cycles(0));
 495
 496     /** Perform trap to Handle Given Fault */
 497     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 498
 499     /** Schedule thread activation on the CPU */
 500     void activateContext(ThreadID tid, Cycles delay = Cycles(0));
 501
 502     /** Add Thread to Active Threads List. */
 503     void activateThread(ThreadID tid);
 504
 505     /** Activate Thread In Each Pipeline Stage */
 506     void activateThreadInPipeline(ThreadID tid);
 507
 508     /** Schedule Thread Activation from Ready List */
 509     void activateNextReadyContext(Cycles delay = Cycles(0));
 510
 511     /** Add Thread From Ready List to Active Threads List. */
 512     void activateNextReadyThread();
 513
 514     /** Schedule a thread deactivation on the CPU */
 515     void deactivateContext(ThreadID tid, Cycles delay = Cycles(0));
 516
 517     /** Remove from Active Thread List */
 518     void deactivateThread(ThreadID tid);
 519
 520     /** Schedule a thread suspension on the CPU */
 521   void suspendContext(ThreadID tid);
 522
 523     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 524     void suspendThread(ThreadID tid);
 525
 526     /** Schedule a thread halt on the CPU */
 527     void haltContext(ThreadID tid);
 528
 529     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 530      *  Threads List
 531      */
 532     void haltThread(ThreadID tid);
 533
 534     /** squashFromMemStall() - sets up a squash event
 535      *  squashDueToMemStall() - squashes pipeline
 536      *  @note: maybe squashContext/squashThread would be better?
 537      */
 538     void squashFromMemStall(DynInstPtr inst, ThreadID tid,
 539                             Cycles delay = Cycles(0));
 540     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 541
 542     void removePipelineStalls(ThreadID tid);
 543     void squashThreadInPipeline(ThreadID tid);
 544     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 545
 546     PipelineStage* getPipeStage(int stage_num);
 547
 548     int
 549     contextId()
 550     {
 551         hack_once("return a bogus context id");
 552         return 0;
 553     }
 554
 555     /** Update The Order In Which We Process Threads. */
 556     void updateThreadPriority();
 557
 558     /** Switches a Pipeline Stage to Active. (Unused currently) */
 559     void switchToActive(int stage_idx)
 560     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 561
 562     /** Get the current instruction sequence number, and increment it. */
 563     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 564     { return globalSeqNum[tid]++; }
 565
 566     /** Get the current instruction sequence number, and increment it. */
 567     InstSeqNum nextInstSeqNum(ThreadID tid)
 568     { return globalSeqNum[tid]; }
 569
 570     /** Increment Instruction Sequence Number */
 571     void incrInstSeqNum(ThreadID tid)
 572     { globalSeqNum[tid]++; }
 573
 574     /** Set Instruction Sequence Number */
 575     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 576     {
 577         globalSeqNum[tid] = seq_num;
 578     }
 579
 580     /** Get & Update Next Event Number */
 581     InstSeqNum getNextEventNum()
 582     {
 583 #ifdef DEBUG
 584         return cpuEventNum++;
 585 #else
 586         return 0;
 587 #endif
 588     }
 589
 590     /** Register file accessors  */
 591     uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
 592
 593     FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
 594
 595     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 596
 597     CCReg readCCReg(RegIndex reg_idx, ThreadID tid);
 598
 599     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 600
 601     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 602
 603     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 604
 605     void setCCReg(RegIndex reg_idx, CCReg val, ThreadID tid);
 606
 607     RegIndex flattenRegIdx(RegIndex reg_idx, RegClass &reg_type, ThreadID tid);
 608
 609     /** Reads a miscellaneous register. */
 610     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 611
 612     /** Reads a misc. register, including any side effects the read
 613      * might have as defined by the architecture.
 614      */
 615     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 616
 617     /** Sets a miscellaneous register. */
 618     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 619                             ThreadID tid = 0);
 620
 621     /** Sets a misc. register, including any side effects the write
 622      * might have as defined by the architecture.
 623      */
 624     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 625
 626     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 627      *  target thread
 628      */
 629     uint64_t readRegOtherThread(unsigned misc_reg,
 630                                 ThreadID tid = InvalidThreadID);
 631
 632     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 633      * target thread
 634      */
 635     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 636                            ThreadID tid);
 637
 638     /** Reads the commit PC of a specific thread. */
 639     TheISA::PCState
 640     pcState(ThreadID tid)
 641     {
 642         return pc[tid];
 643     }
 644
 645     /** Sets the commit PC of a specific thread. */
 646     void
 647     pcState(const TheISA::PCState &newPC, ThreadID tid)
 648     {
 649         pc[tid] = newPC;
 650     }
 651
 652     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 653     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 654     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 655
 656     /** Function to add instruction onto the head of the list of the
 657      *  instructions.  Used when new instructions are fetched.
 658      */
 659     ListIt addInst(DynInstPtr inst);
 660
 661     /** Find instruction on instruction list */
 662     ListIt findInst(InstSeqNum seq_num, ThreadID tid);
 663
 664     /** Function to tell the CPU that an instruction has completed. */
 665     void instDone(DynInstPtr inst, ThreadID tid);
 666
 667     /** Add Instructions to the CPU Remove List*/
 668     void addToRemoveList(DynInstPtr inst);
 669
 670     /** Remove an instruction from CPU */
 671     void removeInst(DynInstPtr inst);
 672
 673     /** Remove all instructions younger than the given sequence number. */
 674     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 675
 676     /** Removes the instruction pointed to by the iterator. */
 677     inline void squashInstIt(const ListIt inst_it, ThreadID tid);
 678
 679     /** Cleans up all instructions on the instruction remove list. */
 680     void cleanUpRemovedInsts();
 681
 682     /** Cleans up all events on the CPU event remove list. */
 683     void cleanUpRemovedEvents();
 684
 685     /** Debug function to print all instructions on the list. */
 686     void dumpInsts();
 687
 688     /** Forwards an instruction read to the appropriate data
 689      *  resource (indexes into Resource Pool thru "dataPortIdx")
 690      */
 691     Fault read(DynInstPtr inst, Addr addr,
 692                uint8_t *data, unsigned size, unsigned flags);
 693
 694     /** Forwards an instruction write. to the appropriate data
 695      *  resource (indexes into Resource Pool thru "dataPortIdx")
 696      */
 697     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 698                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 699
 700   public:
 701     /** Per-Thread List of all the instructions in flight. */
 702     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 703
 704     /** List of all the instructions that will be removed at the end of this
 705      *  cycle.
 706      */
 707     std::queue<ListIt> removeList;
 708
 709     bool trapPending[ThePipeline::MaxThreads];
 710
 711     /** List of all the cpu event requests that will be removed at the end of
 712      *  the current cycle.
 713      */
 714     std::queue<Event*> cpuEventRemoveList;
 715
 716     /** Records if instructions need to be removed this cycle due to
 717      *  being retired or squashed.
 718      */
 719     bool removeInstsThisCycle;
 720
 721     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 722      * execution unit know, NOT to execute while the instruction is active.
 723      */
 724     bool nonSpecInstActive[ThePipeline::MaxThreads];
 725
 726     /** Instruction Seq. Num of current non-speculative instruction. */
 727     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 728
 729     /** Instruction Seq. Num of last instruction squashed in pipeline */
 730     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 731
 732     /** Last Cycle that the CPU squashed instruction end. */
 733     Tick lastSquashCycle[ThePipeline::MaxThreads];
 734
 735     std::list<ThreadID> fetchPriorityList;
 736
 737   protected:
 738     /** Active Threads List */
 739     std::list<ThreadID> activeThreads;
 740
 741     /** Ready Threads List */
 742     std::list<ThreadID> readyThreads;
 743
 744     /** Suspended Threads List */
 745     std::list<ThreadID> suspendedThreads;
 746
 747     /** Halted Threads List */
 748     std::list<ThreadID> haltedThreads;
 749
 750     /** Thread Status Functions */
 751     bool isThreadActive(ThreadID tid);
 752     bool isThreadReady(ThreadID tid);
 753     bool isThreadSuspended(ThreadID tid);
 754
 755   private:
 756     /** The activity recorder; used to tell if the CPU has any
 757      * activity remaining or if it can go to idle and deschedule
 758      * itself.
 759      */
 760     ActivityRecorder activityRec;
 761
 762   public:
 763     /** Number of Active Threads in the CPU */
 764     ThreadID numActiveThreads() { return activeThreads.size(); }
 765
 766     /** Thread id of active thread
 767      *  Only used for SwitchOnCacheMiss model.
 768      *  Assumes only 1 thread active
 769      */
 770     ThreadID activeThreadId()
 771     {
 772         if (numActiveThreads() > 0)
 773             return activeThreads.front();
 774         else
 775             return InvalidThreadID;
 776     }
 777
 778
 779     /** Records that there was time buffer activity this cycle. */
 780     void activityThisCycle() { activityRec.activity(); }
 781
 782     /** Changes a stage's status to active within the activity recorder. */
 783     void activateStage(const int idx)
 784     { activityRec.activateStage(idx); }
 785
 786     /** Changes a stage's status to inactive within the activity recorder. */
 787     void deactivateStage(const int idx)
 788     { activityRec.deactivateStage(idx); }
 789
 790     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 791     void wakeCPU();
 792
 793     virtual void wakeup();
 794
 795     /* LL/SC debug functionality
 796     unsigned stCondFails;
 797
 798     unsigned readStCondFailures()
 799     { return stCondFails; }
 800
 801     unsigned setStCondFailures(unsigned st_fails)
 802     { return stCondFails = st_fails; }
 803     */
 804
 805     /** Returns a pointer to a thread context. */
 806     ThreadContext *tcBase(ThreadID tid = 0)
 807     {
 808         return thread[tid]->getTC();
 809     }
 810
 811     /** Count the Total Instructions Committed in the CPU. */
 812     virtual Counter totalInsts() const
 813     {
 814         Counter total(0);
 815
 816         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 817             total += thread[tid]->numInst;
 818
 819         return total;
 820     }
 821
 822     /** Count the Total Ops Committed in the CPU. */
 823     virtual Counter totalOps() const
 824     {
 825         Counter total(0);
 826
 827         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 828             total += thread[tid]->numOp;
 829
 830         return total;
 831     }
 832
 833     /** Pointer to the system. */
 834     System *system;
 835
 836     /** The global sequence number counter. */
 837     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 838
 839 #ifdef DEBUG
 840     /** The global event number counter. */
 841     InstSeqNum cpuEventNum;
 842
 843     /** Number of resource requests active in CPU **/
 844     unsigned resReqCount;
 845 #endif
 846
 847     Addr lockAddr;
 848
 849     /** Temporary fix for the lock flag, works in the UP case. */
 850     bool lockFlag;
 851
 852     /** Counter of how many stages have completed draining */
 853     int drainCount;
 854
 855     /** Pointers to all of the threads in the CPU. */
 856     std::vector<Thread *> thread;
 857
 858     /** Per-Stage Instruction Tracing */
 859     bool stageTracing;
 860
 861     /** The cycle that the CPU was last running, used for statistics. */
 862     Tick lastRunningCycle;
 863
 864     void updateContextSwitchStats();
 865     unsigned instsPerSwitch;
 866     Stats::Average instsPerCtxtSwitch;
 867     Stats::Scalar numCtxtSwitches;
 868
 869     /** Update Thread , used for statistic purposes*/
 870     inline void tickThreadStats();
 871
 872     /** Per-Thread Tick */
 873     Stats::Vector threadCycles;
 874
 875     /** Tick for SMT */
 876     Stats::Scalar smtCycles;
 877
 878     /** Stat for total number of times the CPU is descheduled. */
 879     Stats::Scalar timesIdled;
 880
 881     /** Stat for total number of cycles the CPU spends descheduled or no
 882      *  stages active.
 883      */
 884     Stats::Scalar idleCycles;
 885
 886     /** Stat for total number of cycles the CPU is active. */
 887     Stats::Scalar runCycles;
 888
 889     /** Percentage of cycles a stage was active */
 890     Stats::Formula activity;
 891
 892     /** Instruction Mix Stats */
 893     Stats::Scalar comLoads;
 894     Stats::Scalar comStores;
 895     Stats::Scalar comBranches;
 896     Stats::Scalar comNops;
 897     Stats::Scalar comNonSpec;
 898     Stats::Scalar comInts;
 899     Stats::Scalar comFloats;
 900
 901     /** Stat for the number of committed instructions per thread. */
 902     Stats::Vector committedInsts;
 903
 904     /** Stat for the number of committed ops per thread. */
 905     Stats::Vector committedOps;
 906
 907     /** Stat for the number of committed instructions per thread. */
 908     Stats::Vector smtCommittedInsts;
 909
 910     /** Stat for the total number of committed instructions. */
 911     Stats::Scalar totalCommittedInsts;
 912
 913     /** Stat for the CPI per thread. */
 914     Stats::Formula cpi;
 915
 916     /** Stat for the SMT-CPI per thread. */
 917     Stats::Formula smtCpi;
 918
 919     /** Stat for the total CPI. */
 920     Stats::Formula totalCpi;
 921
 922     /** Stat for the IPC per thread. */
 923     Stats::Formula ipc;
 924
 925     /** Stat for the total IPC. */
 926     Stats::Formula smtIpc;
 927
 928     /** Stat for the total IPC. */
 929     Stats::Formula totalIpc;
 930 };
 931
 932 #endif // __CPU_O3_CPU_HH__