src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007 MIPS Technologies, Inc.
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Korey Sewell
  41  *
  42  */
  43
  44 #ifndef __CPU_INORDER_CPU_HH__
  45 #define __CPU_INORDER_CPU_HH__
  46
  47 #include <iostream>
  48 #include <list>
  49 #include <queue>
  50 #include <set>
  51 #include <vector>
  52
  53 #include "arch/isa_traits.hh"
  54 #include "arch/registers.hh"
  55 #include "arch/types.hh"
  56 #include "base/statistics.hh"
  57 #include "base/types.hh"
  58 #include "config/the_isa.hh"
  59 #include "cpu/inorder/inorder_dyn_inst.hh"
  60 #include "cpu/inorder/pipeline_stage.hh"
  61 #include "cpu/inorder/pipeline_traits.hh"
  62 #include "cpu/inorder/reg_dep_map.hh"
  63 #include "cpu/inorder/thread_state.hh"
  64 #include "cpu/o3/dep_graph.hh"
  65 #include "cpu/o3/rename_map.hh"
  66 #include "cpu/activity.hh"
  67 #include "cpu/base.hh"
  68 #include "cpu/simple_thread.hh"
  69 #include "cpu/timebuf.hh"
  70 #include "mem/packet.hh"
  71 #include "mem/port.hh"
  72 #include "mem/request.hh"
  73 #include "sim/eventq.hh"
  74 #include "sim/process.hh"
  75
  76 class CacheUnit;
  77 class ThreadContext;
  78 class MemInterface;
  79 class MemObject;
  80 class Process;
  81 class ResourcePool;
  82
  83 class InOrderCPU : public BaseCPU
  84 {
  85
  86   protected:
  87     typedef ThePipeline::Params Params;
  88     typedef InOrderThreadState Thread;
  89
  90    //ISA TypeDefs
  91     typedef TheISA::IntReg IntReg;
  92     typedef TheISA::FloatReg FloatReg;
  93     typedef TheISA::FloatRegBits FloatRegBits;
  94     typedef TheISA::MiscReg MiscReg;
  95     typedef TheISA::RegIndex RegIndex;
  96
  97     //DynInstPtr TypeDefs
  98     typedef ThePipeline::DynInstPtr DynInstPtr;
  99     typedef std::list<DynInstPtr>::iterator ListIt;
 100
 101     //TimeBuffer TypeDefs
 102     typedef TimeBuffer<InterStageStruct> StageQueue;
 103
 104     friend class Resource;
 105
 106   public:
 107     /** Constructs a CPU with the given parameters. */
 108     InOrderCPU(Params *params);
 109     /* Destructor */
 110     ~InOrderCPU();
 111
 112     /** Return a reference to the data port. */
 113     virtual CpuPort &getDataPort() { return dataPort; }
 114
 115     /** Return a reference to the instruction port. */
 116     virtual CpuPort &getInstPort() { return instPort; }
 117
 118     /** CPU ID */
 119     int cpu_id;
 120
 121     // SE Mode ASIDs
 122     ThreadID asid[ThePipeline::MaxThreads];
 123
 124     /** Type of core that this is */
 125     std::string coreType;
 126
 127     // Only need for SE MODE
 128     enum ThreadModel {
 129         Single,
 130         SMT,
 131         SwitchOnCacheMiss
 132     };
 133
 134     ThreadModel threadModel;
 135
 136     int readCpuId() { return cpu_id; }
 137
 138     void setCpuId(int val) { cpu_id = val; }
 139
 140     Params *cpu_params;
 141
 142   public:
 143     enum Status {
 144         Running,
 145         Idle,
 146         Halted,
 147         Blocked,
 148         SwitchedOut
 149     };
 150
 151     /** Overall CPU status. */
 152     Status _status;
 153   private:
 154
 155     /**
 156      * CachePort class for the in-order CPU, interacting with a
 157      * specific CacheUnit in the pipeline.
 158      */
 159     class CachePort : public CpuPort
 160     {
 161
 162       private:
 163         /** Pointer to cache unit */
 164         CacheUnit *cacheUnit;
 165
 166       public:
 167         /** Default constructor. */
 168         CachePort(CacheUnit *_cacheUnit, const std::string& name);
 169
 170       protected:
 171
 172         /** Timing version of receive */
 173         bool recvTimingResp(PacketPtr pkt);
 174
 175         /** Handles doing a retry of a failed timing request. */
 176         void recvRetry();
 177
 178         /** Ignoring snoops for now. */
 179         void recvTimingSnoopReq(PacketPtr pkt) { }
 180     };
 181
 182     /** Define TickEvent for the CPU */
 183     class TickEvent : public Event
 184     {
 185       private:
 186         /** Pointer to the CPU. */
 187         InOrderCPU *cpu;
 188
 189       public:
 190         /** Constructs a tick event. */
 191         TickEvent(InOrderCPU *c);
 192
 193         /** Processes a tick event, calling tick() on the CPU. */
 194         void process();
 195
 196         /** Returns the description of the tick event. */
 197         const char *description() const;
 198     };
 199
 200     /** The tick event used for scheduling CPU ticks. */
 201     TickEvent tickEvent;
 202
 203     /** Schedule tick event, regardless of its current state. */
 204     void scheduleTickEvent(Cycles delay)
 205     {
 206         assert(!tickEvent.scheduled() || tickEvent.squashed());
 207         reschedule(&tickEvent, clockEdge(delay), true);
 208     }
 209
 210     /** Unschedule tick event, regardless of its current state. */
 211     void unscheduleTickEvent()
 212     {
 213         if (tickEvent.scheduled())
 214             tickEvent.squash();
 215     }
 216
 217   public:
 218     // List of Events That can be scheduled from
 219     // within the CPU.
 220     // NOTE(1): The Resource Pool also uses this event list
 221     // to schedule events broadcast to all resources interfaces
 222     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 223     // pool event.
 224     enum CPUEventType {
 225         ActivateThread,
 226         ActivateNextReadyThread,
 227         DeactivateThread,
 228         HaltThread,
 229         SuspendThread,
 230         Trap,
 231         Syscall,
 232         SquashFromMemStall,
 233         UpdatePCs,
 234         NumCPUEvents
 235     };
 236
 237     static std::string eventNames[NumCPUEvents];
 238
 239     enum CPUEventPri {
 240         InOrderCPU_Pri                 = Event::CPU_Tick_Pri,
 241         Syscall_Pri                    = Event::CPU_Tick_Pri + 9,
 242         ActivateNextReadyThread_Pri    = Event::CPU_Tick_Pri + 10
 243     };
 244
 245     /** Define CPU Event */
 246     class CPUEvent : public Event
 247     {
 248       protected:
 249         InOrderCPU *cpu;
 250
 251       public:
 252         CPUEventType cpuEventType;
 253         ThreadID tid;
 254         DynInstPtr inst;
 255         Fault fault;
 256         unsigned vpe;
 257         short syscall_num;
 258
 259       public:
 260         /** Constructs a CPU event. */
 261         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 262                  ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
 263
 264         /** Set Type of Event To Be Scheduled */
 265         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 266                       DynInstPtr _inst)
 267         {
 268             fault = _fault;
 269             cpuEventType = e_type;
 270             tid = _tid;
 271             inst = _inst;
 272             vpe = 0;
 273         }
 274
 275         /** Processes a CPU event. */
 276         void process();
 277
 278         /** Returns the description of the CPU event. */
 279         const char *description() const;
 280
 281         /** Schedule Event */
 282         void scheduleEvent(Cycles delay);
 283
 284         /** Unschedule This Event */
 285         void unscheduleEvent();
 286     };
 287
 288     /** Schedule a CPU Event */
 289     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 290                           DynInstPtr inst, Cycles delay = Cycles(0),
 291                           CPUEventPri event_pri = InOrderCPU_Pri);
 292
 293   public:
 294
 295     /** Width (processing bandwidth) of each stage */
 296     int stageWidth;
 297
 298     /** Interface between the CPU and CPU resources. */
 299     ResourcePool *resPool;
 300
 301     /** Instruction used to signify that there is no *real* instruction in
 302         buffer slot */
 303     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 304     DynInstPtr dummyBufferInst;
 305     DynInstPtr dummyReqInst;
 306     DynInstPtr dummyTrapInst[ThePipeline::MaxThreads];
 307
 308     /** Used by resources to signify a denied access to a resource. */
 309     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 310
 311     /** The Pipeline Stages for the CPU */
 312     PipelineStage *pipelineStage[ThePipeline::NumStages];
 313
 314     /** Program Counters */
 315     TheISA::PCState pc[ThePipeline::MaxThreads];
 316
 317     /** Last Committed PC */
 318     TheISA::PCState lastCommittedPC[ThePipeline::MaxThreads];
 319
 320     /** The Register File for the CPU */
 321     union {
 322         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 323         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 324     } floatRegs;
 325     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 326
 327     /** ISA state */
 328     std::vector<TheISA::ISA *> isa;
 329
 330     /** Dependency Tracker for Integer & Floating Point Regs */
 331     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 332
 333     /** Register Types Used in Dependency Tracking */
 334     enum RegType { IntType, FloatType, MiscType, NumRegTypes};
 335
 336     /** Global communication structure */
 337     TimeBuffer<TimeStruct> timeBuffer;
 338
 339     /** Communication structure that sits in between pipeline stages */
 340     StageQueue *stageQueue[ThePipeline::NumStages-1];
 341
 342     TheISA::TLB *getITBPtr();
 343     TheISA::TLB *getDTBPtr();
 344
 345     TheISA::Decoder *getDecoderPtr(unsigned tid);
 346
 347     /** Accessor Type for the SkedCache */
 348     typedef uint32_t SkedID;
 349
 350     /** Cache of Instruction Schedule using the instruction's name as a key */
 351     static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
 352
 353     typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 354
 355     /** Initialized to last iterator in map, signifying a invalid entry
 356         on map searches
 357     */
 358     SkedCacheIt endOfSkedIt;
 359
 360     ThePipeline::RSkedPtr frontEndSked;
 361     ThePipeline::RSkedPtr faultSked;
 362
 363     /** Add a new instruction schedule to the schedule cache */
 364     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 365     {
 366         SkedID sked_id = genSkedID(inst);
 367         assert(skedCache.find(sked_id) == skedCache.end());
 368         skedCache[sked_id] = inst_sked;
 369     }
 370
 371
 372     /** Find a instruction schedule */
 373     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 374     {
 375         SkedID sked_id = genSkedID(inst);
 376         SkedCacheIt lookup_it = skedCache.find(sked_id);
 377
 378         if (lookup_it != endOfSkedIt) {
 379             return (*lookup_it).second;
 380         } else {
 381             return NULL;
 382         }
 383     }
 384
 385     static const uint8_t INST_OPCLASS                       = 26;
 386     static const uint8_t INST_LOAD                          = 25;
 387     static const uint8_t INST_STORE                         = 24;
 388     static const uint8_t INST_CONTROL                       = 23;
 389     static const uint8_t INST_NONSPEC                       = 22;
 390     static const uint8_t INST_DEST_REGS                     = 18;
 391     static const uint8_t INST_SRC_REGS                      = 14;
 392     static const uint8_t INST_SPLIT_DATA                    = 13;
 393
 394     inline SkedID genSkedID(DynInstPtr inst)
 395     {
 396         SkedID id = 0;
 397         id = (inst->opClass() << INST_OPCLASS) |
 398             (inst->isLoad() << INST_LOAD) |
 399             (inst->isStore() << INST_STORE) |
 400             (inst->isControl() << INST_CONTROL) |
 401             (inst->isNonSpeculative() << INST_NONSPEC) |
 402             (inst->numDestRegs() << INST_DEST_REGS) |
 403             (inst->numSrcRegs() << INST_SRC_REGS) |
 404             (inst->splitInst << INST_SPLIT_DATA);
 405         return id;
 406     }
 407
 408     ThePipeline::RSkedPtr createFrontEndSked();
 409     ThePipeline::RSkedPtr createFaultSked();
 410     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 411
 412     class StageScheduler {
 413       private:
 414         ThePipeline::RSkedPtr rsked;
 415         int stageNum;
 416         int nextTaskPriority;
 417
 418       public:
 419         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 420             : rsked(_rsked), stageNum(stage_num),
 421               nextTaskPriority(0)
 422         { }
 423
 424         void needs(int unit, int request) {
 425             rsked->push(new ScheduleEntry(
 426                             stageNum, nextTaskPriority++, unit, request
 427                             ));
 428         }
 429
 430         void needs(int unit, int request, int param) {
 431             rsked->push(new ScheduleEntry(
 432                             stageNum, nextTaskPriority++, unit, request, param
 433                             ));
 434         }
 435     };
 436
 437   private:
 438
 439     /** Data port. Note that it has to appear after the resPool. */
 440     CachePort dataPort;
 441
 442     /** Instruction port. Note that it has to appear after the resPool. */
 443     CachePort instPort;
 444
 445   public:
 446
 447     /** Registers statistics. */
 448     void regStats();
 449
 450     /** Ticks CPU, calling tick() on each stage, and checking the overall
 451      *  activity to see if the CPU should deschedule itself.
 452      */
 453     void tick();
 454
 455     /** Initialize the CPU */
 456     void init();
 457
 458     /** HW return from error interrupt. */
 459     Fault hwrei(ThreadID tid);
 460
 461     bool simPalCheck(int palFunc, ThreadID tid);
 462
 463     void checkForInterrupts();
 464
 465     /** Returns the Fault for any valid interrupt. */
 466     Fault getInterrupts();
 467
 468     /** Processes any an interrupt fault. */
 469     void processInterrupts(Fault interrupt);
 470
 471     /** Halts the CPU. */
 472     void halt() { panic("Halt not implemented!\n"); }
 473
 474     /** Check if this address is a valid instruction address. */
 475     bool validInstAddr(Addr addr) { return true; }
 476
 477     /** Check if this address is a valid data address. */
 478     bool validDataAddr(Addr addr) { return true; }
 479
 480     /** Schedule a syscall on the CPU */
 481     void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
 482                         Cycles delay = Cycles(0));
 483
 484     /** Executes a syscall.*/
 485     void syscall(int64_t callnum, ThreadID tid);
 486
 487     /** Schedule a trap on the CPU */
 488     void trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
 489                      Cycles delay = Cycles(0));
 490
 491     /** Perform trap to Handle Given Fault */
 492     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 493
 494     /** Schedule thread activation on the CPU */
 495     void activateContext(ThreadID tid, Cycles delay = Cycles(0));
 496
 497     /** Add Thread to Active Threads List. */
 498     void activateThread(ThreadID tid);
 499
 500     /** Activate Thread In Each Pipeline Stage */
 501     void activateThreadInPipeline(ThreadID tid);
 502
 503     /** Schedule Thread Activation from Ready List */
 504     void activateNextReadyContext(Cycles delay = Cycles(0));
 505
 506     /** Add Thread From Ready List to Active Threads List. */
 507     void activateNextReadyThread();
 508
 509     /** Schedule a thread deactivation on the CPU */
 510     void deactivateContext(ThreadID tid, Cycles delay = Cycles(0));
 511
 512     /** Remove from Active Thread List */
 513     void deactivateThread(ThreadID tid);
 514
 515     /** Schedule a thread suspension on the CPU */
 516   void suspendContext(ThreadID tid);
 517
 518     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 519     void suspendThread(ThreadID tid);
 520
 521     /** Schedule a thread halt on the CPU */
 522     void haltContext(ThreadID tid);
 523
 524     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 525      *  Threads List
 526      */
 527     void haltThread(ThreadID tid);
 528
 529     /** squashFromMemStall() - sets up a squash event
 530      *  squashDueToMemStall() - squashes pipeline
 531      *  @note: maybe squashContext/squashThread would be better?
 532      */
 533     void squashFromMemStall(DynInstPtr inst, ThreadID tid,
 534                             Cycles delay = Cycles(0));
 535     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 536
 537     void removePipelineStalls(ThreadID tid);
 538     void squashThreadInPipeline(ThreadID tid);
 539     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 540
 541     PipelineStage* getPipeStage(int stage_num);
 542
 543     int
 544     contextId()
 545     {
 546         hack_once("return a bogus context id");
 547         return 0;
 548     }
 549
 550     /** Update The Order In Which We Process Threads. */
 551     void updateThreadPriority();
 552
 553     /** Switches a Pipeline Stage to Active. (Unused currently) */
 554     void switchToActive(int stage_idx)
 555     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 556
 557     /** Get the current instruction sequence number, and increment it. */
 558     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 559     { return globalSeqNum[tid]++; }
 560
 561     /** Get the current instruction sequence number, and increment it. */
 562     InstSeqNum nextInstSeqNum(ThreadID tid)
 563     { return globalSeqNum[tid]; }
 564
 565     /** Increment Instruction Sequence Number */
 566     void incrInstSeqNum(ThreadID tid)
 567     { globalSeqNum[tid]++; }
 568
 569     /** Set Instruction Sequence Number */
 570     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 571     {
 572         globalSeqNum[tid] = seq_num;
 573     }
 574
 575     /** Get & Update Next Event Number */
 576     InstSeqNum getNextEventNum()
 577     {
 578 #ifdef DEBUG
 579         return cpuEventNum++;
 580 #else
 581         return 0;
 582 #endif
 583     }
 584
 585     /** Register file accessors  */
 586     uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
 587
 588     FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
 589
 590     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 591
 592     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 593
 594     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 595
 596     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 597
 598     RegType inline getRegType(RegIndex reg_idx)
 599     {
 600         if (reg_idx < TheISA::FP_Base_DepTag)
 601             return IntType;
 602         else if (reg_idx < TheISA::Ctrl_Base_DepTag)
 603             return FloatType;
 604         else
 605             return MiscType;
 606     }
 607
 608     RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
 609
 610     /** Reads a miscellaneous register. */
 611     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 612
 613     /** Reads a misc. register, including any side effects the read
 614      * might have as defined by the architecture.
 615      */
 616     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 617
 618     /** Sets a miscellaneous register. */
 619     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 620                             ThreadID tid = 0);
 621
 622     /** Sets a misc. register, including any side effects the write
 623      * might have as defined by the architecture.
 624      */
 625     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 626
 627     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 628      *  target thread
 629      */
 630     uint64_t readRegOtherThread(unsigned misc_reg,
 631                                 ThreadID tid = InvalidThreadID);
 632
 633     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 634      * target thread
 635      */
 636     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 637                            ThreadID tid);
 638
 639     /** Reads the commit PC of a specific thread. */
 640     TheISA::PCState
 641     pcState(ThreadID tid)
 642     {
 643         return pc[tid];
 644     }
 645
 646     /** Sets the commit PC of a specific thread. */
 647     void
 648     pcState(const TheISA::PCState &newPC, ThreadID tid)
 649     {
 650         pc[tid] = newPC;
 651     }
 652
 653     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 654     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 655     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 656
 657     /** Function to add instruction onto the head of the list of the
 658      *  instructions.  Used when new instructions are fetched.
 659      */
 660     ListIt addInst(DynInstPtr inst);
 661
 662     /** Find instruction on instruction list */
 663     ListIt findInst(InstSeqNum seq_num, ThreadID tid);
 664
 665     /** Function to tell the CPU that an instruction has completed. */
 666     void instDone(DynInstPtr inst, ThreadID tid);
 667
 668     /** Add Instructions to the CPU Remove List*/
 669     void addToRemoveList(DynInstPtr inst);
 670
 671     /** Remove an instruction from CPU */
 672     void removeInst(DynInstPtr inst);
 673
 674     /** Remove all instructions younger than the given sequence number. */
 675     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 676
 677     /** Removes the instruction pointed to by the iterator. */
 678     inline void squashInstIt(const ListIt inst_it, ThreadID tid);
 679
 680     /** Cleans up all instructions on the instruction remove list. */
 681     void cleanUpRemovedInsts();
 682
 683     /** Cleans up all events on the CPU event remove list. */
 684     void cleanUpRemovedEvents();
 685
 686     /** Debug function to print all instructions on the list. */
 687     void dumpInsts();
 688
 689     /** Forwards an instruction read to the appropriate data
 690      *  resource (indexes into Resource Pool thru "dataPortIdx")
 691      */
 692     Fault read(DynInstPtr inst, Addr addr,
 693                uint8_t *data, unsigned size, unsigned flags);
 694
 695     /** Forwards an instruction write. to the appropriate data
 696      *  resource (indexes into Resource Pool thru "dataPortIdx")
 697      */
 698     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 699                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 700
 701   public:
 702     /** Per-Thread List of all the instructions in flight. */
 703     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 704
 705     /** List of all the instructions that will be removed at the end of this
 706      *  cycle.
 707      */
 708     std::queue<ListIt> removeList;
 709
 710     bool trapPending[ThePipeline::MaxThreads];
 711
 712     /** List of all the cpu event requests that will be removed at the end of
 713      *  the current cycle.
 714      */
 715     std::queue<Event*> cpuEventRemoveList;
 716
 717     /** Records if instructions need to be removed this cycle due to
 718      *  being retired or squashed.
 719      */
 720     bool removeInstsThisCycle;
 721
 722     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 723      * execution unit know, NOT to execute while the instruction is active.
 724      */
 725     bool nonSpecInstActive[ThePipeline::MaxThreads];
 726
 727     /** Instruction Seq. Num of current non-speculative instruction. */
 728     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 729
 730     /** Instruction Seq. Num of last instruction squashed in pipeline */
 731     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 732
 733     /** Last Cycle that the CPU squashed instruction end. */
 734     Tick lastSquashCycle[ThePipeline::MaxThreads];
 735
 736     std::list<ThreadID> fetchPriorityList;
 737
 738   protected:
 739     /** Active Threads List */
 740     std::list<ThreadID> activeThreads;
 741
 742     /** Ready Threads List */
 743     std::list<ThreadID> readyThreads;
 744
 745     /** Suspended Threads List */
 746     std::list<ThreadID> suspendedThreads;
 747
 748     /** Halted Threads List */
 749     std::list<ThreadID> haltedThreads;
 750
 751     /** Thread Status Functions */
 752     bool isThreadActive(ThreadID tid);
 753     bool isThreadReady(ThreadID tid);
 754     bool isThreadSuspended(ThreadID tid);
 755
 756   private:
 757     /** The activity recorder; used to tell if the CPU has any
 758      * activity remaining or if it can go to idle and deschedule
 759      * itself.
 760      */
 761     ActivityRecorder activityRec;
 762
 763   public:
 764     /** Number of Active Threads in the CPU */
 765     ThreadID numActiveThreads() { return activeThreads.size(); }
 766
 767     /** Thread id of active thread
 768      *  Only used for SwitchOnCacheMiss model.
 769      *  Assumes only 1 thread active
 770      */
 771     ThreadID activeThreadId()
 772     {
 773         if (numActiveThreads() > 0)
 774             return activeThreads.front();
 775         else
 776             return InvalidThreadID;
 777     }
 778
 779
 780     /** Records that there was time buffer activity this cycle. */
 781     void activityThisCycle() { activityRec.activity(); }
 782
 783     /** Changes a stage's status to active within the activity recorder. */
 784     void activateStage(const int idx)
 785     { activityRec.activateStage(idx); }
 786
 787     /** Changes a stage's status to inactive within the activity recorder. */
 788     void deactivateStage(const int idx)
 789     { activityRec.deactivateStage(idx); }
 790
 791     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 792     void wakeCPU();
 793
 794     virtual void wakeup();
 795
 796     /* LL/SC debug functionality
 797     unsigned stCondFails;
 798
 799     unsigned readStCondFailures()
 800     { return stCondFails; }
 801
 802     unsigned setStCondFailures(unsigned st_fails)
 803     { return stCondFails = st_fails; }
 804     */
 805
 806     /** Returns a pointer to a thread context. */
 807     ThreadContext *tcBase(ThreadID tid = 0)
 808     {
 809         return thread[tid]->getTC();
 810     }
 811
 812     /** Count the Total Instructions Committed in the CPU. */
 813     virtual Counter totalInsts() const
 814     {
 815         Counter total(0);
 816
 817         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 818             total += thread[tid]->numInst;
 819
 820         return total;
 821     }
 822
 823     /** Count the Total Ops Committed in the CPU. */
 824     virtual Counter totalOps() const
 825     {
 826         Counter total(0);
 827
 828         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 829             total += thread[tid]->numOp;
 830
 831         return total;
 832     }
 833
 834     /** Pointer to the system. */
 835     System *system;
 836
 837     /** The global sequence number counter. */
 838     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 839
 840 #ifdef DEBUG
 841     /** The global event number counter. */
 842     InstSeqNum cpuEventNum;
 843
 844     /** Number of resource requests active in CPU **/
 845     unsigned resReqCount;
 846 #endif
 847
 848     Addr lockAddr;
 849
 850     /** Temporary fix for the lock flag, works in the UP case. */
 851     bool lockFlag;
 852
 853     /** Counter of how many stages have completed draining */
 854     int drainCount;
 855
 856     /** Pointers to all of the threads in the CPU. */
 857     std::vector<Thread *> thread;
 858
 859     /** Per-Stage Instruction Tracing */
 860     bool stageTracing;
 861
 862     /** The cycle that the CPU was last running, used for statistics. */
 863     Tick lastRunningCycle;
 864
 865     void updateContextSwitchStats();
 866     unsigned instsPerSwitch;
 867     Stats::Average instsPerCtxtSwitch;
 868     Stats::Scalar numCtxtSwitches;
 869
 870     /** Update Thread , used for statistic purposes*/
 871     inline void tickThreadStats();
 872
 873     /** Per-Thread Tick */
 874     Stats::Vector threadCycles;
 875
 876     /** Tick for SMT */
 877     Stats::Scalar smtCycles;
 878
 879     /** Stat for total number of times the CPU is descheduled. */
 880     Stats::Scalar timesIdled;
 881
 882     /** Stat for total number of cycles the CPU spends descheduled or no
 883      *  stages active.
 884      */
 885     Stats::Scalar idleCycles;
 886
 887     /** Stat for total number of cycles the CPU is active. */
 888     Stats::Scalar runCycles;
 889
 890     /** Percentage of cycles a stage was active */
 891     Stats::Formula activity;
 892
 893     /** Instruction Mix Stats */
 894     Stats::Scalar comLoads;
 895     Stats::Scalar comStores;
 896     Stats::Scalar comBranches;
 897     Stats::Scalar comNops;
 898     Stats::Scalar comNonSpec;
 899     Stats::Scalar comInts;
 900     Stats::Scalar comFloats;
 901
 902     /** Stat for the number of committed instructions per thread. */
 903     Stats::Vector committedInsts;
 904
 905     /** Stat for the number of committed ops per thread. */
 906     Stats::Vector committedOps;
 907
 908     /** Stat for the number of committed instructions per thread. */
 909     Stats::Vector smtCommittedInsts;
 910
 911     /** Stat for the total number of committed instructions. */
 912     Stats::Scalar totalCommittedInsts;
 913
 914     /** Stat for the CPI per thread. */
 915     Stats::Formula cpi;
 916
 917     /** Stat for the SMT-CPI per thread. */
 918     Stats::Formula smtCpi;
 919
 920     /** Stat for the total CPI. */
 921     Stats::Formula totalCpi;
 922
 923     /** Stat for the IPC per thread. */
 924     Stats::Formula ipc;
 925
 926     /** Stat for the total IPC. */
 927     Stats::Formula smtIpc;
 928
 929     /** Stat for the total IPC. */
 930     Stats::Formula totalIpc;
 931 };
 932
 933 #endif // __CPU_O3_CPU_HH__