2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_CPU_HH__
33 #define __CPU_INORDER_CPU_HH__
41 #include "arch/isa_traits.hh"
42 #include "arch/registers.hh"
43 #include "arch/types.hh"
44 #include "base/statistics.hh"
45 #include "base/types.hh"
46 #include "config/full_system.hh"
47 #include "config/the_isa.hh"
48 #include "cpu/inorder/inorder_dyn_inst.hh"
49 #include "cpu/inorder/pipeline_stage.hh"
50 #include "cpu/inorder/pipeline_traits.hh"
51 #include "cpu/inorder/reg_dep_map.hh"
52 #include "cpu/inorder/thread_state.hh"
53 #include "cpu/o3/dep_graph.hh"
54 #include "cpu/o3/rename_map.hh"
55 #include "cpu/activity.hh"
56 #include "cpu/base.hh"
57 #include "cpu/simple_thread.hh"
58 #include "cpu/timebuf.hh"
59 #include "mem/packet.hh"
60 #include "mem/port.hh"
61 #include "mem/request.hh"
62 #include "sim/eventq.hh"
63 #include "sim/process.hh"
71 class InOrderCPU : public BaseCPU
75 typedef ThePipeline::Params Params;
76 typedef InOrderThreadState Thread;
79 typedef TheISA::IntReg IntReg;
80 typedef TheISA::FloatReg FloatReg;
81 typedef TheISA::FloatRegBits FloatRegBits;
82 typedef TheISA::MiscReg MiscReg;
85 typedef ThePipeline::DynInstPtr DynInstPtr;
86 typedef std::list<DynInstPtr>::iterator ListIt;
89 typedef TimeBuffer<InterStageStruct> StageQueue;
91 friend class Resource;
94 /** Constructs a CPU with the given parameters. */
95 InOrderCPU(Params *params);
103 ThreadID asid[ThePipeline::MaxThreads];
105 /** Type of core that this is */
106 std::string coreType;
108 // Only need for SE MODE
115 ThreadModel threadModel;
117 int readCpuId() { return cpu_id; }
119 void setCpuId(int val) { cpu_id = val; }
132 /** Overall CPU status. */
135 /** Define TickEvent for the CPU */
136 class TickEvent : public Event
139 /** Pointer to the CPU. */
143 /** Constructs a tick event. */
144 TickEvent(InOrderCPU *c);
146 /** Processes a tick event, calling tick() on the CPU. */
149 /** Returns the description of the tick event. */
150 const char *description();
153 /** The tick event used for scheduling CPU ticks. */
156 /** Schedule tick event, regardless of its current state. */
157 void scheduleTickEvent(int delay)
159 assert(!tickEvent.scheduled() || tickEvent.squashed());
160 reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
163 /** Unschedule tick event, regardless of its current state. */
164 void unscheduleTickEvent()
166 if (tickEvent.scheduled())
171 // List of Events That can be scheduled from
173 // NOTE(1): The Resource Pool also uses this event list
174 // to schedule events broadcast to all resources interfaces
175 // NOTE(2): CPU Events usually need to schedule a corresponding resource
179 ActivateNextReadyThread,
190 static std::string eventNames[NumCPUEvents];
192 /** Define CPU Event */
193 class CPUEvent : public Event
199 CPUEventType cpuEventType;
206 /** Constructs a CPU event. */
207 CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
208 ThreadID _tid, DynInstPtr inst, unsigned event_pri_offset);
210 /** Set Type of Event To Be Scheduled */
211 void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
215 cpuEventType = e_type;
221 /** Processes a CPU event. */
224 /** Returns the description of the CPU event. */
225 const char *description();
227 /** Schedule Event */
228 void scheduleEvent(int delay);
230 /** Unschedule This Event */
231 void unscheduleEvent();
234 /** Schedule a CPU Event */
235 void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
236 DynInstPtr inst, unsigned delay = 0,
237 unsigned event_pri_offset = 0);
240 /** Interface between the CPU and CPU resources. */
241 ResourcePool *resPool;
243 /** Instruction used to signify that there is no *real* instruction in
245 DynInstPtr dummyInst[ThePipeline::MaxThreads];
246 DynInstPtr dummyBufferInst;
247 DynInstPtr dummyReqInst;
249 /** Used by resources to signify a denied access to a resource. */
250 ResourceRequest *dummyReq[ThePipeline::MaxThreads];
252 /** Identifies the resource id that identifies a fetch
255 unsigned fetchPortIdx;
257 /** Identifies the resource id that identifies a ITB */
260 /** Identifies the resource id that identifies a data
263 unsigned dataPortIdx;
265 /** Identifies the resource id that identifies a DTB */
268 /** The Pipeline Stages for the CPU */
269 PipelineStage *pipelineStage[ThePipeline::NumStages];
271 /** Width (processing bandwidth) of each stage */
274 /** Program Counters */
275 TheISA::PCState pc[ThePipeline::MaxThreads];
277 /** The Register File for the CPU */
279 FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
280 FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
282 TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
285 TheISA::ISA isa[ThePipeline::MaxThreads];
287 /** Dependency Tracker for Integer & Floating Point Regs */
288 RegDepMap archRegDepMap[ThePipeline::MaxThreads];
290 /** Global communication structure */
291 TimeBuffer<TimeStruct> timeBuffer;
293 /** Communication structure that sits in between pipeline stages */
294 StageQueue *stageQueue[ThePipeline::NumStages-1];
296 TheISA::TLB *getITBPtr();
297 TheISA::TLB *getDTBPtr();
299 /** Accessor Type for the SkedCache */
300 typedef uint32_t SkedID;
302 /** Cache of Instruction Schedule using the instruction's name as a key */
303 static std::map<SkedID, ThePipeline::RSkedPtr> skedCache;
305 typedef std::map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
307 /** Initialized to last iterator in map, signifying a invalid entry
310 SkedCacheIt endOfSkedIt;
312 ThePipeline::RSkedPtr frontEndSked;
314 /** Add a new instruction schedule to the schedule cache */
315 void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
317 SkedID sked_id = genSkedID(inst);
318 assert(skedCache.find(sked_id) == skedCache.end());
319 skedCache[sked_id] = inst_sked;
323 /** Find a instruction schedule */
324 ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
326 SkedID sked_id = genSkedID(inst);
327 SkedCacheIt lookup_it = skedCache.find(sked_id);
329 if (lookup_it != endOfSkedIt) {
330 return (*lookup_it).second;
336 static const uint8_t INST_OPCLASS = 26;
337 static const uint8_t INST_LOAD = 25;
338 static const uint8_t INST_STORE = 24;
339 static const uint8_t INST_CONTROL = 23;
340 static const uint8_t INST_NONSPEC = 22;
341 static const uint8_t INST_DEST_REGS = 18;
342 static const uint8_t INST_SRC_REGS = 14;
344 inline SkedID genSkedID(DynInstPtr inst)
347 id = (inst->opClass() << INST_OPCLASS) |
348 (inst->isLoad() << INST_LOAD) |
349 (inst->isStore() << INST_STORE) |
350 (inst->isControl() << INST_CONTROL) |
351 (inst->isNonSpeculative() << INST_NONSPEC) |
352 (inst->numDestRegs() << INST_DEST_REGS) |
353 (inst->numSrcRegs() << INST_SRC_REGS);
357 ThePipeline::RSkedPtr createFrontEndSked();
358 ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
360 class StageScheduler {
362 ThePipeline::RSkedPtr rsked;
364 int nextTaskPriority;
367 StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
368 : rsked(_rsked), stageNum(stage_num),
372 void needs(int unit, int request) {
373 rsked->push(new ScheduleEntry(
374 stageNum, nextTaskPriority++, unit, request
378 void needs(int unit, int request, int param) {
379 rsked->push(new ScheduleEntry(
380 stageNum, nextTaskPriority++, unit, request, param
387 /** Registers statistics. */
390 /** Ticks CPU, calling tick() on each stage, and checking the overall
391 * activity to see if the CPU should deschedule itself.
395 /** Initialize the CPU */
398 /** Get a Memory Port */
399 Port* getPort(const std::string &if_name, int idx = 0);
402 /** HW return from error interrupt. */
403 Fault hwrei(ThreadID tid);
405 bool simPalCheck(int palFunc, ThreadID tid);
407 /** Returns the Fault for any valid interrupt. */
408 Fault getInterrupts();
410 /** Processes any an interrupt fault. */
411 void processInterrupts(Fault interrupt);
413 /** Halts the CPU. */
414 void halt() { panic("Halt not implemented!\n"); }
416 /** Update the Virt and Phys ports of all ThreadContexts to
417 * reflect change in memory connections. */
418 void updateMemPorts();
420 /** Check if this address is a valid instruction address. */
421 bool validInstAddr(Addr addr) { return true; }
423 /** Check if this address is a valid data address. */
424 bool validDataAddr(Addr addr) { return true; }
427 /** trap() - sets up a trap event on the cpuTraps to handle given fault.
428 * trapCPU() - Traps to handle given fault
430 void trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
431 void trapCPU(Fault fault, ThreadID tid, DynInstPtr inst);
433 /** Add Thread to Active Threads List. */
434 void activateContext(ThreadID tid, int delay = 0);
435 void activateThread(ThreadID tid);
436 void activateThreadInPipeline(ThreadID tid);
438 /** Add Thread to Active Threads List. */
439 void activateNextReadyContext(int delay = 0);
440 void activateNextReadyThread();
442 /** Remove from Active Thread List */
443 void deactivateContext(ThreadID tid, int delay = 0);
444 void deactivateThread(ThreadID tid);
446 /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
447 void suspendContext(ThreadID tid, int delay = 0);
448 void suspendThread(ThreadID tid);
450 /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
453 void haltContext(ThreadID tid, int delay = 0);
454 void haltThread(ThreadID tid);
456 /** squashFromMemStall() - sets up a squash event
457 * squashDueToMemStall() - squashes pipeline
458 * @note: maybe squashContext/squashThread would be better?
460 void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
461 void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
463 void removePipelineStalls(ThreadID tid);
464 void squashThreadInPipeline(ThreadID tid);
465 void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
467 PipelineStage* getPipeStage(int stage_num);
472 hack_once("return a bogus context id");
476 /** Update The Order In Which We Process Threads. */
477 void updateThreadPriority();
479 /** Switches a Pipeline Stage to Active. (Unused currently) */
480 void switchToActive(int stage_idx)
481 { /*pipelineStage[stage_idx]->switchToActive();*/ }
483 /** Get the current instruction sequence number, and increment it. */
484 InstSeqNum getAndIncrementInstSeq(ThreadID tid)
485 { return globalSeqNum[tid]++; }
487 /** Get the current instruction sequence number, and increment it. */
488 InstSeqNum nextInstSeqNum(ThreadID tid)
489 { return globalSeqNum[tid]; }
491 /** Increment Instruction Sequence Number */
492 void incrInstSeqNum(ThreadID tid)
493 { globalSeqNum[tid]++; }
495 /** Set Instruction Sequence Number */
496 void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
498 globalSeqNum[tid] = seq_num;
501 /** Get & Update Next Event Number */
502 InstSeqNum getNextEventNum()
505 return cpuEventNum++;
511 /** Register file accessors */
512 uint64_t readIntReg(int reg_idx, ThreadID tid);
514 FloatReg readFloatReg(int reg_idx, ThreadID tid);
516 FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
518 void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
520 void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
522 void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid);
524 /** Reads a miscellaneous register. */
525 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
527 /** Reads a misc. register, including any side effects the read
528 * might have as defined by the architecture.
530 MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
532 /** Sets a miscellaneous register. */
533 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
536 /** Sets a misc. register, including any side effects the write
537 * might have as defined by the architecture.
539 void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
541 /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
544 uint64_t readRegOtherThread(unsigned misc_reg,
545 ThreadID tid = InvalidThreadID);
547 /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
550 void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
553 /** Reads the commit PC of a specific thread. */
555 pcState(ThreadID tid)
560 /** Sets the commit PC of a specific thread. */
562 pcState(const TheISA::PCState &newPC, ThreadID tid)
567 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
568 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
569 MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
571 /** Function to add instruction onto the head of the list of the
572 * instructions. Used when new instructions are fetched.
574 ListIt addInst(DynInstPtr &inst);
576 /** Function to tell the CPU that an instruction has completed. */
577 void instDone(DynInstPtr inst, ThreadID tid);
579 /** Add Instructions to the CPU Remove List*/
580 void addToRemoveList(DynInstPtr &inst);
582 /** Remove an instruction from CPU */
583 void removeInst(DynInstPtr &inst);
585 /** Remove all instructions younger than the given sequence number. */
586 void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
588 /** Removes the instruction pointed to by the iterator. */
589 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
591 /** Cleans up all instructions on the instruction remove list. */
592 void cleanUpRemovedInsts();
594 /** Cleans up all events on the CPU event remove list. */
595 void cleanUpRemovedEvents();
597 /** Debug function to print all instructions on the list. */
600 /** Forwards an instruction read to the appropriate data
601 * resource (indexes into Resource Pool thru "dataPortIdx")
603 Fault read(DynInstPtr inst, Addr addr,
604 uint8_t *data, unsigned size, unsigned flags);
606 /** Forwards an instruction write. to the appropriate data
607 * resource (indexes into Resource Pool thru "dataPortIdx")
609 Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
610 Addr addr, unsigned flags, uint64_t *write_res = NULL);
612 /** Executes a syscall.*/
613 void syscall(int64_t callnum, ThreadID tid);
616 /** Per-Thread List of all the instructions in flight. */
617 std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
619 /** List of all the instructions that will be removed at the end of this
622 std::queue<ListIt> removeList;
624 /** List of all the cpu event requests that will be removed at the end of
627 std::queue<Event*> cpuEventRemoveList;
629 /** Records if instructions need to be removed this cycle due to
630 * being retired or squashed.
632 bool removeInstsThisCycle;
634 /** True if there is non-speculative Inst Active In Pipeline. Lets any
635 * execution unit know, NOT to execute while the instruction is active.
637 bool nonSpecInstActive[ThePipeline::MaxThreads];
639 /** Instruction Seq. Num of current non-speculative instruction. */
640 InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
642 /** Instruction Seq. Num of last instruction squashed in pipeline */
643 InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
645 /** Last Cycle that the CPU squashed instruction end. */
646 Tick lastSquashCycle[ThePipeline::MaxThreads];
648 std::list<ThreadID> fetchPriorityList;
651 /** Active Threads List */
652 std::list<ThreadID> activeThreads;
654 /** Ready Threads List */
655 std::list<ThreadID> readyThreads;
657 /** Suspended Threads List */
658 std::list<ThreadID> suspendedThreads;
660 /** Halted Threads List */
661 std::list<ThreadID> haltedThreads;
663 /** Thread Status Functions */
664 bool isThreadActive(ThreadID tid);
665 bool isThreadReady(ThreadID tid);
666 bool isThreadSuspended(ThreadID tid);
669 /** The activity recorder; used to tell if the CPU has any
670 * activity remaining or if it can go to idle and deschedule
673 ActivityRecorder activityRec;
676 /** Number of Active Threads in the CPU */
677 ThreadID numActiveThreads() { return activeThreads.size(); }
679 /** Thread id of active thread
680 * Only used for SwitchOnCacheMiss model.
681 * Assumes only 1 thread active
683 ThreadID activeThreadId()
685 if (numActiveThreads() > 0)
686 return activeThreads.front();
688 return InvalidThreadID;
692 /** Records that there was time buffer activity this cycle. */
693 void activityThisCycle() { activityRec.activity(); }
695 /** Changes a stage's status to active within the activity recorder. */
696 void activateStage(const int idx)
697 { activityRec.activateStage(idx); }
699 /** Changes a stage's status to inactive within the activity recorder. */
700 void deactivateStage(const int idx)
701 { activityRec.deactivateStage(idx); }
703 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
707 virtual void wakeup();
710 // LL/SC debug functionality
711 unsigned stCondFails;
713 unsigned readStCondFailures()
714 { return stCondFails; }
716 unsigned setStCondFailures(unsigned st_fails)
717 { return stCondFails = st_fails; }
719 /** Returns a pointer to a thread context. */
720 ThreadContext *tcBase(ThreadID tid = 0)
722 return thread[tid]->getTC();
725 /** Count the Total Instructions Committed in the CPU. */
726 virtual Counter totalInstructions() const
730 for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
731 total += thread[tid]->numInst;
737 /** Pointer to the system. */
740 /** Pointer to physical memory. */
741 PhysicalMemory *physmem;
744 /** The global sequence number counter. */
745 InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
748 /** The global event number counter. */
749 InstSeqNum cpuEventNum;
751 /** Number of resource requests active in CPU **/
752 unsigned resReqCount;
755 /** Counter of how many stages have completed switching out. */
758 /** Pointers to all of the threads in the CPU. */
759 std::vector<Thread *> thread;
761 /** Pointer to the icache interface. */
762 MemInterface *icacheInterface;
764 /** Pointer to the dcache interface. */
765 MemInterface *dcacheInterface;
767 /** Whether or not the CPU should defer its registration. */
768 bool deferRegistration;
770 /** Per-Stage Instruction Tracing */
773 /** The cycle that the CPU was last running, used for statistics. */
774 Tick lastRunningCycle;
776 void updateContextSwitchStats();
777 unsigned instsPerSwitch;
778 Stats::Average instsPerCtxtSwitch;
779 Stats::Scalar numCtxtSwitches;
781 /** Update Thread , used for statistic purposes*/
782 inline void tickThreadStats();
784 /** Per-Thread Tick */
785 Stats::Vector threadCycles;
788 Stats::Scalar smtCycles;
790 /** Stat for total number of times the CPU is descheduled. */
791 Stats::Scalar timesIdled;
793 /** Stat for total number of cycles the CPU spends descheduled or no
796 Stats::Scalar idleCycles;
798 /** Stat for total number of cycles the CPU is active. */
799 Stats::Scalar runCycles;
801 /** Percentage of cycles a stage was active */
802 Stats::Formula activity;
804 /** Instruction Mix Stats */
805 Stats::Scalar comLoads;
806 Stats::Scalar comStores;
807 Stats::Scalar comBranches;
808 Stats::Scalar comNops;
809 Stats::Scalar comNonSpec;
810 Stats::Scalar comInts;
811 Stats::Scalar comFloats;
813 /** Stat for the number of committed instructions per thread. */
814 Stats::Vector committedInsts;
816 /** Stat for the number of committed instructions per thread. */
817 Stats::Vector smtCommittedInsts;
819 /** Stat for the total number of committed instructions. */
820 Stats::Scalar totalCommittedInsts;
822 /** Stat for the CPI per thread. */
825 /** Stat for the SMT-CPI per thread. */
826 Stats::Formula smtCpi;
828 /** Stat for the total CPI. */
829 Stats::Formula totalCpi;
831 /** Stat for the IPC per thread. */
834 /** Stat for the total IPC. */
835 Stats::Formula smtIpc;
837 /** Stat for the total IPC. */
838 Stats::Formula totalIpc;
841 #endif // __CPU_O3_CPU_HH__