src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/types.hh"
  43 #include "arch/registers.hh"
  44 #include "base/statistics.hh"
  45 #include "base/timebuf.hh"
  46 #include "base/types.hh"
  47 #include "config/full_system.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/activity.hh"
  50 #include "cpu/base.hh"
  51 #include "cpu/simple_thread.hh"
  52 #include "cpu/inorder/inorder_dyn_inst.hh"
  53 #include "cpu/inorder/pipeline_traits.hh"
  54 #include "cpu/inorder/pipeline_stage.hh"
  55 #include "cpu/inorder/thread_state.hh"
  56 #include "cpu/inorder/reg_dep_map.hh"
  57 #include "cpu/o3/dep_graph.hh"
  58 #include "cpu/o3/rename_map.hh"
  59 #include "mem/packet.hh"
  60 #include "mem/port.hh"
  61 #include "mem/request.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/process.hh"
  64
  65 class ThreadContext;
  66 class MemInterface;
  67 class MemObject;
  68 class Process;
  69 class ResourcePool;
  70
  71 class InOrderCPU : public BaseCPU
  72 {
  73
  74   protected:
  75     typedef ThePipeline::Params Params;
  76     typedef InOrderThreadState Thread;
  77
  78    //ISA TypeDefs
  79     typedef TheISA::IntReg IntReg;
  80     typedef TheISA::FloatReg FloatReg;
  81     typedef TheISA::FloatRegBits FloatRegBits;
  82     typedef TheISA::MiscReg MiscReg;
  83
  84     //DynInstPtr TypeDefs
  85     typedef ThePipeline::DynInstPtr DynInstPtr;
  86     typedef std::list<DynInstPtr>::iterator ListIt;
  87
  88     //TimeBuffer TypeDefs
  89     typedef TimeBuffer<InterStageStruct> StageQueue;
  90
  91     friend class Resource;
  92
  93   public:
  94     /** Constructs a CPU with the given parameters. */
  95     InOrderCPU(Params *params);
  96
  97     /** CPU ID */
  98     int cpu_id;
  99
 100     /** Type of core that this is */
 101     std::string coreType;
 102
 103     // Only need for SE MODE
 104     enum ThreadModel {
 105         Single,
 106         SMT,
 107         SwitchOnCacheMiss
 108     };
 109
 110     ThreadModel threadModel;
 111
 112     int readCpuId() { return cpu_id; }
 113
 114     void setCpuId(int val) { cpu_id = val; }
 115
 116     Params *cpu_params;
 117
 118   public:
 119     enum Status {
 120         Running,
 121         Idle,
 122         Halted,
 123         Blocked,
 124         SwitchedOut
 125     };
 126
 127     /** Overall CPU status. */
 128     Status _status;
 129   private:
 130     /** Define TickEvent for the CPU */
 131     class TickEvent : public Event
 132     {
 133       private:
 134         /** Pointer to the CPU. */
 135         InOrderCPU *cpu;
 136
 137       public:
 138         /** Constructs a tick event. */
 139         TickEvent(InOrderCPU *c);
 140
 141         /** Processes a tick event, calling tick() on the CPU. */
 142         void process();
 143
 144         /** Returns the description of the tick event. */
 145         const char *description();
 146     };
 147
 148     /** The tick event used for scheduling CPU ticks. */
 149     TickEvent tickEvent;
 150
 151     /** Schedule tick event, regardless of its current state. */
 152     void scheduleTickEvent(int delay)
 153     {
 154         if (tickEvent.squashed())
 155           mainEventQueue.reschedule(&tickEvent,
 156                                     nextCycle(curTick + ticks(delay)));
 157         else if (!tickEvent.scheduled())
 158           mainEventQueue.schedule(&tickEvent,
 159                                   nextCycle(curTick + ticks(delay)));
 160     }
 161
 162     /** Unschedule tick event, regardless of its current state. */
 163     void unscheduleTickEvent()
 164     {
 165         if (tickEvent.scheduled())
 166             tickEvent.squash();
 167     }
 168
 169   public:
 170     // List of Events That can be scheduled from
 171     // within the CPU.
 172     // NOTE(1): The Resource Pool also uses this event list
 173     // to schedule events broadcast to all resources interfaces
 174     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 175     // pool event.
 176     enum CPUEventType {
 177         ActivateThread,
 178         DeallocateThread,
 179         SuspendThread,
 180         DisableThreads,
 181         EnableThreads,
 182         DisableVPEs,
 183         EnableVPEs,
 184         Trap,
 185         InstGraduated,
 186         SquashFromMemStall,
 187         UpdatePCs,
 188         NumCPUEvents
 189     };
 190
 191     static std::string eventNames[NumCPUEvents];
 192
 193     /** Define CPU Event */
 194     class CPUEvent : public Event
 195     {
 196       protected:
 197         InOrderCPU *cpu;
 198
 199       public:
 200         CPUEventType cpuEventType;
 201         ThreadID tid;
 202         DynInstPtr inst;
 203         Fault fault;
 204         unsigned vpe;
 205
 206       public:
 207         /** Constructs a CPU event. */
 208         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 209                  ThreadID _tid, DynInstPtr inst, unsigned event_pri_offset);
 210
 211         /** Set Type of Event To Be Scheduled */
 212         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 213                       DynInstPtr _inst)
 214         {
 215             fault = _fault;
 216             cpuEventType = e_type;
 217             tid = _tid;
 218             inst = _inst;
 219             vpe = 0;
 220         }
 221
 222         /** Processes a resource event. */
 223         virtual void process();
 224
 225         /** Returns the description of the resource event. */
 226         const char *description();
 227
 228         /** Schedule Event */
 229         void scheduleEvent(int delay);
 230
 231         /** Unschedule This Event */
 232         void unscheduleEvent();
 233     };
 234
 235     /** Schedule a CPU Event */
 236     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 237                           DynInstPtr inst, unsigned delay = 0,
 238                           unsigned event_pri_offset = 0);
 239
 240   public:
 241     /** Interface between the CPU and CPU resources. */
 242     ResourcePool *resPool;
 243
 244     /** Instruction used to signify that there is no *real* instruction in
 245         buffer slot */
 246     DynInstPtr dummyInst;
 247
 248     /** Used by resources to signify a denied access to a resource. */
 249     ResourceRequest *dummyReq;
 250
 251     /** Identifies the resource id that identifies a fetch
 252      * access unit.
 253      */
 254     unsigned fetchPortIdx;
 255
 256     /** Identifies the resource id that identifies a ITB       */
 257     unsigned itbIdx;
 258
 259     /** Identifies the resource id that identifies a data
 260      * access unit.
 261      */
 262     unsigned dataPortIdx;
 263
 264     /** Identifies the resource id that identifies a DTB       */
 265     unsigned dtbIdx;
 266
 267     /** The Pipeline Stages for the CPU */
 268     PipelineStage *pipelineStage[ThePipeline::NumStages];
 269
 270     /** Program Counters */
 271     TheISA::IntReg PC[ThePipeline::MaxThreads];
 272     TheISA::IntReg nextPC[ThePipeline::MaxThreads];
 273     TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
 274
 275     /** The Register File for the CPU */
 276     union {
 277         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 278         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 279     } floatRegs;
 280     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 281
 282     /** ISA state */
 283     TheISA::ISA isa[ThePipeline::MaxThreads];
 284
 285     /** Dependency Tracker for Integer & Floating Point Regs */
 286     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 287
 288     /** Global communication structure */
 289     TimeBuffer<TimeStruct> timeBuffer;
 290
 291     /** Communication structure that sits in between pipeline stages */
 292     StageQueue *stageQueue[ThePipeline::NumStages-1];
 293
 294     TheISA::TLB *getITBPtr();
 295     TheISA::TLB *getDTBPtr();
 296
 297   public:
 298
 299     /** Registers statistics. */
 300     void regStats();
 301
 302     /** Ticks CPU, calling tick() on each stage, and checking the overall
 303      *  activity to see if the CPU should deschedule itself.
 304      */
 305     void tick();
 306
 307     /** Initialize the CPU */
 308     void init();
 309
 310     /** Reset State in the CPU */
 311     void reset();
 312
 313     /** Get a Memory Port */
 314     Port* getPort(const std::string &if_name, int idx = 0);
 315
 316 #if FULL_SYSTEM
 317     /** HW return from error interrupt. */
 318     Fault hwrei(ThreadID tid);
 319
 320     bool simPalCheck(int palFunc, ThreadID tid);
 321
 322     /** Returns the Fault for any valid interrupt. */
 323     Fault getInterrupts();
 324
 325     /** Processes any an interrupt fault. */
 326     void processInterrupts(Fault interrupt);
 327
 328     /** Halts the CPU. */
 329     void halt() { panic("Halt not implemented!\n"); }
 330
 331     /** Update the Virt and Phys ports of all ThreadContexts to
 332      * reflect change in memory connections. */
 333     void updateMemPorts();
 334
 335     /** Check if this address is a valid instruction address. */
 336     bool validInstAddr(Addr addr) { return true; }
 337
 338     /** Check if this address is a valid data address. */
 339     bool validDataAddr(Addr addr) { return true; }
 340 #endif
 341
 342     /** trap() - sets up a trap event on the cpuTraps to handle given fault.
 343      *  trapCPU() - Traps to handle given fault
 344      */
 345     void trap(Fault fault, ThreadID tid, int delay = 0);
 346     void trapCPU(Fault fault, ThreadID tid);
 347
 348     /** squashFromMemStall() - sets up a squash event
 349      *  squashDueToMemStall() - squashes pipeline
 350      */
 351     void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
 352     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 353
 354     /** Setup CPU to insert a thread's context */
 355     void insertThread(ThreadID tid);
 356
 357     /** Remove all of a thread's context from CPU */
 358     void removeThread(ThreadID tid);
 359
 360     /** Add Thread to Active Threads List. */
 361     void activateContext(ThreadID tid, int delay = 0);
 362     void activateThread(ThreadID tid);
 363
 364     /** Remove Thread from Active Threads List */
 365     void suspendContext(ThreadID tid, int delay = 0);
 366     void suspendThread(ThreadID tid);
 367
 368     /** Remove Thread from Active Threads List &&
 369      *  Remove Thread Context from CPU.
 370      */
 371     void deallocateContext(ThreadID tid, int delay = 0);
 372     void deallocateThread(ThreadID tid);
 373     void deactivateThread(ThreadID tid);
 374
 375     PipelineStage* getPipeStage(int stage_num);
 376
 377     int
 378     contextId()
 379     {
 380         hack_once("return a bogus context id");
 381         return 0;
 382     }
 383
 384     /** Remove Thread from Active Threads List &&
 385      *  Remove Thread Context from CPU.
 386      */
 387     void haltContext(ThreadID tid, int delay = 0);
 388
 389     void removePipelineStalls(ThreadID tid);
 390
 391     void squashThreadInPipeline(ThreadID tid);
 392
 393     /// Notify the CPU to enable a virtual processor element.
 394     virtual void enableVirtProcElement(unsigned vpe);
 395     void enableVPEs(unsigned vpe);
 396
 397     /// Notify the CPU to disable a virtual processor element.
 398     virtual void disableVirtProcElement(ThreadID tid, unsigned vpe);
 399     void disableVPEs(ThreadID tid, unsigned vpe);
 400
 401     /// Notify the CPU that multithreading is enabled.
 402     virtual void enableMultiThreading(unsigned vpe);
 403     void enableThreads(unsigned vpe);
 404
 405     /// Notify the CPU that multithreading is disabled.
 406     virtual void disableMultiThreading(ThreadID tid, unsigned vpe);
 407     void disableThreads(ThreadID tid, unsigned vpe);
 408
 409     /** Activate a Thread When CPU Resources are Available. */
 410     void activateWhenReady(ThreadID tid);
 411
 412     /** Add or Remove a Thread Context in the CPU. */
 413     void doContextSwitch();
 414
 415     /** Update The Order In Which We Process Threads. */
 416     void updateThreadPriority();
 417
 418     /** Switches a Pipeline Stage to Active. (Unused currently) */
 419     void switchToActive(int stage_idx)
 420     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 421
 422     /** Get the current instruction sequence number, and increment it. */
 423     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 424     { return globalSeqNum[tid]++; }
 425
 426     /** Get the current instruction sequence number, and increment it. */
 427     InstSeqNum nextInstSeqNum(ThreadID tid)
 428     { return globalSeqNum[tid]; }
 429
 430     /** Increment Instruction Sequence Number */
 431     void incrInstSeqNum(ThreadID tid)
 432     { globalSeqNum[tid]++; }
 433
 434     /** Set Instruction Sequence Number */
 435     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 436     {
 437         globalSeqNum[tid] = seq_num;
 438     }
 439
 440     /** Get & Update Next Event Number */
 441     InstSeqNum getNextEventNum()
 442     {
 443 #ifdef DEBUG
 444         return cpuEventNum++;
 445 #else
 446         return 0;
 447 #endif
 448     }
 449
 450     /** Register file accessors  */
 451     uint64_t readIntReg(int reg_idx, ThreadID tid);
 452
 453     FloatReg readFloatReg(int reg_idx, ThreadID tid);
 454
 455     FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
 456
 457     void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
 458
 459     void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
 460
 461     void setFloatRegBits(int reg_idx, FloatRegBits val,  ThreadID tid);
 462
 463     /** Reads a miscellaneous register. */
 464     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 465
 466     /** Reads a misc. register, including any side effects the read
 467      * might have as defined by the architecture.
 468      */
 469     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 470
 471     /** Sets a miscellaneous register. */
 472     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 473                             ThreadID tid = 0);
 474
 475     /** Sets a misc. register, including any side effects the write
 476      * might have as defined by the architecture.
 477      */
 478     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 479
 480     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 481      *  target thread
 482      */
 483     uint64_t readRegOtherThread(unsigned misc_reg,
 484                                 ThreadID tid = InvalidThreadID);
 485
 486     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 487      * target thread
 488      */
 489     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 490                            ThreadID tid);
 491
 492     /** Reads the commit PC of a specific thread. */
 493     uint64_t readPC(ThreadID tid);
 494
 495     /** Sets the commit PC of a specific thread. */
 496     void setPC(Addr new_PC, ThreadID tid);
 497
 498     /** Reads the next PC of a specific thread. */
 499     uint64_t readNextPC(ThreadID tid);
 500
 501     /** Sets the next PC of a specific thread. */
 502     void setNextPC(uint64_t val, ThreadID tid);
 503
 504     /** Reads the next NPC of a specific thread. */
 505     uint64_t readNextNPC(ThreadID tid);
 506
 507     /** Sets the next NPC of a specific thread. */
 508     void setNextNPC(uint64_t val, ThreadID tid);
 509
 510     /** Function to add instruction onto the head of the list of the
 511      *  instructions.  Used when new instructions are fetched.
 512      */
 513     ListIt addInst(DynInstPtr &inst);
 514
 515     /** Function to tell the CPU that an instruction has completed. */
 516     void instDone(DynInstPtr inst, ThreadID tid);
 517
 518     /** Add Instructions to the CPU Remove List*/
 519     void addToRemoveList(DynInstPtr &inst);
 520
 521     /** Remove an instruction from CPU */
 522     void removeInst(DynInstPtr &inst);
 523
 524     /** Remove all instructions younger than the given sequence number. */
 525     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 526
 527     /** Removes the instruction pointed to by the iterator. */
 528     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 529
 530     /** Cleans up all instructions on the instruction remove list. */
 531     void cleanUpRemovedInsts();
 532
 533     /** Cleans up all instructions on the request remove list. */
 534     void cleanUpRemovedReqs();
 535
 536     /** Cleans up all instructions on the CPU event remove list. */
 537     void cleanUpRemovedEvents();
 538
 539     /** Debug function to print all instructions on the list. */
 540     void dumpInsts();
 541
 542     /** Forwards an instruction read to the appropriate data
 543      *  resource (indexes into Resource Pool thru "dataPortIdx")
 544      */
 545     template <class T>
 546     Fault read(DynInstPtr inst, Addr addr, T &data, unsigned flags);
 547
 548     /** Forwards an instruction write. to the appropriate data
 549      *  resource (indexes into Resource Pool thru "dataPortIdx")
 550      */
 551     template <class T>
 552     Fault write(DynInstPtr inst, T data, Addr addr, unsigned flags,
 553                 uint64_t *write_res = NULL);
 554
 555     /** Forwards an instruction prefetch to the appropriate data
 556      *  resource (indexes into Resource Pool thru "dataPortIdx")
 557      */
 558     void prefetch(DynInstPtr inst);
 559
 560     /** Forwards an instruction writeHint to the appropriate data
 561      *  resource (indexes into Resource Pool thru "dataPortIdx")
 562      */
 563     void writeHint(DynInstPtr inst);
 564
 565     /** Executes a syscall.*/
 566     void syscall(int64_t callnum, ThreadID tid);
 567
 568   public:
 569     /** Per-Thread List of all the instructions in flight. */
 570     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 571
 572     /** List of all the instructions that will be removed at the end of this
 573      *  cycle.
 574      */
 575     std::queue<ListIt> removeList;
 576
 577     /** List of all the resource requests that will be removed at the end
 578      *  of this cycle.
 579      */
 580     std::queue<ResourceRequest*> reqRemoveList;
 581
 582     /** List of all the cpu event requests that will be removed at the end of
 583      *  the current cycle.
 584      */
 585     std::queue<Event*> cpuEventRemoveList;
 586
 587     /** Records if instructions need to be removed this cycle due to
 588      *  being retired or squashed.
 589      */
 590     bool removeInstsThisCycle;
 591
 592     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 593      * execution unit know, NOT to execute while the instruction is active.
 594      */
 595     bool nonSpecInstActive[ThePipeline::MaxThreads];
 596
 597     /** Instruction Seq. Num of current non-speculative instruction. */
 598     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 599
 600     /** Instruction Seq. Num of last instruction squashed in pipeline */
 601     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 602
 603     /** Last Cycle that the CPU squashed instruction end. */
 604     Tick lastSquashCycle[ThePipeline::MaxThreads];
 605
 606     std::list<ThreadID> fetchPriorityList;
 607
 608   protected:
 609     /** Active Threads List */
 610     std::list<ThreadID> activeThreads;
 611
 612     /** Current Threads List */
 613     std::list<ThreadID> currentThreads;
 614
 615     /** Suspended Threads List */
 616     std::list<ThreadID> suspendedThreads;
 617
 618     /** Thread Status Functions (Unused Currently) */
 619     bool isThreadInCPU(ThreadID tid);
 620     bool isThreadActive(ThreadID tid);
 621     bool isThreadSuspended(ThreadID tid);
 622     void addToCurrentThreads(ThreadID tid);
 623     void removeFromCurrentThreads(ThreadID tid);
 624
 625   private:
 626     /** The activity recorder; used to tell if the CPU has any
 627      * activity remaining or if it can go to idle and deschedule
 628      * itself.
 629      */
 630     ActivityRecorder activityRec;
 631
 632   public:
 633     /** Number of Active Threads in the CPU */
 634     ThreadID numActiveThreads() { return activeThreads.size(); }
 635
 636     /** Records that there was time buffer activity this cycle. */
 637     void activityThisCycle() { activityRec.activity(); }
 638
 639     /** Changes a stage's status to active within the activity recorder. */
 640     void activateStage(const int idx)
 641     { activityRec.activateStage(idx); }
 642
 643     /** Changes a stage's status to inactive within the activity recorder. */
 644     void deactivateStage(const int idx)
 645     { activityRec.deactivateStage(idx); }
 646
 647     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 648     void wakeCPU();
 649
 650 #if FULL_SYSTEM
 651     virtual void wakeup();
 652 #endif
 653
 654     /** Gets a free thread id. Use if thread ids change across system. */
 655     ThreadID getFreeTid();
 656
 657     // LL/SC debug functionality
 658     unsigned stCondFails;
 659
 660     unsigned readStCondFailures()
 661     { return stCondFails; }
 662
 663     unsigned setStCondFailures(unsigned st_fails)
 664     { return stCondFails = st_fails; }
 665
 666     /** Returns a pointer to a thread context. */
 667     ThreadContext *tcBase(ThreadID tid = 0)
 668     {
 669         return thread[tid]->getTC();
 670     }
 671
 672     /** Count the Total Instructions Committed in the CPU. */
 673     virtual Counter totalInstructions() const
 674     {
 675         Counter total(0);
 676
 677         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 678             total += thread[tid]->numInst;
 679
 680         return total;
 681     }
 682
 683 #if FULL_SYSTEM
 684     /** Pointer to the system. */
 685     System *system;
 686
 687     /** Pointer to physical memory. */
 688     PhysicalMemory *physmem;
 689 #endif
 690
 691     /** The global sequence number counter. */
 692     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 693
 694 #ifdef DEBUG
 695     /** The global event number counter. */
 696     InstSeqNum cpuEventNum;
 697
 698     /** Number of resource requests active in CPU **/
 699     unsigned resReqCount;
 700
 701     Stats::Scalar maxResReqCount;
 702 #endif
 703
 704     /** Counter of how many stages have completed switching out. */
 705     int switchCount;
 706
 707     /** Pointers to all of the threads in the CPU. */
 708     std::vector<Thread *> thread;
 709
 710     /** Pointer to the icache interface. */
 711     MemInterface *icacheInterface;
 712
 713     /** Pointer to the dcache interface. */
 714     MemInterface *dcacheInterface;
 715
 716     /** Whether or not the CPU should defer its registration. */
 717     bool deferRegistration;
 718
 719     /** Per-Stage Instruction Tracing */
 720     bool stageTracing;
 721
 722     /** Is there a context switch pending? */
 723     bool contextSwitch;
 724
 725     /** Threads Scheduled to Enter CPU */
 726     std::list<int> cpuWaitList;
 727
 728     /** The cycle that the CPU was last running, used for statistics. */
 729     Tick lastRunningCycle;
 730
 731     /** Number of Virtual Processors the CPU can process */
 732     unsigned numVirtProcs;
 733
 734     /** Update Thread , used for statistic purposes*/
 735     inline void tickThreadStats();
 736
 737     /** Per-Thread Tick */
 738     Stats::Vector threadCycles;
 739
 740     /** Tick for SMT */
 741     Stats::Scalar smtCycles;
 742
 743     /** Stat for total number of times the CPU is descheduled. */
 744     Stats::Scalar timesIdled;
 745
 746     /** Stat for total number of cycles the CPU spends descheduled. */
 747     Stats::Scalar idleCycles;
 748
 749     /** Stat for the number of committed instructions per thread. */
 750     Stats::Vector committedInsts;
 751
 752     /** Stat for the number of committed instructions per thread. */
 753     Stats::Vector smtCommittedInsts;
 754
 755     /** Stat for the total number of committed instructions. */
 756     Stats::Scalar totalCommittedInsts;
 757
 758     /** Stat for the CPI per thread. */
 759     Stats::Formula cpi;
 760
 761     /** Stat for the SMT-CPI per thread. */
 762     Stats::Formula smtCpi;
 763
 764     /** Stat for the total CPI. */
 765     Stats::Formula totalCpi;
 766
 767     /** Stat for the IPC per thread. */
 768     Stats::Formula ipc;
 769
 770     /** Stat for the total IPC. */
 771     Stats::Formula smtIpc;
 772
 773     /** Stat for the total IPC. */
 774     Stats::Formula totalIpc;
 775 };
 776
 777 #endif // __CPU_O3_CPU_HH__