src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "base/statistics.hh"
  43 #include "base/timebuf.hh"
  44 #include "config/full_system.hh"
  45 #include "cpu/activity.hh"
  46 #include "cpu/base.hh"
  47 #include "cpu/simple_thread.hh"
  48 #include "cpu/inorder/inorder_dyn_inst.hh"
  49 #include "cpu/inorder/pipeline_traits.hh"
  50 #include "cpu/inorder/pipeline_stage.hh"
  51 #include "cpu/inorder/thread_state.hh"
  52 #include "cpu/inorder/reg_dep_map.hh"
  53 #include "cpu/o3/dep_graph.hh"
  54 #include "cpu/o3/rename_map.hh"
  55 #include "mem/packet.hh"
  56 #include "mem/port.hh"
  57 #include "mem/request.hh"
  58 #include "sim/eventq.hh"
  59 #include "sim/process.hh"
  60
  61 class ThreadContext;
  62 class MemInterface;
  63 class MemObject;
  64 class Process;
  65 class ResourcePool;
  66
  67 class InOrderCPU : public BaseCPU
  68 {
  69
  70   protected:
  71     typedef ThePipeline::Params Params;
  72     typedef InOrderThreadState Thread;
  73
  74    //ISA TypeDefs
  75     typedef TheISA::IntReg IntReg;
  76     typedef TheISA::FloatReg FloatReg;
  77     typedef TheISA::FloatRegBits FloatRegBits;
  78     typedef TheISA::MiscReg MiscReg;
  79     typedef TheISA::RegFile RegFile;
  80
  81     //DynInstPtr TypeDefs
  82     typedef ThePipeline::DynInstPtr DynInstPtr;
  83     typedef std::list<DynInstPtr>::iterator ListIt;
  84
  85     //TimeBuffer TypeDefs
  86     typedef TimeBuffer<InterStageStruct> StageQueue;
  87
  88     friend class Resource;
  89
  90   public:
  91     /** Constructs a CPU with the given parameters. */
  92     InOrderCPU(Params *params);
  93
  94     /** CPU ID */
  95     int cpu_id;
  96
  97     /** Type of core that this is */
  98     std::string coreType;
  99
 100     int readCpuId() { return cpu_id; }
 101
 102     void setCpuId(int val) { cpu_id = val; }
 103
 104     Params *cpu_params;
 105
 106   public:
 107     enum Status {
 108         Running,
 109         Idle,
 110         Halted,
 111         Blocked,
 112         SwitchedOut
 113     };
 114
 115     /** Overall CPU status. */
 116     Status _status;
 117
 118   private:
 119     /** Define TickEvent for the CPU */
 120     class TickEvent : public Event
 121     {
 122       private:
 123         /** Pointer to the CPU. */
 124         InOrderCPU *cpu;
 125
 126       public:
 127         /** Constructs a tick event. */
 128         TickEvent(InOrderCPU *c);
 129
 130         /** Processes a tick event, calling tick() on the CPU. */
 131         void process();
 132
 133         /** Returns the description of the tick event. */
 134         const char *description();
 135     };
 136
 137     /** The tick event used for scheduling CPU ticks. */
 138     TickEvent tickEvent;
 139
 140     /** Schedule tick event, regardless of its current state. */
 141     void scheduleTickEvent(int delay)
 142     {
 143         if (tickEvent.squashed())
 144           mainEventQueue.reschedule(&tickEvent, nextCycle(curTick + ticks(delay)));
 145         else if (!tickEvent.scheduled())
 146           mainEventQueue.schedule(&tickEvent, nextCycle(curTick + ticks(delay)));
 147     }
 148
 149     /** Unschedule tick event, regardless of its current state. */
 150     void unscheduleTickEvent()
 151     {
 152         if (tickEvent.scheduled())
 153             tickEvent.squash();
 154     }
 155
 156   public:
 157     // List of Events That can be scheduled from
 158     // within the CPU.
 159     // NOTE(1): The Resource Pool also uses this event list
 160     // to schedule events broadcast to all resources interfaces
 161     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 162     // pool event.
 163     enum CPUEventType {
 164         ActivateThread,
 165         DeallocateThread,
 166         SuspendThread,
 167         DisableThreads,
 168         EnableThreads,
 169         DisableVPEs,
 170         EnableVPEs,
 171         Trap,
 172         InstGraduated,
 173         SquashAll,
 174         UpdatePCs,
 175         NumCPUEvents
 176     };
 177
 178     /** Define CPU Event */
 179     class CPUEvent : public Event
 180     {
 181       protected:
 182         InOrderCPU *cpu;
 183
 184       public:
 185         CPUEventType cpuEventType;
 186         unsigned tid;
 187         unsigned vpe;
 188         Fault fault;
 189
 190       public:
 191         /** Constructs a CPU event. */
 192         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 193                  unsigned _tid, unsigned _vpe);
 194
 195         /** Set Type of Event To Be Scheduled */
 196         void setEvent(CPUEventType e_type, Fault _fault, unsigned _tid, unsigned _vpe)
 197         {
 198             fault = _fault;
 199             cpuEventType = e_type;
 200             tid = _tid;
 201             vpe = _vpe;
 202         }
 203
 204         /** Processes a resource event. */
 205         virtual void process();
 206
 207         /** Returns the description of the resource event. */
 208         const char *description();
 209
 210         /** Schedule Event */
 211         void scheduleEvent(int delay);
 212
 213         /** Unschedule This Event */
 214         void unscheduleEvent();
 215     };
 216
 217     /** Schedule a CPU Event */
 218     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, unsigned tid,
 219                           unsigned vpe, unsigned delay = 0);
 220
 221   public:
 222     /** Interface between the CPU and CPU resources. */
 223     ResourcePool *resPool;
 224
 225     /** Instruction used to signify that there is no *real* instruction in buffer slot */
 226     DynInstPtr dummyBufferInst;
 227
 228     /** Used by resources to signify a denied access to a resource. */
 229     ResourceRequest *dummyReq;
 230
 231     /** Identifies the resource id that identifies a fetch
 232      * access unit.
 233      */
 234     unsigned fetchPortIdx;
 235
 236     /** Identifies the resource id that identifies a ITB       */
 237     unsigned itbIdx;
 238
 239     /** Identifies the resource id that identifies a data
 240      * access unit.
 241      */
 242     unsigned dataPortIdx;
 243
 244     /** Identifies the resource id that identifies a DTB       */
 245     unsigned dtbIdx;
 246
 247     /** The Pipeline Stages for the CPU */
 248     PipelineStage *pipelineStage[ThePipeline::NumStages];
 249
 250     /** Program Counters */
 251     TheISA::IntReg PC[ThePipeline::MaxThreads];
 252     TheISA::IntReg nextPC[ThePipeline::MaxThreads];
 253     TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
 254
 255     /** The Register File for the CPU */
 256     TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];;
 257     TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];;
 258     TheISA::MiscRegFile miscRegFile;
 259
 260     /** Dependency Tracker for Integer & Floating Point Regs */
 261     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 262
 263     /** Global communication structure */
 264     TimeBuffer<TimeStruct> timeBuffer;
 265
 266     /** Communication structure that sits in between pipeline stages */
 267     StageQueue *stageQueue[ThePipeline::NumStages-1];
 268
 269     TheISA::TLB *getITBPtr();
 270     TheISA::TLB *getDTBPtr();
 271
 272   public:
 273
 274     /** Registers statistics. */
 275     void regStats();
 276
 277     /** Ticks CPU, calling tick() on each stage, and checking the overall
 278      *  activity to see if the CPU should deschedule itself.
 279      */
 280     void tick();
 281
 282     /** Initialize the CPU */
 283     void init();
 284
 285     /** Reset State in the CPU */
 286     void reset();
 287
 288     /** Get a Memory Port */
 289     Port* getPort(const std::string &if_name, int idx = 0);
 290
 291     /** trap() - sets up a trap event on the cpuTraps to handle given fault.
 292      *  trapCPU() - Traps to handle given fault
 293      */
 294     void trap(Fault fault, unsigned tid, int delay = 0);
 295     void trapCPU(Fault fault, unsigned tid);
 296
 297     /** Setup CPU to insert a thread's context */
 298     void insertThread(unsigned tid);
 299
 300     /** Remove all of a thread's context from CPU */
 301     void removeThread(unsigned tid);
 302
 303     /** Add Thread to Active Threads List. */
 304     void activateContext(unsigned tid, int delay = 0);
 305     void activateThread(unsigned tid);
 306
 307     /** Remove Thread from Active Threads List */
 308     void suspendContext(unsigned tid, int delay = 0);
 309     void suspendThread(unsigned tid);
 310
 311     /** Remove Thread from Active Threads List &&
 312      *  Remove Thread Context from CPU.
 313      */
 314     void deallocateContext(unsigned tid, int delay = 0);
 315     void deallocateThread(unsigned tid);
 316     void deactivateThread(unsigned tid);
 317
 318     PipelineStage* getPipeStage(int stage_num);
 319
 320     int
 321     contextId()
 322     {
 323         hack_once("return a bogus context id");
 324         return 0;
 325     }
 326
 327     /** Remove Thread from Active Threads List &&
 328      *  Remove Thread Context from CPU.
 329      */
 330     void haltContext(unsigned tid, int delay = 0);
 331
 332     void removePipelineStalls(unsigned tid);
 333
 334     void squashThreadInPipeline(unsigned tid);
 335
 336     /// Notify the CPU to enable a virtual processor element.
 337     virtual void enableVirtProcElement(unsigned vpe);
 338     void enableVPEs(unsigned vpe);
 339
 340     /// Notify the CPU to disable a virtual processor element.
 341     virtual void disableVirtProcElement(unsigned tid, unsigned vpe);
 342     void disableVPEs(unsigned tid, unsigned vpe);
 343
 344     /// Notify the CPU that multithreading is enabled.
 345     virtual void enableMultiThreading(unsigned vpe);
 346     void enableThreads(unsigned vpe);
 347
 348     /// Notify the CPU that multithreading is disabled.
 349     virtual void disableMultiThreading(unsigned tid, unsigned vpe);
 350     void disableThreads(unsigned tid, unsigned vpe);
 351
 352     /** Activate a Thread When CPU Resources are Available. */
 353     void activateWhenReady(int tid);
 354
 355     /** Add or Remove a Thread Context in the CPU. */
 356     void doContextSwitch();
 357
 358     /** Update The Order In Which We Process Threads. */
 359     void updateThreadPriority();
 360
 361     /** Switches a Pipeline Stage to Active. (Unused currently) */
 362     void switchToActive(int stage_idx)
 363     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 364
 365     /** Get the current instruction sequence number, and increment it. */
 366     InstSeqNum getAndIncrementInstSeq(unsigned tid)
 367     { return globalSeqNum[tid]++; }
 368
 369     /** Get the current instruction sequence number, and increment it. */
 370     InstSeqNum nextInstSeqNum(unsigned tid)
 371     { return globalSeqNum[tid]; }
 372
 373     /** Increment Instruction Sequence Number */
 374     void incrInstSeqNum(unsigned tid)
 375     { globalSeqNum[tid]++; }
 376
 377     /** Set Instruction Sequence Number */
 378     void setInstSeqNum(unsigned tid, InstSeqNum seq_num)
 379     {
 380         globalSeqNum[tid] = seq_num;
 381     }
 382
 383     /** Get & Update Next Event Number */
 384     InstSeqNum getNextEventNum()
 385     {
 386         return cpuEventNum++;
 387     }
 388
 389     /** Get instruction asid. */
 390     int getInstAsid(unsigned tid)
 391     { return thread[tid]->getInstAsid(); }
 392
 393     /** Get data asid. */
 394     int getDataAsid(unsigned tid)
 395     { return thread[tid]->getDataAsid(); }
 396
 397     /** Register file accessors  */
 398     uint64_t readIntReg(int reg_idx, unsigned tid);
 399
 400     FloatReg readFloatReg(int reg_idx, unsigned tid,
 401                           int width = TheISA::SingleWidth);
 402
 403     FloatRegBits readFloatRegBits(int reg_idx, unsigned tid,
 404                                   int width = TheISA::SingleWidth);
 405
 406     void setIntReg(int reg_idx, uint64_t val, unsigned tid);
 407
 408     void setFloatReg(int reg_idx, FloatReg val,  unsigned tid,
 409                      int width = TheISA::SingleWidth);
 410
 411     void setFloatRegBits(int reg_idx, FloatRegBits val,  unsigned tid,
 412                          int width = TheISA::SingleWidth);
 413
 414     /** Reads a miscellaneous register. */
 415     MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0);
 416
 417     /** Reads a misc. register, including any side effects the read
 418      * might have as defined by the architecture.
 419      */
 420     MiscReg readMiscReg(int misc_reg, unsigned tid = 0);
 421
 422     /** Sets a miscellaneous register. */
 423     void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0);
 424
 425     /** Sets a misc. register, including any side effects the write
 426      * might have as defined by the architecture.
 427      */
 428     void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0);
 429
 430     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 431      *  target thread
 432      */
 433     uint64_t readRegOtherThread(unsigned misc_reg, unsigned tid = -1);
 434
 435     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 436      * target thread
 437      */
 438     void setRegOtherThread(unsigned misc_reg, const MiscReg &val, unsigned tid);
 439
 440     /** Reads the commit PC of a specific thread. */
 441     uint64_t readPC(unsigned tid);
 442
 443     /** Sets the commit PC of a specific thread. */
 444     void setPC(Addr new_PC, unsigned tid);
 445
 446     /** Reads the next PC of a specific thread. */
 447     uint64_t readNextPC(unsigned tid);
 448
 449     /** Sets the next PC of a specific thread. */
 450     void setNextPC(uint64_t val, unsigned tid);
 451
 452     /** Reads the next NPC of a specific thread. */
 453     uint64_t readNextNPC(unsigned tid);
 454
 455     /** Sets the next NPC of a specific thread. */
 456     void setNextNPC(uint64_t val, unsigned tid);
 457
 458     /** Function to add instruction onto the head of the list of the
 459      *  instructions.  Used when new instructions are fetched.
 460      */
 461     ListIt addInst(DynInstPtr &inst);
 462
 463     /** Function to tell the CPU that an instruction has completed. */
 464     void instDone(DynInstPtr inst, unsigned tid);
 465
 466     /** Add Instructions to the CPU Remove List*/
 467     void addToRemoveList(DynInstPtr &inst);
 468
 469     /** Remove an instruction from CPU */
 470     void removeInst(DynInstPtr &inst);
 471
 472     /** Remove all instructions younger than the given sequence number. */
 473     void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
 474
 475     /** Removes the instruction pointed to by the iterator. */
 476     inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
 477
 478     /** Cleans up all instructions on the instruction remove list. */
 479     void cleanUpRemovedInsts();
 480
 481     /** Cleans up all instructions on the request remove list. */
 482     void cleanUpRemovedReqs();
 483
 484     /** Cleans up all instructions on the CPU event remove list. */
 485     void cleanUpRemovedEvents();
 486
 487     /** Debug function to print all instructions on the list. */
 488     void dumpInsts();
 489
 490     /** Forwards an instruction read to the appropriate data
 491      *  resource (indexes into Resource Pool thru "dataPortIdx")
 492      */
 493     Fault read(DynInstPtr inst);
 494
 495     /** Forwards an instruction write. to the appropriate data
 496      *  resource (indexes into Resource Pool thru "dataPortIdx")
 497      */
 498     Fault write(DynInstPtr inst);
 499
 500     /** Executes a syscall.*/
 501     void syscall(int64_t callnum, int tid);
 502
 503   public:
 504     /** Per-Thread List of all the instructions in flight. */
 505     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 506
 507     /** List of all the instructions that will be removed at the end of this
 508      *  cycle.
 509      */
 510     std::queue<ListIt> removeList;
 511
 512     /** List of all the resource requests that will be removed at the end of this
 513      *  cycle.
 514      */
 515     std::queue<ResourceRequest*> reqRemoveList;
 516
 517     /** List of all the cpu event requests that will be removed at the end of
 518      *  the current cycle.
 519      */
 520     std::queue<Event*> cpuEventRemoveList;
 521
 522     /** Records if instructions need to be removed this cycle due to
 523      *  being retired or squashed.
 524      */
 525     bool removeInstsThisCycle;
 526
 527     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 528      * execution unit know, NOT to execute while the instruction is active.
 529      */
 530     bool nonSpecInstActive[ThePipeline::MaxThreads];
 531
 532     /** Instruction Seq. Num of current non-speculative instruction. */
 533     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 534
 535     /** Instruction Seq. Num of last instruction squashed in pipeline */
 536     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 537
 538     /** Last Cycle that the CPU squashed instruction end. */
 539     Tick lastSquashCycle[ThePipeline::MaxThreads];
 540
 541     std::list<unsigned> fetchPriorityList;
 542
 543   protected:
 544     /** Active Threads List */
 545     std::list<unsigned> activeThreads;
 546
 547     /** Current Threads List */
 548     std::list<unsigned> currentThreads;
 549
 550     /** Suspended Threads List */
 551     std::list<unsigned> suspendedThreads;
 552
 553     /** Thread Status Functions (Unused Currently) */
 554     bool isThreadInCPU(unsigned tid);
 555     bool isThreadActive(unsigned tid);
 556     bool isThreadSuspended(unsigned tid);
 557     void addToCurrentThreads(unsigned tid);
 558     void removeFromCurrentThreads(unsigned tid);
 559
 560   private:
 561     /** The activity recorder; used to tell if the CPU has any
 562      * activity remaining or if it can go to idle and deschedule
 563      * itself.
 564      */
 565     ActivityRecorder activityRec;
 566
 567   public:
 568     void readFunctional(Addr addr, uint32_t &buffer);
 569
 570     /** Number of Active Threads in the CPU */
 571     int numActiveThreads() { return activeThreads.size(); }
 572
 573     /** Records that there was time buffer activity this cycle. */
 574     void activityThisCycle() { activityRec.activity(); }
 575
 576     /** Changes a stage's status to active within the activity recorder. */
 577     void activateStage(const int idx)
 578     { activityRec.activateStage(idx); }
 579
 580     /** Changes a stage's status to inactive within the activity recorder. */
 581     void deactivateStage(const int idx)
 582     { activityRec.deactivateStage(idx); }
 583
 584     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 585     void wakeCPU();
 586
 587     /** Gets a free thread id. Use if thread ids change across system. */
 588     int getFreeTid();
 589
 590     // LL/SC debug functionality
 591     unsigned stCondFails;
 592     unsigned readStCondFailures() { return stCondFails; }
 593     unsigned setStCondFailures(unsigned st_fails) { return stCondFails = st_fails; }
 594
 595     /** Returns a pointer to a thread context. */
 596     ThreadContext *tcBase(unsigned tid = 0)
 597     {
 598         return thread[tid]->getTC();
 599     }
 600
 601     /** Count the Total Instructions Committed in the CPU. */
 602     virtual Counter totalInstructions() const
 603     {
 604         Counter total(0);
 605
 606         for (int i=0; i < thread.size(); i++)
 607             total += thread[i]->numInst;
 608
 609         return total;
 610     }
 611
 612     /** The global sequence number counter. */
 613     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 614
 615     /** The global event number counter. */
 616     InstSeqNum cpuEventNum;
 617
 618     /** Counter of how many stages have completed switching out. */
 619     int switchCount;
 620
 621     /** Pointers to all of the threads in the CPU. */
 622     std::vector<Thread *> thread;
 623
 624     /** Pointer to the icache interface. */
 625     MemInterface *icacheInterface;
 626
 627     /** Pointer to the dcache interface. */
 628     MemInterface *dcacheInterface;
 629
 630     /** Whether or not the CPU should defer its registration. */
 631     bool deferRegistration;
 632
 633     /** Per-Stage Instruction Tracing */
 634     bool stageTracing;
 635
 636     /** Is there a context switch pending? */
 637     bool contextSwitch;
 638
 639     /** Threads Scheduled to Enter CPU */
 640     std::list<int> cpuWaitList;
 641
 642     /** The cycle that the CPU was last running, used for statistics. */
 643     Tick lastRunningCycle;
 644
 645     /** Number of Threads the CPU can process */
 646     unsigned numThreads;
 647
 648     /** Number of Virtual Processors the CPU can process */
 649     unsigned numVirtProcs;
 650
 651     /** Update Thread , used for statistic purposes*/
 652     inline void tickThreadStats();
 653
 654     /** Per-Thread Tick */
 655     Stats::Vector threadCycles;
 656
 657     /** Tick for SMT */
 658     Stats::Scalar smtCycles;
 659
 660     /** Stat for total number of times the CPU is descheduled. */
 661     Stats::Scalar timesIdled;
 662
 663     /** Stat for total number of cycles the CPU spends descheduled. */
 664     Stats::Scalar idleCycles;
 665
 666     /** Stat for the number of committed instructions per thread. */
 667     Stats::Vector committedInsts;
 668
 669     /** Stat for the number of committed instructions per thread. */
 670     Stats::Vector smtCommittedInsts;
 671
 672     /** Stat for the total number of committed instructions. */
 673     Stats::Scalar totalCommittedInsts;
 674
 675     /** Stat for the CPI per thread. */
 676     Stats::Formula cpi;
 677
 678     /** Stat for the SMT-CPI per thread. */
 679     Stats::Formula smtCpi;
 680
 681     /** Stat for the total CPI. */
 682     Stats::Formula totalCpi;
 683
 684     /** Stat for the IPC per thread. */
 685     Stats::Formula ipc;
 686
 687     /** Stat for the total IPC. */
 688     Stats::Formula smtIpc;
 689
 690     /** Stat for the total IPC. */
 691     Stats::Formula totalIpc;
 692 };
 693
 694 #endif // __CPU_O3_CPU_HH__